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Merge git://git.kernel.org/pub/scm/linux/kernel/git/rusty/linux-2.6-for-linus
[deliverable/linux.git] / arch / arm / mach-at91 / at91cap9_devices.c
CommitLineData
2b3b3516
AV		 1/*
2 * arch/arm/mach-at91/at91cap9_devices.c
3 *
4 * Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
5 * Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
6 * Copyright (C) 2007 Atmel Corporation.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 */
14#include <asm/mach/arch.h>
15#include <asm/mach/map.h>
16
17#include <linux/dma-mapping.h>
18#include <linux/platform_device.h>
11aadac4 19#include <linux/i2c-gpio.h>
2b3b3516
AV		 20
21#include <video/atmel_lcdc.h>
22
a09e64fb
RK		 23#include <mach/board.h>
24#include <mach/gpio.h>
25#include <mach/at91cap9.h>
26#include <mach/at91cap9_matrix.h>
27#include <mach/at91sam9_smc.h>
2b3b3516
AV		 28
29#include "generic.h"
30
31
32/* --------------------------------------------------------------------
33 * USB Host
34 * -------------------------------------------------------------------- */
35
36#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
37static u64 ohci_dmamask = DMA_BIT_MASK(32);
38static struct at91_usbh_data usbh_data;
39
40static struct resource usbh_resources[] = {
41 [0] = {
42 .start = AT91CAP9_UHP_BASE,
43 .end = AT91CAP9_UHP_BASE + SZ_1M - 1,
44 .flags = IORESOURCE_MEM,
45 },
46 [1] = {
47 .start = AT91CAP9_ID_UHP,
48 .end = AT91CAP9_ID_UHP,
49 .flags = IORESOURCE_IRQ,
50 },
51};
52
53static struct platform_device at91_usbh_device = {
54 .name = "at91_ohci",
55 .id = -1,
56 .dev = {
57 .dma_mask = &ohci_dmamask,
58 .coherent_dma_mask = DMA_BIT_MASK(32),
59 .platform_data = &usbh_data,
60 },
61 .resource = usbh_resources,
62 .num_resources = ARRAY_SIZE(usbh_resources),
63};
64
65void __init at91_add_device_usbh(struct at91_usbh_data *data)
66{
67 int i;
68
69 if (!data)
70 return;
71
72 /* Enable VBus control for UHP ports */
73 for (i = 0; i < data->ports; i++) {
74 if (data->vbus_pin[i])
75 at91_set_gpio_output(data->vbus_pin[i], 0);
76 }
77
78 usbh_data = *data;
79 platform_device_register(&at91_usbh_device);
80}
81#else
82void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
83#endif
84
85
7c8cf665
SP		 86/* --------------------------------------------------------------------
87 * USB HS Device (Gadget)
88 * -------------------------------------------------------------------- */
89
90#if defined(CONFIG_USB_GADGET_ATMEL_USBA) || defined(CONFIG_USB_GADGET_ATMEL_USBA_MODULE)
91
92static struct resource usba_udc_resources[] = {
93 [0] = {
94 .start = AT91CAP9_UDPHS_FIFO,
95 .end = AT91CAP9_UDPHS_FIFO + SZ_512K - 1,
96 .flags = IORESOURCE_MEM,
97 },
98 [1] = {
99 .start = AT91CAP9_BASE_UDPHS,
100 .end = AT91CAP9_BASE_UDPHS + SZ_1K - 1,
101 .flags = IORESOURCE_MEM,
102 },
103 [2] = {
104 .start = AT91CAP9_ID_UDPHS,
105 .end = AT91CAP9_ID_UDPHS,
106 .flags = IORESOURCE_IRQ,
107 },
108};
109
110#define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
111 [idx] = { \
112 .name = nam, \
113 .index = idx, \
114 .fifo_size = maxpkt, \
115 .nr_banks = maxbk, \
116 .can_dma = dma, \
117 .can_isoc = isoc, \
118 }
119
120static struct usba_ep_data usba_udc_ep[] = {
121 EP("ep0", 0, 64, 1, 0, 0),
122 EP("ep1", 1, 1024, 3, 1, 1),
123 EP("ep2", 2, 1024, 3, 1, 1),
124 EP("ep3", 3, 1024, 2, 1, 1),
125 EP("ep4", 4, 1024, 2, 1, 1),
126 EP("ep5", 5, 1024, 2, 1, 0),
127 EP("ep6", 6, 1024, 2, 1, 0),
128 EP("ep7", 7, 1024, 2, 0, 0),
129};
130
131#undef EP
132
133/*
134 * pdata doesn't have room for any endpoints, so we need to
135 * append room for the ones we need right after it.
136 */
137static struct {
138 struct usba_platform_data pdata;
139 struct usba_ep_data ep[8];
140} usba_udc_data;
141
142static struct platform_device at91_usba_udc_device = {
143 .name = "atmel_usba_udc",
144 .id = -1,
145 .dev = {
146 .platform_data = &usba_udc_data.pdata,
147 },
148 .resource = usba_udc_resources,
149 .num_resources = ARRAY_SIZE(usba_udc_resources),
150};
151
152void __init at91_add_device_usba(struct usba_platform_data *data)
153{
154 at91_sys_write(AT91_MATRIX_UDPHS, AT91_MATRIX_SELECT_UDPHS |
155 AT91_MATRIX_UDPHS_BYPASS_LOCK);
156
157 /*
158 * Invalid pins are 0 on AT91, but the usba driver is shared
159 * with AVR32, which use negative values instead. Once/if
160 * gpio_is_valid() is ported to AT91, revisit this code.
161 */
162 usba_udc_data.pdata.vbus_pin = -EINVAL;
163 usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
164 memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));;
165
166 if (data && data->vbus_pin > 0) {
167 at91_set_gpio_input(data->vbus_pin, 0);
168 at91_set_deglitch(data->vbus_pin, 1);
169 usba_udc_data.pdata.vbus_pin = data->vbus_pin;
170 }
171
172 /* Pullup pin is handled internally by USB device peripheral */
173
174 /* Clocks */
175 at91_clock_associate("utmi_clk", &at91_usba_udc_device.dev, "hclk");
176 at91_clock_associate("udphs_clk", &at91_usba_udc_device.dev, "pclk");
177
178 platform_device_register(&at91_usba_udc_device);
179}
180#else
181void __init at91_add_device_usba(struct usba_platform_data *data) {}
182#endif
183
184
2b3b3516
AV		 185/* --------------------------------------------------------------------
186 * Ethernet
187 * -------------------------------------------------------------------- */
188
189#if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
190static u64 eth_dmamask = DMA_BIT_MASK(32);
191static struct at91_eth_data eth_data;
192
193static struct resource eth_resources[] = {
194 [0] = {
195 .start = AT91CAP9_BASE_EMAC,
196 .end = AT91CAP9_BASE_EMAC + SZ_16K - 1,
197 .flags = IORESOURCE_MEM,
198 },
199 [1] = {
200 .start = AT91CAP9_ID_EMAC,
201 .end = AT91CAP9_ID_EMAC,
202 .flags = IORESOURCE_IRQ,
203 },
204};
205
206static struct platform_device at91cap9_eth_device = {
207 .name = "macb",
208 .id = -1,
209 .dev = {
210 .dma_mask = &eth_dmamask,
211 .coherent_dma_mask = DMA_BIT_MASK(32),
212 .platform_data = &eth_data,
213 },
214 .resource = eth_resources,
215 .num_resources = ARRAY_SIZE(eth_resources),
216};
217
218void __init at91_add_device_eth(struct at91_eth_data *data)
219{
220 if (!data)
221 return;
222
223 if (data->phy_irq_pin) {
224 at91_set_gpio_input(data->phy_irq_pin, 0);
225 at91_set_deglitch(data->phy_irq_pin, 1);
226 }
227
228 /* Pins used for MII and RMII */
229 at91_set_A_periph(AT91_PIN_PB21, 0); /* ETXCK_EREFCK */
230 at91_set_A_periph(AT91_PIN_PB22, 0); /* ERXDV */
231 at91_set_A_periph(AT91_PIN_PB25, 0); /* ERX0 */
232 at91_set_A_periph(AT91_PIN_PB26, 0); /* ERX1 */
233 at91_set_A_periph(AT91_PIN_PB27, 0); /* ERXER */
234 at91_set_A_periph(AT91_PIN_PB28, 0); /* ETXEN */
235 at91_set_A_periph(AT91_PIN_PB23, 0); /* ETX0 */
236 at91_set_A_periph(AT91_PIN_PB24, 0); /* ETX1 */
237 at91_set_A_periph(AT91_PIN_PB30, 0); /* EMDIO */
238 at91_set_A_periph(AT91_PIN_PB29, 0); /* EMDC */
239
240 if (!data->is_rmii) {
241 at91_set_B_periph(AT91_PIN_PC25, 0); /* ECRS */
242 at91_set_B_periph(AT91_PIN_PC26, 0); /* ECOL */
243 at91_set_B_periph(AT91_PIN_PC22, 0); /* ERX2 */
244 at91_set_B_periph(AT91_PIN_PC23, 0); /* ERX3 */
245 at91_set_B_periph(AT91_PIN_PC27, 0); /* ERXCK */
246 at91_set_B_periph(AT91_PIN_PC20, 0); /* ETX2 */
247 at91_set_B_periph(AT91_PIN_PC21, 0); /* ETX3 */
248 at91_set_B_periph(AT91_PIN_PC24, 0); /* ETXER */
249 }
250
251 eth_data = *data;
252 platform_device_register(&at91cap9_eth_device);
253}
254#else
255void __init at91_add_device_eth(struct at91_eth_data *data) {}
256#endif
257
258
259/* --------------------------------------------------------------------
260 * MMC / SD
261 * -------------------------------------------------------------------- */
262
263#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
264static u64 mmc_dmamask = DMA_BIT_MASK(32);
265static struct at91_mmc_data mmc0_data, mmc1_data;
266
267static struct resource mmc0_resources[] = {
268 [0] = {
269 .start = AT91CAP9_BASE_MCI0,
270 .end = AT91CAP9_BASE_MCI0 + SZ_16K - 1,
271 .flags = IORESOURCE_MEM,
272 },
273 [1] = {
274 .start = AT91CAP9_ID_MCI0,
275 .end = AT91CAP9_ID_MCI0,
276 .flags = IORESOURCE_IRQ,
277 },
278};
279
280static struct platform_device at91cap9_mmc0_device = {
281 .name = "at91_mci",
282 .id = 0,
283 .dev = {
284 .dma_mask = &mmc_dmamask,
285 .coherent_dma_mask = DMA_BIT_MASK(32),
286 .platform_data = &mmc0_data,
287 },
288 .resource = mmc0_resources,
289 .num_resources = ARRAY_SIZE(mmc0_resources),
290};
291
292static struct resource mmc1_resources[] = {
293 [0] = {
294 .start = AT91CAP9_BASE_MCI1,
295 .end = AT91CAP9_BASE_MCI1 + SZ_16K - 1,
296 .flags = IORESOURCE_MEM,
297 },
298 [1] = {
299 .start = AT91CAP9_ID_MCI1,
300 .end = AT91CAP9_ID_MCI1,
301 .flags = IORESOURCE_IRQ,
302 },
303};
304
305static struct platform_device at91cap9_mmc1_device = {
306 .name = "at91_mci",
307 .id = 1,
308 .dev = {
309 .dma_mask = &mmc_dmamask,
310 .coherent_dma_mask = DMA_BIT_MASK(32),
311 .platform_data = &mmc1_data,
312 },
313 .resource = mmc1_resources,
314 .num_resources = ARRAY_SIZE(mmc1_resources),
315};
316
317void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
318{
319 if (!data)
320 return;
321
322 /* input/irq */
323 if (data->det_pin) {
324 at91_set_gpio_input(data->det_pin, 1);
325 at91_set_deglitch(data->det_pin, 1);
326 }
327 if (data->wp_pin)
328 at91_set_gpio_input(data->wp_pin, 1);
329 if (data->vcc_pin)
330 at91_set_gpio_output(data->vcc_pin, 0);
331
332 if (mmc_id == 0) { /* MCI0 */
333 /* CLK */
334 at91_set_A_periph(AT91_PIN_PA2, 0);
335
336 /* CMD */
337 at91_set_A_periph(AT91_PIN_PA1, 1);
338
339 /* DAT0, maybe DAT1..DAT3 */
340 at91_set_A_periph(AT91_PIN_PA0, 1);
341 if (data->wire4) {
342 at91_set_A_periph(AT91_PIN_PA3, 1);
343 at91_set_A_periph(AT91_PIN_PA4, 1);
344 at91_set_A_periph(AT91_PIN_PA5, 1);
345 }
346
347 mmc0_data = *data;
fb8b131b 348 at91_clock_associate("mci0_clk", &at91cap9_mmc0_device.dev, "mci_clk");
2b3b3516
AV		 349 platform_device_register(&at91cap9_mmc0_device);
350 } else { /* MCI1 */
351 /* CLK */
352 at91_set_A_periph(AT91_PIN_PA16, 0);
353
354 /* CMD */
355 at91_set_A_periph(AT91_PIN_PA17, 1);
356
357 /* DAT0, maybe DAT1..DAT3 */
358 at91_set_A_periph(AT91_PIN_PA18, 1);
359 if (data->wire4) {
360 at91_set_A_periph(AT91_PIN_PA19, 1);
361 at91_set_A_periph(AT91_PIN_PA20, 1);
362 at91_set_A_periph(AT91_PIN_PA21, 1);
363 }
364
365 mmc1_data = *data;
366 at91_clock_associate("mci1_clk", &at91cap9_mmc1_device.dev, "mci_clk");
367 platform_device_register(&at91cap9_mmc1_device);
368 }
369}
370#else
371void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
372#endif
373
374
375/* --------------------------------------------------------------------
376 * NAND / SmartMedia
377 * -------------------------------------------------------------------- */
378
f6ed6f78 379#if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
3c3796cc 380static struct atmel_nand_data nand_data;
2b3b3516
AV		 381
382#define NAND_BASE AT91_CHIPSELECT_3
383
384static struct resource nand_resources[] = {
d7a2415f 385 [0] = {
2b3b3516
AV		 386 .start = NAND_BASE,
387 .end = NAND_BASE + SZ_256M - 1,
388 .flags = IORESOURCE_MEM,
d7a2415f
AV		 389 },
390 [1] = {
391 .start = AT91_BASE_SYS + AT91_ECC,
392 .end = AT91_BASE_SYS + AT91_ECC + SZ_512 - 1,
393 .flags = IORESOURCE_MEM,
2b3b3516
AV		 394 }
395};
396
397static struct platform_device at91cap9_nand_device = {
3c3796cc 398 .name = "atmel_nand",
2b3b3516
AV		 399 .id = -1,
400 .dev = {
401 .platform_data = &nand_data,
402 },
403 .resource = nand_resources,
404 .num_resources = ARRAY_SIZE(nand_resources),
405};
406
3c3796cc 407void __init at91_add_device_nand(struct atmel_nand_data *data)
2b3b3516
AV		 408{
409 unsigned long csa, mode;
410
411 if (!data)
412 return;
413
414 csa = at91_sys_read(AT91_MATRIX_EBICSA);
415 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA | AT91_MATRIX_EBI_VDDIOMSEL_3_3V);
416
417 /* set the bus interface characteristics */
418 at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(1)
419 | AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(1));
420
421 at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(6)
422 | AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(6));
423
424 at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(8) | AT91_SMC_NRDCYCLE_(8));
425
426 if (data->bus_width_16)
427 mode = AT91_SMC_DBW_16;
428 else
429 mode = AT91_SMC_DBW_8;
430 at91_sys_write(AT91_SMC_MODE(3), mode | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(1));
431
432 /* enable pin */
433 if (data->enable_pin)
434 at91_set_gpio_output(data->enable_pin, 1);
435
436 /* ready/busy pin */
437 if (data->rdy_pin)
438 at91_set_gpio_input(data->rdy_pin, 1);
439
440 /* card detect pin */
441 if (data->det_pin)
442 at91_set_gpio_input(data->det_pin, 1);
443
444 nand_data = *data;
445 platform_device_register(&at91cap9_nand_device);
446}
447#else
3c3796cc 448void __init at91_add_device_nand(struct atmel_nand_data *data) {}
2b3b3516
AV		 449#endif
450
11aadac4 451
2b3b3516
AV		 452/* --------------------------------------------------------------------
453 * TWI (i2c)
454 * -------------------------------------------------------------------- */
455
456/*
457 * Prefer the GPIO code since the TWI controller isn't robust
458 * (gets overruns and underruns under load) and can only issue
459 * repeated STARTs in one scenario (the driver doesn't yet handle them).
460 */
461#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
462
463static struct i2c_gpio_platform_data pdata = {
464 .sda_pin = AT91_PIN_PB4,
465 .sda_is_open_drain = 1,
466 .scl_pin = AT91_PIN_PB5,
467 .scl_is_open_drain = 1,
468 .udelay = 2, /* ~100 kHz */
469};
470
471static struct platform_device at91cap9_twi_device = {
472 .name = "i2c-gpio",
473 .id = -1,
474 .dev.platform_data = &pdata,
475};
476
477void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
478{
479 at91_set_GPIO_periph(AT91_PIN_PB4, 1); /* TWD (SDA) */
480 at91_set_multi_drive(AT91_PIN_PB4, 1);
481
482 at91_set_GPIO_periph(AT91_PIN_PB5, 1); /* TWCK (SCL) */
483 at91_set_multi_drive(AT91_PIN_PB5, 1);
484
485 i2c_register_board_info(0, devices, nr_devices);
486 platform_device_register(&at91cap9_twi_device);
487}
488
489#elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
490
491static struct resource twi_resources[] = {
492 [0] = {
493 .start = AT91CAP9_BASE_TWI,
494 .end = AT91CAP9_BASE_TWI + SZ_16K - 1,
495 .flags = IORESOURCE_MEM,
496 },
497 [1] = {
498 .start = AT91CAP9_ID_TWI,
499 .end = AT91CAP9_ID_TWI,
500 .flags = IORESOURCE_IRQ,
501 },
502};
503
504static struct platform_device at91cap9_twi_device = {
505 .name = "at91_i2c",
506 .id = -1,
507 .resource = twi_resources,
508 .num_resources = ARRAY_SIZE(twi_resources),
509};
510
511void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
512{
513 /* pins used for TWI interface */
514 at91_set_B_periph(AT91_PIN_PB4, 0); /* TWD */
515 at91_set_multi_drive(AT91_PIN_PB4, 1);
516
517 at91_set_B_periph(AT91_PIN_PB5, 0); /* TWCK */
518 at91_set_multi_drive(AT91_PIN_PB5, 1);
519
520 i2c_register_board_info(0, devices, nr_devices);
521 platform_device_register(&at91cap9_twi_device);
522}
523#else
524void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
525#endif
526
527/* --------------------------------------------------------------------
528 * SPI
529 * -------------------------------------------------------------------- */
530
531#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
532static u64 spi_dmamask = DMA_BIT_MASK(32);
533
534static struct resource spi0_resources[] = {
535 [0] = {
536 .start = AT91CAP9_BASE_SPI0,
537 .end = AT91CAP9_BASE_SPI0 + SZ_16K - 1,
538 .flags = IORESOURCE_MEM,
539 },
540 [1] = {
541 .start = AT91CAP9_ID_SPI0,
542 .end = AT91CAP9_ID_SPI0,
543 .flags = IORESOURCE_IRQ,
544 },
545};
546
547static struct platform_device at91cap9_spi0_device = {
548 .name = "atmel_spi",
549 .id = 0,
550 .dev = {
551 .dma_mask = &spi_dmamask,
552 .coherent_dma_mask = DMA_BIT_MASK(32),
553 },
554 .resource = spi0_resources,
555 .num_resources = ARRAY_SIZE(spi0_resources),
556};
557
558static const unsigned spi0_standard_cs[4] = { AT91_PIN_PA5, AT91_PIN_PA3, AT91_PIN_PD0, AT91_PIN_PD1 };
559
560static struct resource spi1_resources[] = {
561 [0] = {
562 .start = AT91CAP9_BASE_SPI1,
563 .end = AT91CAP9_BASE_SPI1 + SZ_16K - 1,
564 .flags = IORESOURCE_MEM,
565 },
566 [1] = {
567 .start = AT91CAP9_ID_SPI1,
568 .end = AT91CAP9_ID_SPI1,
569 .flags = IORESOURCE_IRQ,
570 },
571};
572
573static struct platform_device at91cap9_spi1_device = {
574 .name = "atmel_spi",
575 .id = 1,
576 .dev = {
577 .dma_mask = &spi_dmamask,
578 .coherent_dma_mask = DMA_BIT_MASK(32),
579 },
580 .resource = spi1_resources,
581 .num_resources = ARRAY_SIZE(spi1_resources),
582};
583
584static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB15, AT91_PIN_PB16, AT91_PIN_PB17, AT91_PIN_PB18 };
585
586void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
587{
588 int i;
589 unsigned long cs_pin;
590 short enable_spi0 = 0;
591 short enable_spi1 = 0;
592
593 /* Choose SPI chip-selects */
594 for (i = 0; i < nr_devices; i++) {
595 if (devices[i].controller_data)
596 cs_pin = (unsigned long) devices[i].controller_data;
597 else if (devices[i].bus_num == 0)
598 cs_pin = spi0_standard_cs[devices[i].chip_select];
599 else
600 cs_pin = spi1_standard_cs[devices[i].chip_select];
601
602 if (devices[i].bus_num == 0)
603 enable_spi0 = 1;
604 else
605 enable_spi1 = 1;
606
607 /* enable chip-select pin */
608 at91_set_gpio_output(cs_pin, 1);
609
610 /* pass chip-select pin to driver */
611 devices[i].controller_data = (void *) cs_pin;
612 }
613
614 spi_register_board_info(devices, nr_devices);
615
616 /* Configure SPI bus(es) */
617 if (enable_spi0) {
618 at91_set_B_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
619 at91_set_B_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
620 at91_set_B_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */
621
622 at91_clock_associate("spi0_clk", &at91cap9_spi0_device.dev, "spi_clk");
623 platform_device_register(&at91cap9_spi0_device);
624 }
625 if (enable_spi1) {
626 at91_set_A_periph(AT91_PIN_PB12, 0); /* SPI1_MISO */
627 at91_set_A_periph(AT91_PIN_PB13, 0); /* SPI1_MOSI */
628 at91_set_A_periph(AT91_PIN_PB14, 0); /* SPI1_SPCK */
629
630 at91_clock_associate("spi1_clk", &at91cap9_spi1_device.dev, "spi_clk");
631 platform_device_register(&at91cap9_spi1_device);
632 }
633}
634#else
635void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
636#endif
637
638
e5f40bfa
AV		 639/* --------------------------------------------------------------------
640 * Timer/Counter block
641 * -------------------------------------------------------------------- */
642
643#ifdef CONFIG_ATMEL_TCLIB
644
645static struct resource tcb_resources[] = {
646 [0] = {
647 .start = AT91CAP9_BASE_TCB0,
648 .end = AT91CAP9_BASE_TCB0 + SZ_16K - 1,
649 .flags = IORESOURCE_MEM,
650 },
651 [1] = {
652 .start = AT91CAP9_ID_TCB,
653 .end = AT91CAP9_ID_TCB,
654 .flags = IORESOURCE_IRQ,
655 },
656};
657
658static struct platform_device at91cap9_tcb_device = {
659 .name = "atmel_tcb",
660 .id = 0,
661 .resource = tcb_resources,
662 .num_resources = ARRAY_SIZE(tcb_resources),
663};
664
665static void __init at91_add_device_tc(void)
666{
667 /* this chip has one clock and irq for all three TC channels */
668 at91_clock_associate("tcb_clk", &at91cap9_tcb_device.dev, "t0_clk");
669 platform_device_register(&at91cap9_tcb_device);
670}
671#else
672static void __init at91_add_device_tc(void) { }
673#endif
674
675
2b3b3516
AV		 676/* --------------------------------------------------------------------
677 * RTT
678 * -------------------------------------------------------------------- */
679
4fd9212c
AV		 680static struct resource rtt_resources[] = {
681 {
682 .start = AT91_BASE_SYS + AT91_RTT,
683 .end = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1,
684 .flags = IORESOURCE_MEM,
685 }
686};
687
2b3b3516
AV		 688static struct platform_device at91cap9_rtt_device = {
689 .name = "at91_rtt",
4fd9212c
AV		 690 .id = 0,
691 .resource = rtt_resources,
692 .num_resources = ARRAY_SIZE(rtt_resources),
2b3b3516
AV		 693};
694
695static void __init at91_add_device_rtt(void)
696{
697 platform_device_register(&at91cap9_rtt_device);
698}
699
700
701/* --------------------------------------------------------------------
702 * Watchdog
703 * -------------------------------------------------------------------- */
704
705#if defined(CONFIG_AT91SAM9_WATCHDOG) || defined(CONFIG_AT91SAM9_WATCHDOG_MODULE)
706static struct platform_device at91cap9_wdt_device = {
707 .name = "at91_wdt",
708 .id = -1,
709 .num_resources = 0,
710};
711
712static void __init at91_add_device_watchdog(void)
713{
714 platform_device_register(&at91cap9_wdt_device);
715}
716#else
717static void __init at91_add_device_watchdog(void) {}
718#endif
719
720
bb1ad68b
AV		 721/* --------------------------------------------------------------------
722 * PWM
723 * --------------------------------------------------------------------*/
724
725#if defined(CONFIG_ATMEL_PWM)
726static u32 pwm_mask;
727
728static struct resource pwm_resources[] = {
729 [0] = {
730 .start = AT91CAP9_BASE_PWMC,
731 .end = AT91CAP9_BASE_PWMC + SZ_16K - 1,
732 .flags = IORESOURCE_MEM,
733 },
734 [1] = {
735 .start = AT91CAP9_ID_PWMC,
736 .end = AT91CAP9_ID_PWMC,
737 .flags = IORESOURCE_IRQ,
738 },
739};
740
741static struct platform_device at91cap9_pwm0_device = {
742 .name = "atmel_pwm",
743 .id = -1,
744 .dev = {
745 .platform_data = &pwm_mask,
746 },
747 .resource = pwm_resources,
748 .num_resources = ARRAY_SIZE(pwm_resources),
749};
750
751void __init at91_add_device_pwm(u32 mask)
752{
753 if (mask & (1 << AT91_PWM0))
754 at91_set_A_periph(AT91_PIN_PB19, 1); /* enable PWM0 */
755
756 if (mask & (1 << AT91_PWM1))
757 at91_set_B_periph(AT91_PIN_PB8, 1); /* enable PWM1 */
758
759 if (mask & (1 << AT91_PWM2))
760 at91_set_B_periph(AT91_PIN_PC29, 1); /* enable PWM2 */
761
762 if (mask & (1 << AT91_PWM3))
763 at91_set_B_periph(AT91_PIN_PA11, 1); /* enable PWM3 */
764
765 pwm_mask = mask;
766
767 platform_device_register(&at91cap9_pwm0_device);
768}
769#else
770void __init at91_add_device_pwm(u32 mask) {}
771#endif
772
773
774
2b3b3516
AV		 775/* --------------------------------------------------------------------
776 * AC97
777 * -------------------------------------------------------------------- */
778
779#if defined(CONFIG_SND_AT91_AC97) || defined(CONFIG_SND_AT91_AC97_MODULE)
780static u64 ac97_dmamask = DMA_BIT_MASK(32);
781static struct atmel_ac97_data ac97_data;
782
783static struct resource ac97_resources[] = {
784 [0] = {
785 .start = AT91CAP9_BASE_AC97C,
786 .end = AT91CAP9_BASE_AC97C + SZ_16K - 1,
787 .flags = IORESOURCE_MEM,
788 },
789 [1] = {
790 .start = AT91CAP9_ID_AC97C,
791 .end = AT91CAP9_ID_AC97C,
792 .flags = IORESOURCE_IRQ,
793 },
794};
795
796static struct platform_device at91cap9_ac97_device = {
797 .name = "ac97c",
798 .id = 1,
799 .dev = {
800 .dma_mask = &ac97_dmamask,
801 .coherent_dma_mask = DMA_BIT_MASK(32),
802 .platform_data = &ac97_data,
803 },
804 .resource = ac97_resources,
805 .num_resources = ARRAY_SIZE(ac97_resources),
806};
807
808void __init at91_add_device_ac97(struct atmel_ac97_data *data)
809{
810 if (!data)
811 return;
812
813 at91_set_A_periph(AT91_PIN_PA6, 0); /* AC97FS */
814 at91_set_A_periph(AT91_PIN_PA7, 0); /* AC97CK */
815 at91_set_A_periph(AT91_PIN_PA8, 0); /* AC97TX */
816 at91_set_A_periph(AT91_PIN_PA9, 0); /* AC97RX */
817
818 /* reset */
819 if (data->reset_pin)
820 at91_set_gpio_output(data->reset_pin, 0);
821
822 ac97_data = *data;
823 platform_device_register(&at91cap9_ac97_device);
824}
825#else
826void __init at91_add_device_ac97(struct atmel_ac97_data *data) {}
827#endif
828
829
830/* --------------------------------------------------------------------
831 * LCD Controller
832 * -------------------------------------------------------------------- */
833
834#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
835static u64 lcdc_dmamask = DMA_BIT_MASK(32);
836static struct atmel_lcdfb_info lcdc_data;
837
838static struct resource lcdc_resources[] = {
839 [0] = {
840 .start = AT91CAP9_LCDC_BASE,
841 .end = AT91CAP9_LCDC_BASE + SZ_4K - 1,
842 .flags = IORESOURCE_MEM,
843 },
844 [1] = {
845 .start = AT91CAP9_ID_LCDC,
846 .end = AT91CAP9_ID_LCDC,
847 .flags = IORESOURCE_IRQ,
848 },
849};
850
851static struct platform_device at91_lcdc_device = {
852 .name = "atmel_lcdfb",
853 .id = 0,
854 .dev = {
855 .dma_mask = &lcdc_dmamask,
856 .coherent_dma_mask = DMA_BIT_MASK(32),
857 .platform_data = &lcdc_data,
858 },
859 .resource = lcdc_resources,
860 .num_resources = ARRAY_SIZE(lcdc_resources),
861};
862
863void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
864{
865 if (!data)
866 return;
867
868 at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */
869 at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */
870 at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDDEN */
871 at91_set_B_periph(AT91_PIN_PB9, 0); /* LCDCC */
872 at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDD2 */
873 at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDD3 */
874 at91_set_A_periph(AT91_PIN_PC8, 0); /* LCDD4 */
875 at91_set_A_periph(AT91_PIN_PC9, 0); /* LCDD5 */
876 at91_set_A_periph(AT91_PIN_PC10, 0); /* LCDD6 */
877 at91_set_A_periph(AT91_PIN_PC11, 0); /* LCDD7 */
878 at91_set_A_periph(AT91_PIN_PC14, 0); /* LCDD10 */
879 at91_set_A_periph(AT91_PIN_PC15, 0); /* LCDD11 */
880 at91_set_A_periph(AT91_PIN_PC16, 0); /* LCDD12 */
881 at91_set_A_periph(AT91_PIN_PC17, 0); /* LCDD13 */
882 at91_set_A_periph(AT91_PIN_PC18, 0); /* LCDD14 */
883 at91_set_A_periph(AT91_PIN_PC19, 0); /* LCDD15 */
884 at91_set_A_periph(AT91_PIN_PC22, 0); /* LCDD18 */
885 at91_set_A_periph(AT91_PIN_PC23, 0); /* LCDD19 */
886 at91_set_A_periph(AT91_PIN_PC24, 0); /* LCDD20 */
887 at91_set_A_periph(AT91_PIN_PC25, 0); /* LCDD21 */
888 at91_set_A_periph(AT91_PIN_PC26, 0); /* LCDD22 */
889 at91_set_A_periph(AT91_PIN_PC27, 0); /* LCDD23 */
890
891 lcdc_data = *data;
892 platform_device_register(&at91_lcdc_device);
893}
894#else
895void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
896#endif
897
898
899/* --------------------------------------------------------------------
900 * SSC -- Synchronous Serial Controller
901 * -------------------------------------------------------------------- */
902
903#if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
904static u64 ssc0_dmamask = DMA_BIT_MASK(32);
905
906static struct resource ssc0_resources[] = {
907 [0] = {
908 .start = AT91CAP9_BASE_SSC0,
909 .end = AT91CAP9_BASE_SSC0 + SZ_16K - 1,
910 .flags = IORESOURCE_MEM,
911 },
912 [1] = {
913 .start = AT91CAP9_ID_SSC0,
914 .end = AT91CAP9_ID_SSC0,
915 .flags = IORESOURCE_IRQ,
916 },
917};
918
919static struct platform_device at91cap9_ssc0_device = {
920 .name = "ssc",
921 .id = 0,
922 .dev = {
923 .dma_mask = &ssc0_dmamask,
924 .coherent_dma_mask = DMA_BIT_MASK(32),
925 },
926 .resource = ssc0_resources,
927 .num_resources = ARRAY_SIZE(ssc0_resources),
928};
929
930static inline void configure_ssc0_pins(unsigned pins)
931{
932 if (pins & ATMEL_SSC_TF)
933 at91_set_A_periph(AT91_PIN_PB0, 1);
934 if (pins & ATMEL_SSC_TK)
935 at91_set_A_periph(AT91_PIN_PB1, 1);
936 if (pins & ATMEL_SSC_TD)
937 at91_set_A_periph(AT91_PIN_PB2, 1);
938 if (pins & ATMEL_SSC_RD)
939 at91_set_A_periph(AT91_PIN_PB3, 1);
940 if (pins & ATMEL_SSC_RK)
941 at91_set_A_periph(AT91_PIN_PB4, 1);
942 if (pins & ATMEL_SSC_RF)
943 at91_set_A_periph(AT91_PIN_PB5, 1);
944}
945
946static u64 ssc1_dmamask = DMA_BIT_MASK(32);
947
948static struct resource ssc1_resources[] = {
949 [0] = {
950 .start = AT91CAP9_BASE_SSC1,
951 .end = AT91CAP9_BASE_SSC1 + SZ_16K - 1,
952 .flags = IORESOURCE_MEM,
953 },
954 [1] = {
955 .start = AT91CAP9_ID_SSC1,
956 .end = AT91CAP9_ID_SSC1,
957 .flags = IORESOURCE_IRQ,
958 },
959};
960
961static struct platform_device at91cap9_ssc1_device = {
962 .name = "ssc",
963 .id = 1,
964 .dev = {
965 .dma_mask = &ssc1_dmamask,
966 .coherent_dma_mask = DMA_BIT_MASK(32),
967 },
968 .resource = ssc1_resources,
969 .num_resources = ARRAY_SIZE(ssc1_resources),
970};
971
972static inline void configure_ssc1_pins(unsigned pins)
973{
974 if (pins & ATMEL_SSC_TF)
975 at91_set_A_periph(AT91_PIN_PB6, 1);
976 if (pins & ATMEL_SSC_TK)
977 at91_set_A_periph(AT91_PIN_PB7, 1);
978 if (pins & ATMEL_SSC_TD)
979 at91_set_A_periph(AT91_PIN_PB8, 1);
980 if (pins & ATMEL_SSC_RD)
981 at91_set_A_periph(AT91_PIN_PB9, 1);
982 if (pins & ATMEL_SSC_RK)
983 at91_set_A_periph(AT91_PIN_PB10, 1);
984 if (pins & ATMEL_SSC_RF)
985 at91_set_A_periph(AT91_PIN_PB11, 1);
986}
987
988/*
989 * SSC controllers are accessed through library code, instead of any
990 * kind of all-singing/all-dancing driver. For example one could be
991 * used by a particular I2S audio codec's driver, while another one
992 * on the same system might be used by a custom data capture driver.
993 */
994void __init at91_add_device_ssc(unsigned id, unsigned pins)
995{
996 struct platform_device *pdev;
997
998 /*
999 * NOTE: caller is responsible for passing information matching
1000 * "pins" to whatever will be using each particular controller.
1001 */
1002 switch (id) {
1003 case AT91CAP9_ID_SSC0:
1004 pdev = &at91cap9_ssc0_device;
1005 configure_ssc0_pins(pins);
1006 at91_clock_associate("ssc0_clk", &pdev->dev, "ssc");
1007 break;
1008 case AT91CAP9_ID_SSC1:
1009 pdev = &at91cap9_ssc1_device;
1010 configure_ssc1_pins(pins);
1011 at91_clock_associate("ssc1_clk", &pdev->dev, "ssc");
1012 break;
1013 default:
1014 return;
1015 }
1016
1017 platform_device_register(pdev);
1018}
1019
1020#else
1021void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
1022#endif
1023
1024
1025/* --------------------------------------------------------------------
1026 * UART
1027 * -------------------------------------------------------------------- */
1028
1029#if defined(CONFIG_SERIAL_ATMEL)
1030static struct resource dbgu_resources[] = {
1031 [0] = {
1032 .start = AT91_VA_BASE_SYS + AT91_DBGU,
1033 .end = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
1034 .flags = IORESOURCE_MEM,
1035 },
1036 [1] = {
1037 .start = AT91_ID_SYS,
1038 .end = AT91_ID_SYS,
1039 .flags = IORESOURCE_IRQ,
1040 },
1041};
1042
1043static struct atmel_uart_data dbgu_data = {
1044 .use_dma_tx = 0,
1045 .use_dma_rx = 0, /* DBGU not capable of receive DMA */
1046 .regs = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
1047};
1048
1049static u64 dbgu_dmamask = DMA_BIT_MASK(32);
1050
1051static struct platform_device at91cap9_dbgu_device = {
1052 .name = "atmel_usart",
1053 .id = 0,
1054 .dev = {
1055 .dma_mask = &dbgu_dmamask,
1056 .coherent_dma_mask = DMA_BIT_MASK(32),
1057 .platform_data = &dbgu_data,
1058 },
1059 .resource = dbgu_resources,
1060 .num_resources = ARRAY_SIZE(dbgu_resources),
1061};
1062
1063static inline void configure_dbgu_pins(void)
1064{
1065 at91_set_A_periph(AT91_PIN_PC30, 0); /* DRXD */
1066 at91_set_A_periph(AT91_PIN_PC31, 1); /* DTXD */
1067}
1068
1069static struct resource uart0_resources[] = {
1070 [0] = {
1071 .start = AT91CAP9_BASE_US0,
1072 .end = AT91CAP9_BASE_US0 + SZ_16K - 1,
1073 .flags = IORESOURCE_MEM,
1074 },
1075 [1] = {
1076 .start = AT91CAP9_ID_US0,
1077 .end = AT91CAP9_ID_US0,
1078 .flags = IORESOURCE_IRQ,
1079 },
1080};
1081
1082static struct atmel_uart_data uart0_data = {
1083 .use_dma_tx = 1,
1084 .use_dma_rx = 1,
1085};
1086
1087static u64 uart0_dmamask = DMA_BIT_MASK(32);
1088
1089static struct platform_device at91cap9_uart0_device = {
1090 .name = "atmel_usart",
1091 .id = 1,
1092 .dev = {
1093 .dma_mask = &uart0_dmamask,
1094 .coherent_dma_mask = DMA_BIT_MASK(32),
1095 .platform_data = &uart0_data,
1096 },
1097 .resource = uart0_resources,
1098 .num_resources = ARRAY_SIZE(uart0_resources),
1099};
1100
1101static inline void configure_usart0_pins(unsigned pins)
1102{
1103 at91_set_A_periph(AT91_PIN_PA22, 1); /* TXD0 */
1104 at91_set_A_periph(AT91_PIN_PA23, 0); /* RXD0 */
1105
1106 if (pins & ATMEL_UART_RTS)
1107 at91_set_A_periph(AT91_PIN_PA24, 0); /* RTS0 */
1108 if (pins & ATMEL_UART_CTS)
1109 at91_set_A_periph(AT91_PIN_PA25, 0); /* CTS0 */
1110}
1111
1112static struct resource uart1_resources[] = {
1113 [0] = {
1114 .start = AT91CAP9_BASE_US1,
1115 .end = AT91CAP9_BASE_US1 + SZ_16K - 1,
1116 .flags = IORESOURCE_MEM,
1117 },
1118 [1] = {
1119 .start = AT91CAP9_ID_US1,
1120 .end = AT91CAP9_ID_US1,
1121 .flags = IORESOURCE_IRQ,
1122 },
1123};
1124
1125static struct atmel_uart_data uart1_data = {
1126 .use_dma_tx = 1,
1127 .use_dma_rx = 1,
1128};
1129
1130static u64 uart1_dmamask = DMA_BIT_MASK(32);
1131
1132static struct platform_device at91cap9_uart1_device = {
1133 .name = "atmel_usart",
1134 .id = 2,
1135 .dev = {
1136 .dma_mask = &uart1_dmamask,
1137 .coherent_dma_mask = DMA_BIT_MASK(32),
1138 .platform_data = &uart1_data,
1139 },
1140 .resource = uart1_resources,
1141 .num_resources = ARRAY_SIZE(uart1_resources),
1142};
1143
1144static inline void configure_usart1_pins(unsigned pins)
1145{
1146 at91_set_A_periph(AT91_PIN_PD0, 1); /* TXD1 */
1147 at91_set_A_periph(AT91_PIN_PD1, 0); /* RXD1 */
1148
1149 if (pins & ATMEL_UART_RTS)
1150 at91_set_B_periph(AT91_PIN_PD7, 0); /* RTS1 */
1151 if (pins & ATMEL_UART_CTS)
1152 at91_set_B_periph(AT91_PIN_PD8, 0); /* CTS1 */
1153}
1154
1155static struct resource uart2_resources[] = {
1156 [0] = {
1157 .start = AT91CAP9_BASE_US2,
1158 .end = AT91CAP9_BASE_US2 + SZ_16K - 1,
1159 .flags = IORESOURCE_MEM,
1160 },
1161 [1] = {
1162 .start = AT91CAP9_ID_US2,
1163 .end = AT91CAP9_ID_US2,
1164 .flags = IORESOURCE_IRQ,
1165 },
1166};
1167
1168static struct atmel_uart_data uart2_data = {
1169 .use_dma_tx = 1,
1170 .use_dma_rx = 1,
1171};
1172
1173static u64 uart2_dmamask = DMA_BIT_MASK(32);
1174
1175static struct platform_device at91cap9_uart2_device = {
1176 .name = "atmel_usart",
1177 .id = 3,
1178 .dev = {
1179 .dma_mask = &uart2_dmamask,
1180 .coherent_dma_mask = DMA_BIT_MASK(32),
1181 .platform_data = &uart2_data,
1182 },
1183 .resource = uart2_resources,
1184 .num_resources = ARRAY_SIZE(uart2_resources),
1185};
1186
1187static inline void configure_usart2_pins(unsigned pins)
1188{
1189 at91_set_A_periph(AT91_PIN_PD2, 1); /* TXD2 */
1190 at91_set_A_periph(AT91_PIN_PD3, 0); /* RXD2 */
1191
1192 if (pins & ATMEL_UART_RTS)
1193 at91_set_B_periph(AT91_PIN_PD5, 0); /* RTS2 */
1194 if (pins & ATMEL_UART_CTS)
1195 at91_set_B_periph(AT91_PIN_PD6, 0); /* CTS2 */
1196}
1197
11aadac4 1198static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
2b3b3516
AV		 1199struct platform_device *atmel_default_console_device; /* the serial console device */
1200
1201void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1202{
1203 struct platform_device *pdev;
1204
1205 switch (id) {
1206 case 0: /* DBGU */
1207 pdev = &at91cap9_dbgu_device;
1208 configure_dbgu_pins();
1209 at91_clock_associate("mck", &pdev->dev, "usart");
1210 break;
1211 case AT91CAP9_ID_US0:
1212 pdev = &at91cap9_uart0_device;
1213 configure_usart0_pins(pins);
1214 at91_clock_associate("usart0_clk", &pdev->dev, "usart");
1215 break;
1216 case AT91CAP9_ID_US1:
1217 pdev = &at91cap9_uart1_device;
1218 configure_usart1_pins(pins);
1219 at91_clock_associate("usart1_clk", &pdev->dev, "usart");
1220 break;
1221 case AT91CAP9_ID_US2:
1222 pdev = &at91cap9_uart2_device;
1223 configure_usart2_pins(pins);
1224 at91_clock_associate("usart2_clk", &pdev->dev, "usart");
1225 break;
1226 default:
1227 return;
1228 }
1229 pdev->id = portnr; /* update to mapped ID */
1230
1231 if (portnr < ATMEL_MAX_UART)
1232 at91_uarts[portnr] = pdev;
1233}
1234
1235void __init at91_set_serial_console(unsigned portnr)
1236{
1237 if (portnr < ATMEL_MAX_UART)
1238 atmel_default_console_device = at91_uarts[portnr];
2b3b3516
AV		 1239}
1240
1241void __init at91_add_device_serial(void)
1242{
1243 int i;
1244
1245 for (i = 0; i < ATMEL_MAX_UART; i++) {
1246 if (at91_uarts[i])
1247 platform_device_register(at91_uarts[i]);
1248 }
11aadac4
AV		 1249
1250 if (!atmel_default_console_device)
1251 printk(KERN_INFO "AT91: No default serial console defined.\n");
2b3b3516
AV		 1252}
1253#else
1254void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1255void __init at91_set_serial_console(unsigned portnr) {}
1256void __init at91_add_device_serial(void) {}
1257#endif
1258
1259
1260/* -------------------------------------------------------------------- */
1261/*
1262 * These devices are always present and don't need any board-specific
1263 * setup.
1264 */
1265static int __init at91_add_standard_devices(void)
1266{
1267 at91_add_device_rtt();
1268 at91_add_device_watchdog();
e5f40bfa 1269 at91_add_device_tc();
2b3b3516
AV		 1270 return 0;
1271}
1272
1273arch_initcall(at91_add_standard_devices);
Linux kernel - Deliverables
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