[deliverable/linux.git] / arch / arm / mach-at91 / at91rm9200.c

/*
 * arch/arm/mach-at91/at91rm9200.c
 *
 *  Copyright (C) 2005 SAN People
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 */

#include <linux/module.h>

#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/system_misc.h>
#include <mach/at91rm9200.h>
#include <mach/at91_aic.h>
#include <mach/at91_pmc.h>
#include <mach/at91_st.h>
#include <mach/cpu.h>

#include "soc.h"
#include "generic.h"
#include "clock.h"
#include "sam9_smc.h"

/* --------------------------------------------------------------------
 *  Clocks
 * -------------------------------------------------------------------- */

/*
 * The peripheral clocks.
 */
static struct clk udc_clk = {
	.name		= "udc_clk",
	.pmc_mask	= 1 << AT91RM9200_ID_UDP,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk ohci_clk = {
	.name		= "ohci_clk",
	.pmc_mask	= 1 << AT91RM9200_ID_UHP,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk ether_clk = {
	.name		= "ether_clk",
	.pmc_mask	= 1 << AT91RM9200_ID_EMAC,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk mmc_clk = {
	.name		= "mci_clk",
	.pmc_mask	= 1 << AT91RM9200_ID_MCI,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk twi_clk = {
	.name		= "twi_clk",
	.pmc_mask	= 1 << AT91RM9200_ID_TWI,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart0_clk = {
	.name		= "usart0_clk",
	.pmc_mask	= 1 << AT91RM9200_ID_US0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart1_clk = {
	.name		= "usart1_clk",
	.pmc_mask	= 1 << AT91RM9200_ID_US1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart2_clk = {
	.name		= "usart2_clk",
	.pmc_mask	= 1 << AT91RM9200_ID_US2,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart3_clk = {
	.name		= "usart3_clk",
	.pmc_mask	= 1 << AT91RM9200_ID_US3,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk spi_clk = {
	.name		= "spi_clk",
	.pmc_mask	= 1 << AT91RM9200_ID_SPI,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk pioA_clk = {
	.name		= "pioA_clk",
	.pmc_mask	= 1 << AT91RM9200_ID_PIOA,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk pioB_clk = {
	.name		= "pioB_clk",
	.pmc_mask	= 1 << AT91RM9200_ID_PIOB,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk pioC_clk = {
	.name		= "pioC_clk",
	.pmc_mask	= 1 << AT91RM9200_ID_PIOC,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk pioD_clk = {
	.name		= "pioD_clk",
	.pmc_mask	= 1 << AT91RM9200_ID_PIOD,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk ssc0_clk = {
	.name		= "ssc0_clk",
	.pmc_mask	= 1 << AT91RM9200_ID_SSC0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk ssc1_clk = {
	.name		= "ssc1_clk",
	.pmc_mask	= 1 << AT91RM9200_ID_SSC1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk ssc2_clk = {
	.name		= "ssc2_clk",
	.pmc_mask	= 1 << AT91RM9200_ID_SSC2,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk tc0_clk = {
	.name		= "tc0_clk",
	.pmc_mask	= 1 << AT91RM9200_ID_TC0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk tc1_clk = {
	.name		= "tc1_clk",
	.pmc_mask	= 1 << AT91RM9200_ID_TC1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk tc2_clk = {
	.name		= "tc2_clk",
	.pmc_mask	= 1 << AT91RM9200_ID_TC2,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk tc3_clk = {
	.name		= "tc3_clk",
	.pmc_mask	= 1 << AT91RM9200_ID_TC3,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk tc4_clk = {
	.name		= "tc4_clk",
	.pmc_mask	= 1 << AT91RM9200_ID_TC4,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk tc5_clk = {
	.name		= "tc5_clk",
	.pmc_mask	= 1 << AT91RM9200_ID_TC5,
	.type		= CLK_TYPE_PERIPHERAL,
};

static struct clk *periph_clocks[] __initdata = {
	&pioA_clk,
	&pioB_clk,
	&pioC_clk,
	&pioD_clk,
	&usart0_clk,
	&usart1_clk,
	&usart2_clk,
	&usart3_clk,
	&mmc_clk,
	&udc_clk,
	&twi_clk,
	&spi_clk,
	&ssc0_clk,
	&ssc1_clk,
	&ssc2_clk,
	&tc0_clk,
	&tc1_clk,
	&tc2_clk,
	&tc3_clk,
	&tc4_clk,
	&tc5_clk,
	&ohci_clk,
	&ether_clk,
	// irq0 .. irq6
};

static struct clk_lookup periph_clocks_lookups[] = {
	CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
	CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
	CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
	CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tc3_clk),
	CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.1", &tc4_clk),
	CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.1", &tc5_clk),
	CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
	CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
	CLKDEV_CON_DEV_ID("pclk", "ssc.2", &ssc2_clk),
	CLKDEV_CON_DEV_ID(NULL, "i2c-at91rm9200", &twi_clk),
	/* fake hclk clock */
	CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
	CLKDEV_CON_ID("pioA", &pioA_clk),
	CLKDEV_CON_ID("pioB", &pioB_clk),
	CLKDEV_CON_ID("pioC", &pioC_clk),
	CLKDEV_CON_ID("pioD", &pioD_clk),
	/* usart lookup table for DT entries */
	CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
	CLKDEV_CON_DEV_ID("usart", "fffc0000.serial", &usart0_clk),
	CLKDEV_CON_DEV_ID("usart", "fffc4000.serial", &usart1_clk),
	CLKDEV_CON_DEV_ID("usart", "fffc8000.serial", &usart2_clk),
	CLKDEV_CON_DEV_ID("usart", "fffcc000.serial", &usart3_clk),
	/* tc lookup table for DT entries */
	CLKDEV_CON_DEV_ID("t0_clk", "fffa0000.timer", &tc0_clk),
	CLKDEV_CON_DEV_ID("t1_clk", "fffa0000.timer", &tc1_clk),
	CLKDEV_CON_DEV_ID("t2_clk", "fffa0000.timer", &tc2_clk),
	CLKDEV_CON_DEV_ID("t0_clk", "fffa4000.timer", &tc3_clk),
	CLKDEV_CON_DEV_ID("t1_clk", "fffa4000.timer", &tc4_clk),
	CLKDEV_CON_DEV_ID("t2_clk", "fffa4000.timer", &tc5_clk),
	CLKDEV_CON_DEV_ID("hclk", "300000.ohci", &ohci_clk),
	CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioA_clk),
	CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioB_clk),
	CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioC_clk),
	CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioD_clk),
};

static struct clk_lookup usart_clocks_lookups[] = {
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
};

/*
 * The four programmable clocks.
 * You must configure pin multiplexing to bring these signals out.
 */
static struct clk pck0 = {
	.name		= "pck0",
	.pmc_mask	= AT91_PMC_PCK0,
	.type		= CLK_TYPE_PROGRAMMABLE,
	.id		= 0,
};
static struct clk pck1 = {
	.name		= "pck1",
	.pmc_mask	= AT91_PMC_PCK1,
	.type		= CLK_TYPE_PROGRAMMABLE,
	.id		= 1,
};
static struct clk pck2 = {
	.name		= "pck2",
	.pmc_mask	= AT91_PMC_PCK2,
	.type		= CLK_TYPE_PROGRAMMABLE,
	.id		= 2,
};
static struct clk pck3 = {
	.name		= "pck3",
	.pmc_mask	= AT91_PMC_PCK3,
	.type		= CLK_TYPE_PROGRAMMABLE,
	.id		= 3,
};

static void __init at91rm9200_register_clocks(void)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
		clk_register(periph_clocks[i]);

	clkdev_add_table(periph_clocks_lookups,
			 ARRAY_SIZE(periph_clocks_lookups));
	clkdev_add_table(usart_clocks_lookups,
			 ARRAY_SIZE(usart_clocks_lookups));

	clk_register(&pck0);
	clk_register(&pck1);
	clk_register(&pck2);
	clk_register(&pck3);
}

/* --------------------------------------------------------------------
 *  GPIO
 * -------------------------------------------------------------------- */

static struct at91_gpio_bank at91rm9200_gpio[] __initdata = {
	{
		.id		= AT91RM9200_ID_PIOA,
		.regbase	= AT91RM9200_BASE_PIOA,
	}, {
		.id		= AT91RM9200_ID_PIOB,
		.regbase	= AT91RM9200_BASE_PIOB,
	}, {
		.id		= AT91RM9200_ID_PIOC,
		.regbase	= AT91RM9200_BASE_PIOC,
	}, {
		.id		= AT91RM9200_ID_PIOD,
		.regbase	= AT91RM9200_BASE_PIOD,
	}
};

static void at91rm9200_idle(void)
{
	/*
	 * Disable the processor clock.  The processor will be automatically
	 * re-enabled by an interrupt or by a reset.
	 */
	at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK);
}

static void at91rm9200_restart(char mode, const char *cmd)
{
	/*
	 * Perform a hardware reset with the use of the Watchdog timer.
	 */
	at91_st_write(AT91_ST_WDMR, AT91_ST_RSTEN | AT91_ST_EXTEN | 1);
	at91_st_write(AT91_ST_CR, AT91_ST_WDRST);
}

/* --------------------------------------------------------------------
 *  AT91RM9200 processor initialization
 * -------------------------------------------------------------------- */
static void __init at91rm9200_map_io(void)
{
	/* Map peripherals */
	at91_init_sram(0, AT91RM9200_SRAM_BASE, AT91RM9200_SRAM_SIZE);
}

static void __init at91rm9200_ioremap_registers(void)
{
	at91rm9200_ioremap_st(AT91RM9200_BASE_ST);
	at91_ioremap_ramc(0, AT91RM9200_BASE_MC, 256);
}

static void __init at91rm9200_initialize(void)
{
	arm_pm_idle = at91rm9200_idle;
	arm_pm_restart = at91rm9200_restart;
	at91_extern_irq = (1 << AT91RM9200_ID_IRQ0) | (1 << AT91RM9200_ID_IRQ1)
			| (1 << AT91RM9200_ID_IRQ2) | (1 << AT91RM9200_ID_IRQ3)
			| (1 << AT91RM9200_ID_IRQ4) | (1 << AT91RM9200_ID_IRQ5)
			| (1 << AT91RM9200_ID_IRQ6);

	/* Initialize GPIO subsystem */
	at91_gpio_init(at91rm9200_gpio,
		cpu_is_at91rm9200_bga() ? AT91RM9200_BGA : AT91RM9200_PQFP);
}


/* --------------------------------------------------------------------
 *  Interrupt initialization
 * -------------------------------------------------------------------- */

/*
 * The default interrupt priority levels (0 = lowest, 7 = highest).
 */
static unsigned int at91rm9200_default_irq_priority[NR_AIC_IRQS] __initdata = {
	7,	/* Advanced Interrupt Controller (FIQ) */
	7,	/* System Peripherals */
	1,	/* Parallel IO Controller A */
	1,	/* Parallel IO Controller B */
	1,	/* Parallel IO Controller C */
	1,	/* Parallel IO Controller D */
	5,	/* USART 0 */
	5,	/* USART 1 */
	5,	/* USART 2 */
	5,	/* USART 3 */
	0,	/* Multimedia Card Interface */
	2,	/* USB Device Port */
	6,	/* Two-Wire Interface */
	5,	/* Serial Peripheral Interface */
	4,	/* Serial Synchronous Controller 0 */
	4,	/* Serial Synchronous Controller 1 */
	4,	/* Serial Synchronous Controller 2 */
	0,	/* Timer Counter 0 */
	0,	/* Timer Counter 1 */
	0,	/* Timer Counter 2 */
	0,	/* Timer Counter 3 */
	0,	/* Timer Counter 4 */
	0,	/* Timer Counter 5 */
	2,	/* USB Host port */
	3,	/* Ethernet MAC */
	0,	/* Advanced Interrupt Controller (IRQ0) */
	0,	/* Advanced Interrupt Controller (IRQ1) */
	0,	/* Advanced Interrupt Controller (IRQ2) */
	0,	/* Advanced Interrupt Controller (IRQ3) */
	0,	/* Advanced Interrupt Controller (IRQ4) */
	0,	/* Advanced Interrupt Controller (IRQ5) */
	0	/* Advanced Interrupt Controller (IRQ6) */
};

AT91_SOC_START(rm9200)
	.map_io = at91rm9200_map_io,
	.default_irq_priority = at91rm9200_default_irq_priority,
	.ioremap_registers = at91rm9200_ioremap_registers,
	.register_clocks = at91rm9200_register_clocks,
	.init = at91rm9200_initialize,
AT91_SOC_END
Commit	Line	Data
73a59c1c	1	/*
9d041268	2	* arch/arm/mach-at91/at91rm9200.c
73a59c1c SP	3	*
	4	* Copyright (C) 2005 SAN People
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	*/
	12
73a59c1c SP	13	#include <linux/module.h>
73a59c1c SP	14
80b02c17	15	#include <asm/irq.h>
73a59c1c SP	16	#include <asm/mach/arch.h>
73a59c1c SP	17	#include <asm/mach/map.h>
9f97da78	18	#include <asm/system_misc.h>
a09e64fb	19	#include <mach/at91rm9200.h>
8fe82a55	20	#include <mach/at91_aic.h>
a09e64fb RK	21	#include <mach/at91_pmc.h>
a09e64fb RK	22	#include <mach/at91_st.h>
e57556e3	23	#include <mach/cpu.h>
73a59c1c	24
21d08b9d	25	#include "soc.h"
10e8e1fb	26	#include "generic.h"
2eeaaa21	27	#include "clock.h"
faee0cc3	28	#include "sam9_smc.h"
73a59c1c	29
2eeaaa21 AV	30	/* --------------------------------------------------------------------
	31	* Clocks
	32	* -------------------------------------------------------------------- */
	33
	34	/*
	35	* The peripheral clocks.
	36	*/
	37	static struct clk udc_clk = {
	38	.name = "udc_clk",
	39	.pmc_mask = 1 << AT91RM9200_ID_UDP,
	40	.type = CLK_TYPE_PERIPHERAL,
	41	};
	42	static struct clk ohci_clk = {
	43	.name = "ohci_clk",
	44	.pmc_mask = 1 << AT91RM9200_ID_UHP,
	45	.type = CLK_TYPE_PERIPHERAL,
	46	};
	47	static struct clk ether_clk = {
	48	.name = "ether_clk",
	49	.pmc_mask = 1 << AT91RM9200_ID_EMAC,
	50	.type = CLK_TYPE_PERIPHERAL,
	51	};
	52	static struct clk mmc_clk = {
	53	.name = "mci_clk",
	54	.pmc_mask = 1 << AT91RM9200_ID_MCI,
	55	.type = CLK_TYPE_PERIPHERAL,
	56	};
	57	static struct clk twi_clk = {
	58	.name = "twi_clk",
	59	.pmc_mask = 1 << AT91RM9200_ID_TWI,
	60	.type = CLK_TYPE_PERIPHERAL,
	61	};
	62	static struct clk usart0_clk = {
	63	.name = "usart0_clk",
	64	.pmc_mask = 1 << AT91RM9200_ID_US0,
	65	.type = CLK_TYPE_PERIPHERAL,
	66	};
	67	static struct clk usart1_clk = {
	68	.name = "usart1_clk",
	69	.pmc_mask = 1 << AT91RM9200_ID_US1,
	70	.type = CLK_TYPE_PERIPHERAL,
	71	};
	72	static struct clk usart2_clk = {
	73	.name = "usart2_clk",
	74	.pmc_mask = 1 << AT91RM9200_ID_US2,
	75	.type = CLK_TYPE_PERIPHERAL,
	76	};
	77	static struct clk usart3_clk = {
	78	.name = "usart3_clk",
	79	.pmc_mask = 1 << AT91RM9200_ID_US3,
	80	.type = CLK_TYPE_PERIPHERAL,
	81	};
	82	static struct clk spi_clk = {
	83	.name = "spi_clk",
	84	.pmc_mask = 1 << AT91RM9200_ID_SPI,
	85	.type = CLK_TYPE_PERIPHERAL,
	86	};
	87	static struct clk pioA_clk = {
	88	.name = "pioA_clk",
	89	.pmc_mask = 1 << AT91RM9200_ID_PIOA,
	90	.type = CLK_TYPE_PERIPHERAL,
	91	};
	92	static struct clk pioB_clk = {
	93	.name = "pioB_clk",
94	.pmc_mask = 1 << AT91RM9200_ID_PIOB,
95	.type = CLK_TYPE_PERIPHERAL,
96	};
97	static struct clk pioC_clk = {
98	.name = "pioC_clk",
99	.pmc_mask = 1 << AT91RM9200_ID_PIOC,
100	.type = CLK_TYPE_PERIPHERAL,
101	};
102	static struct clk pioD_clk = {
103	.name = "pioD_clk",
104	.pmc_mask = 1 << AT91RM9200_ID_PIOD,
105	.type = CLK_TYPE_PERIPHERAL,
106	};
e8788bab AV	107	static struct clk ssc0_clk = {
	108	.name = "ssc0_clk",
	109	.pmc_mask = 1 << AT91RM9200_ID_SSC0,
	110	.type = CLK_TYPE_PERIPHERAL,
	111	};
	112	static struct clk ssc1_clk = {
	113	.name = "ssc1_clk",
	114	.pmc_mask = 1 << AT91RM9200_ID_SSC1,
	115	.type = CLK_TYPE_PERIPHERAL,
	116	};
	117	static struct clk ssc2_clk = {
	118	.name = "ssc2_clk",
	119	.pmc_mask = 1 << AT91RM9200_ID_SSC2,
	120	.type = CLK_TYPE_PERIPHERAL,
	121	};
c177a1e7 AV	122	static struct clk tc0_clk = {
	123	.name = "tc0_clk",
	124	.pmc_mask = 1 << AT91RM9200_ID_TC0,
	125	.type = CLK_TYPE_PERIPHERAL,
	126	};
	127	static struct clk tc1_clk = {
	128	.name = "tc1_clk",
	129	.pmc_mask = 1 << AT91RM9200_ID_TC1,
	130	.type = CLK_TYPE_PERIPHERAL,
	131	};
	132	static struct clk tc2_clk = {
	133	.name = "tc2_clk",
	134	.pmc_mask = 1 << AT91RM9200_ID_TC2,
	135	.type = CLK_TYPE_PERIPHERAL,
	136	};
	137	static struct clk tc3_clk = {
	138	.name = "tc3_clk",
	139	.pmc_mask = 1 << AT91RM9200_ID_TC3,
	140	.type = CLK_TYPE_PERIPHERAL,
	141	};
	142	static struct clk tc4_clk = {
	143	.name = "tc4_clk",
	144	.pmc_mask = 1 << AT91RM9200_ID_TC4,
	145	.type = CLK_TYPE_PERIPHERAL,
	146	};
	147	static struct clk tc5_clk = {
	148	.name = "tc5_clk",
	149	.pmc_mask = 1 << AT91RM9200_ID_TC5,
	150	.type = CLK_TYPE_PERIPHERAL,
	151	};
2eeaaa21 AV	152
	153	static struct clk *periph_clocks[] __initdata = {
	154	&pioA_clk,
	155	&pioB_clk,
	156	&pioC_clk,
	157	&pioD_clk,
	158	&usart0_clk,
	159	&usart1_clk,
	160	&usart2_clk,
	161	&usart3_clk,
	162	&mmc_clk,
	163	&udc_clk,
	164	&twi_clk,
	165	&spi_clk,
e8788bab AV	166	&ssc0_clk,
	167	&ssc1_clk,
	168	&ssc2_clk,
c177a1e7 AV	169	&tc0_clk,
	170	&tc1_clk,
	171	&tc2_clk,
	172	&tc3_clk,
	173	&tc4_clk,
	174	&tc5_clk,
2eeaaa21 AV	175	&ohci_clk,
	176	&ether_clk,
	177	// irq0 .. irq6
	178	};
	179
bd602995 JCPV	180	static struct clk_lookup periph_clocks_lookups[] = {
	181	CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
	182	CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
	183	CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
	184	CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tc3_clk),
	185	CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.1", &tc4_clk),
	186	CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.1", &tc5_clk),
c5efefac JE	187	CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
	188	CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
	189	CLKDEV_CON_DEV_ID("pclk", "ssc.2", &ssc2_clk),
fac368a0	190	CLKDEV_CON_DEV_ID(NULL, "i2c-at91rm9200", &twi_clk),
0af4316b JCPV	191	/* fake hclk clock */
0af4316b JCPV	192	CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
619d4a4b JCPV	193	CLKDEV_CON_ID("pioA", &pioA_clk),
	194	CLKDEV_CON_ID("pioB", &pioB_clk),
	195	CLKDEV_CON_ID("pioC", &pioC_clk),
	196	CLKDEV_CON_ID("pioD", &pioD_clk),
0ac433a7 JE	197	/* usart lookup table for DT entries */
	198	CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
	199	CLKDEV_CON_DEV_ID("usart", "fffc0000.serial", &usart0_clk),
	200	CLKDEV_CON_DEV_ID("usart", "fffc4000.serial", &usart1_clk),
	201	CLKDEV_CON_DEV_ID("usart", "fffc8000.serial", &usart2_clk),
	202	CLKDEV_CON_DEV_ID("usart", "fffcc000.serial", &usart3_clk),
	203	/* tc lookup table for DT entries */
	204	CLKDEV_CON_DEV_ID("t0_clk", "fffa0000.timer", &tc0_clk),
	205	CLKDEV_CON_DEV_ID("t1_clk", "fffa0000.timer", &tc1_clk),
	206	CLKDEV_CON_DEV_ID("t2_clk", "fffa0000.timer", &tc2_clk),
	207	CLKDEV_CON_DEV_ID("t0_clk", "fffa4000.timer", &tc3_clk),
	208	CLKDEV_CON_DEV_ID("t1_clk", "fffa4000.timer", &tc4_clk),
	209	CLKDEV_CON_DEV_ID("t2_clk", "fffa4000.timer", &tc5_clk),
	210	CLKDEV_CON_DEV_ID("hclk", "300000.ohci", &ohci_clk),
	211	CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioA_clk),
	212	CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioB_clk),
	213	CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioC_clk),
	214	CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioD_clk),
bd602995 JCPV	215	};
	216
	217	static struct clk_lookup usart_clocks_lookups[] = {
	218	CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
	219	CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
	220	CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
	221	CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
	222	CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
	223	};
	224
2eeaaa21 AV	225	/*
	226	* The four programmable clocks.
	227	* You must configure pin multiplexing to bring these signals out.
	228	*/
	229	static struct clk pck0 = {
	230	.name = "pck0",
	231	.pmc_mask = AT91_PMC_PCK0,
	232	.type = CLK_TYPE_PROGRAMMABLE,
	233	.id = 0,
	234	};
	235	static struct clk pck1 = {
	236	.name = "pck1",
	237	.pmc_mask = AT91_PMC_PCK1,
	238	.type = CLK_TYPE_PROGRAMMABLE,
	239	.id = 1,
	240	};
	241	static struct clk pck2 = {
	242	.name = "pck2",
	243	.pmc_mask = AT91_PMC_PCK2,
	244	.type = CLK_TYPE_PROGRAMMABLE,
	245	.id = 2,
	246	};
	247	static struct clk pck3 = {
	248	.name = "pck3",
	249	.pmc_mask = AT91_PMC_PCK3,
	250	.type = CLK_TYPE_PROGRAMMABLE,
	251	.id = 3,
	252	};
	253
	254	static void __init at91rm9200_register_clocks(void)
73a59c1c	255	{
2eeaaa21 AV	256	int i;
	257
	258	for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
	259	clk_register(periph_clocks[i]);
	260
bd602995 JCPV	261	clkdev_add_table(periph_clocks_lookups,
	262	ARRAY_SIZE(periph_clocks_lookups));
	263	clkdev_add_table(usart_clocks_lookups,
	264	ARRAY_SIZE(usart_clocks_lookups));
	265
2eeaaa21 AV	266	clk_register(&pck0);
	267	clk_register(&pck1);
	268	clk_register(&pck2);
	269	clk_register(&pck3);
	270	}
	271
f2173834 AV	272	/* --------------------------------------------------------------------
	273	* GPIO
	274	* -------------------------------------------------------------------- */
	275
1a2d9156	276	static struct at91_gpio_bank at91rm9200_gpio[] __initdata = {
f2173834 AV	277	{
f2173834 AV	278	.id = AT91RM9200_ID_PIOA,
80e91cb8	279	.regbase = AT91RM9200_BASE_PIOA,
f2173834 AV	280	}, {
f2173834 AV	281	.id = AT91RM9200_ID_PIOB,
80e91cb8	282	.regbase = AT91RM9200_BASE_PIOB,
f2173834 AV	283	}, {
f2173834 AV	284	.id = AT91RM9200_ID_PIOC,
80e91cb8	285	.regbase = AT91RM9200_BASE_PIOC,
f2173834 AV	286	}, {
f2173834 AV	287	.id = AT91RM9200_ID_PIOD,
80e91cb8	288	.regbase = AT91RM9200_BASE_PIOD,
f2173834 AV	289	}
f2173834 AV	290	};
2eeaaa21	291
c9dfafba NP	292	static void at91rm9200_idle(void)
	293	{
	294	/*
	295	* Disable the processor clock. The processor will be automatically
	296	* re-enabled by an interrupt or by a reset.
	297	*/
b5514952	298	at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK);
c9dfafba NP	299	}
c9dfafba NP	300
1b2073e7	301	static void at91rm9200_restart(char mode, const char *cmd)
1f4fd0a0 AV	302	{
	303	/*
	304	* Perform a hardware reset with the use of the Watchdog timer.
	305	*/
5e9cf5e1 JCPV	306	at91_st_write(AT91_ST_WDMR, AT91_ST_RSTEN \| AT91_ST_EXTEN \| 1);
5e9cf5e1 JCPV	307	at91_st_write(AT91_ST_CR, AT91_ST_WDRST);
1f4fd0a0 AV	308	}
1f4fd0a0 AV	309
2eeaaa21 AV	310	/* --------------------------------------------------------------------
	311	* AT91RM9200 processor initialization
	312	* -------------------------------------------------------------------- */
21d08b9d	313	static void __init at91rm9200_map_io(void)
2eeaaa21 AV	314	{
2eeaaa21 AV	315	/* Map peripherals */
f0051d82	316	at91_init_sram(0, AT91RM9200_SRAM_BASE, AT91RM9200_SRAM_SIZE);
1b021a3b	317	}
2eeaaa21	318
cfa5a1fe JCPV	319	static void __init at91rm9200_ioremap_registers(void)
cfa5a1fe JCPV	320	{
5e9cf5e1	321	at91rm9200_ioremap_st(AT91RM9200_BASE_ST);
f363c407	322	at91_ioremap_ramc(0, AT91RM9200_BASE_MC, 256);
cfa5a1fe JCPV	323	}
cfa5a1fe JCPV	324
46539374	325	static void __init at91rm9200_initialize(void)
1b021a3b	326	{
c9dfafba	327	arm_pm_idle = at91rm9200_idle;
1b2073e7	328	arm_pm_restart = at91rm9200_restart;
1f4fd0a0 AV	329	at91_extern_irq = (1 << AT91RM9200_ID_IRQ0) \| (1 << AT91RM9200_ID_IRQ1)
	330	\| (1 << AT91RM9200_ID_IRQ2) \| (1 << AT91RM9200_ID_IRQ3)
	331	\| (1 << AT91RM9200_ID_IRQ4) \| (1 << AT91RM9200_ID_IRQ5)
	332	\| (1 << AT91RM9200_ID_IRQ6);
	333
f2173834	334	/* Initialize GPIO subsystem */
e57556e3 JCPV	335	at91_gpio_init(at91rm9200_gpio,
e57556e3 JCPV	336	cpu_is_at91rm9200_bga() ? AT91RM9200_BGA : AT91RM9200_PQFP);
73a59c1c SP	337	}
73a59c1c SP	338
f2173834 AV	339
	340	/* --------------------------------------------------------------------
	341	* Interrupt initialization
	342	* -------------------------------------------------------------------- */
	343
ba854e18 AV	344	/*
	345	* The default interrupt priority levels (0 = lowest, 7 = highest).
	346	*/
	347	static unsigned int at91rm9200_default_irq_priority[NR_AIC_IRQS] __initdata = {
	348	7, /* Advanced Interrupt Controller (FIQ) */
	349	7, /* System Peripherals */
7cbed2b5 AV	350	1, /* Parallel IO Controller A */
	351	1, /* Parallel IO Controller B */
	352	1, /* Parallel IO Controller C */
	353	1, /* Parallel IO Controller D */
	354	5, /* USART 0 */
	355	5, /* USART 1 */
	356	5, /* USART 2 */
	357	5, /* USART 3 */
ba854e18	358	0, /* Multimedia Card Interface */
7cbed2b5 AV	359	2, /* USB Device Port */
	360	6, /* Two-Wire Interface */
	361	5, /* Serial Peripheral Interface */
	362	4, /* Serial Synchronous Controller 0 */
	363	4, /* Serial Synchronous Controller 1 */
	364	4, /* Serial Synchronous Controller 2 */
ba854e18 AV	365	0, /* Timer Counter 0 */
	366	0, /* Timer Counter 1 */
	367	0, /* Timer Counter 2 */
	368	0, /* Timer Counter 3 */
	369	0, /* Timer Counter 4 */
	370	0, /* Timer Counter 5 */
7cbed2b5	371	2, /* USB Host port */
ba854e18 AV	372	3, /* Ethernet MAC */
	373	0, /* Advanced Interrupt Controller (IRQ0) */
	374	0, /* Advanced Interrupt Controller (IRQ1) */
	375	0, /* Advanced Interrupt Controller (IRQ2) */
	376	0, /* Advanced Interrupt Controller (IRQ3) */
	377	0, /* Advanced Interrupt Controller (IRQ4) */
	378	0, /* Advanced Interrupt Controller (IRQ5) */
	379	0 /* Advanced Interrupt Controller (IRQ6) */
	380	};
	381
8d39e0fd	382	AT91_SOC_START(rm9200)
21d08b9d	383	.map_io = at91rm9200_map_io,
92100c12	384	.default_irq_priority = at91rm9200_default_irq_priority,
cfa5a1fe	385	.ioremap_registers = at91rm9200_ioremap_registers,
51ddec76	386	.register_clocks = at91rm9200_register_clocks,
21d08b9d	387	.init = at91rm9200_initialize,
8d39e0fd	388	AT91_SOC_END