projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[ARM] 4124/1: Rename mach-at91rm9200 and arch-at91rm9200 directories
[deliverable/linux.git] / arch / arm / mach-at91 / at91rm9200_devices.c
CommitLineData
73a59c1c 1/*
9d041268 2 * arch/arm/mach-at91/at91rm9200_devices.c
73a59c1c
SP		 3 *
4 * Copyright (C) 2005 Thibaut VARENE <varenet@parisc-linux.org>
5 * Copyright (C) 2005 David Brownell
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 */
13#include <asm/mach/arch.h>
14#include <asm/mach/map.h>
15
73a59c1c
SP		 16#include <linux/platform_device.h>
17
18#include <asm/arch/board.h>
2e836402 19#include <asm/arch/gpio.h>
69c5eccd
AV		 20#include <asm/arch/at91rm9200.h>
21#include <asm/arch/at91rm9200_mc.h>
73a59c1c 22
2e836402
AV		 23#include "generic.h"
24
25#define SZ_512 0x00000200
26#define SZ_256 0x00000100
27#define SZ_16 0x00000010
73a59c1c
SP		 28
29/* --------------------------------------------------------------------
30 * USB Host
31 * -------------------------------------------------------------------- */
32
33#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
34static u64 ohci_dmamask = 0xffffffffUL;
35static struct at91_usbh_data usbh_data;
36
69c5eccd 37static struct resource usbh_resources[] = {
73a59c1c 38 [0] = {
72729910
AV		 39 .start = AT91RM9200_UHP_BASE,
40 .end = AT91RM9200_UHP_BASE + SZ_1M - 1,
73a59c1c
SP		 41 .flags = IORESOURCE_MEM,
42 },
43 [1] = {
72729910
AV		 44 .start = AT91RM9200_ID_UHP,
45 .end = AT91RM9200_ID_UHP,
73a59c1c
SP		 46 .flags = IORESOURCE_IRQ,
47 },
48};
49
50static struct platform_device at91rm9200_usbh_device = {
2e836402 51 .name = "at91_ohci",
73a59c1c
SP		 52 .id = -1,
53 .dev = {
54 .dma_mask = &ohci_dmamask,
55 .coherent_dma_mask = 0xffffffff,
56 .platform_data = &usbh_data,
57 },
69c5eccd
AV		 58 .resource = usbh_resources,
59 .num_resources = ARRAY_SIZE(usbh_resources),
73a59c1c
SP		 60};
61
62void __init at91_add_device_usbh(struct at91_usbh_data *data)
63{
64 if (!data)
65 return;
66
67 usbh_data = *data;
68 platform_device_register(&at91rm9200_usbh_device);
69}
70#else
71void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
72#endif
73
74
75/* --------------------------------------------------------------------
76 * USB Device (Gadget)
77 * -------------------------------------------------------------------- */
78
79#ifdef CONFIG_USB_GADGET_AT91
80static struct at91_udc_data udc_data;
81
69c5eccd 82static struct resource udc_resources[] = {
2e836402 83 [0] = {
72729910
AV		 84 .start = AT91RM9200_BASE_UDP,
85 .end = AT91RM9200_BASE_UDP + SZ_16K - 1,
73a59c1c 86 .flags = IORESOURCE_MEM,
2e836402
AV		 87 },
88 [1] = {
72729910
AV		 89 .start = AT91RM9200_ID_UDP,
90 .end = AT91RM9200_ID_UDP,
2e836402
AV		 91 .flags = IORESOURCE_IRQ,
92 },
73a59c1c
SP		 93};
94
95static struct platform_device at91rm9200_udc_device = {
96 .name = "at91_udc",
97 .id = -1,
98 .dev = {
99 .platform_data = &udc_data,
100 },
69c5eccd
AV		 101 .resource = udc_resources,
102 .num_resources = ARRAY_SIZE(udc_resources),
73a59c1c
SP		 103};
104
105void __init at91_add_device_udc(struct at91_udc_data *data)
106{
107 if (!data)
108 return;
109
110 if (data->vbus_pin) {
111 at91_set_gpio_input(data->vbus_pin, 0);
112 at91_set_deglitch(data->vbus_pin, 1);
113 }
2e836402 114 if (data->pullup_pin)
73a59c1c
SP		 115 at91_set_gpio_output(data->pullup_pin, 0);
116
117 udc_data = *data;
118 platform_device_register(&at91rm9200_udc_device);
119}
120#else
121void __init at91_add_device_udc(struct at91_udc_data *data) {}
122#endif
123
124
125/* --------------------------------------------------------------------
126 * Ethernet
127 * -------------------------------------------------------------------- */
128
129#if defined(CONFIG_ARM_AT91_ETHER) || defined(CONFIG_ARM_AT91_ETHER_MODULE)
130static u64 eth_dmamask = 0xffffffffUL;
131static struct at91_eth_data eth_data;
132
69c5eccd 133static struct resource eth_resources[] = {
3267c077 134 [0] = {
1f51c10c
AV		 135 .start = AT91_VA_BASE_EMAC,
136 .end = AT91_VA_BASE_EMAC + SZ_16K - 1,
3267c077
AV		 137 .flags = IORESOURCE_MEM,
138 },
139 [1] = {
72729910
AV		 140 .start = AT91RM9200_ID_EMAC,
141 .end = AT91RM9200_ID_EMAC,
3267c077
AV		 142 .flags = IORESOURCE_IRQ,
143 },
144};
145
73a59c1c
SP		 146static struct platform_device at91rm9200_eth_device = {
147 .name = "at91_ether",
148 .id = -1,
149 .dev = {
150 .dma_mask = &eth_dmamask,
151 .coherent_dma_mask = 0xffffffff,
152 .platform_data = &eth_data,
153 },
69c5eccd
AV		 154 .resource = eth_resources,
155 .num_resources = ARRAY_SIZE(eth_resources),
73a59c1c
SP		 156};
157
158void __init at91_add_device_eth(struct at91_eth_data *data)
159{
160 if (!data)
161 return;
162
163 if (data->phy_irq_pin) {
164 at91_set_gpio_input(data->phy_irq_pin, 0);
165 at91_set_deglitch(data->phy_irq_pin, 1);
166 }
167
168 /* Pins used for MII and RMII */
169 at91_set_A_periph(AT91_PIN_PA16, 0); /* EMDIO */
170 at91_set_A_periph(AT91_PIN_PA15, 0); /* EMDC */
171 at91_set_A_periph(AT91_PIN_PA14, 0); /* ERXER */
172 at91_set_A_periph(AT91_PIN_PA13, 0); /* ERX1 */
173 at91_set_A_periph(AT91_PIN_PA12, 0); /* ERX0 */
174 at91_set_A_periph(AT91_PIN_PA11, 0); /* ECRS_ECRSDV */
175 at91_set_A_periph(AT91_PIN_PA10, 0); /* ETX1 */
176 at91_set_A_periph(AT91_PIN_PA9, 0); /* ETX0 */
177 at91_set_A_periph(AT91_PIN_PA8, 0); /* ETXEN */
178 at91_set_A_periph(AT91_PIN_PA7, 0); /* ETXCK_EREFCK */
179
180 if (!data->is_rmii) {
181 at91_set_B_periph(AT91_PIN_PB19, 0); /* ERXCK */
182 at91_set_B_periph(AT91_PIN_PB18, 0); /* ECOL */
183 at91_set_B_periph(AT91_PIN_PB17, 0); /* ERXDV */
184 at91_set_B_periph(AT91_PIN_PB16, 0); /* ERX3 */
185 at91_set_B_periph(AT91_PIN_PB15, 0); /* ERX2 */
186 at91_set_B_periph(AT91_PIN_PB14, 0); /* ETXER */
187 at91_set_B_periph(AT91_PIN_PB13, 0); /* ETX3 */
188 at91_set_B_periph(AT91_PIN_PB12, 0); /* ETX2 */
189 }
190
191 eth_data = *data;
192 platform_device_register(&at91rm9200_eth_device);
193}
194#else
195void __init at91_add_device_eth(struct at91_eth_data *data) {}
196#endif
197
198
199/* --------------------------------------------------------------------
200 * Compact Flash / PCMCIA
201 * -------------------------------------------------------------------- */
202
203#if defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE)
204static struct at91_cf_data cf_data;
205
69c5eccd
AV		 206#define CF_BASE AT91_CHIPSELECT_4
207
208static struct resource cf_resources[] = {
2c536200 209 [0] = {
69c5eccd 210 .start = CF_BASE,
2e836402 211 /* ties up CS4, CS5 and CS6 */
69c5eccd 212 .end = CF_BASE + (0x30000000 - 1),
2c536200
DB		 213 .flags = IORESOURCE_MEM | IORESOURCE_MEM_8AND16BIT,
214 },
215};
216
73a59c1c
SP		 217static struct platform_device at91rm9200_cf_device = {
218 .name = "at91_cf",
219 .id = -1,
220 .dev = {
221 .platform_data = &cf_data,
222 },
69c5eccd
AV		 223 .resource = cf_resources,
224 .num_resources = ARRAY_SIZE(cf_resources),
73a59c1c
SP		 225};
226
227void __init at91_add_device_cf(struct at91_cf_data *data)
228{
69c5eccd
AV		 229 unsigned int csa;
230
73a59c1c
SP		 231 if (!data)
232 return;
233
69c5eccd
AV		 234 data->chipselect = 4; /* can only use EBI ChipSelect 4 */
235
236 /* CF takes over CS4, CS5, CS6 */
237 csa = at91_sys_read(AT91_EBI_CSA);
238 at91_sys_write(AT91_EBI_CSA, csa | AT91_EBI_CS4A_SMC_COMPACTFLASH);
239
240 /*
241 * Static memory controller timing adjustments.
242 * REVISIT: these timings are in terms of MCK cycles, so
243 * when MCK changes (cpufreq etc) so must these values...
244 */
245 at91_sys_write(AT91_SMC_CSR(4),
246 AT91_SMC_ACSS_STD
247 | AT91_SMC_DBW_16
248 | AT91_SMC_BAT
249 | AT91_SMC_WSEN
250 | AT91_SMC_NWS_(32) /* wait states */
251 | AT91_SMC_RWSETUP_(6) /* setup time */
252 | AT91_SMC_RWHOLD_(4) /* hold time */
253 );
254
73a59c1c
SP		 255 /* input/irq */
256 if (data->irq_pin) {
257 at91_set_gpio_input(data->irq_pin, 1);
258 at91_set_deglitch(data->irq_pin, 1);
259 }
260 at91_set_gpio_input(data->det_pin, 1);
261 at91_set_deglitch(data->det_pin, 1);
262
263 /* outputs, initially off */
264 if (data->vcc_pin)
265 at91_set_gpio_output(data->vcc_pin, 0);
266 at91_set_gpio_output(data->rst_pin, 0);
267
2e836402
AV		 268 /* force poweron defaults for these pins ... */
269 at91_set_A_periph(AT91_PIN_PC9, 0); /* A25/CFRNW */
270 at91_set_A_periph(AT91_PIN_PC10, 0); /* NCS4/CFCS */
271 at91_set_A_periph(AT91_PIN_PC11, 0); /* NCS5/CFCE1 */
272 at91_set_A_periph(AT91_PIN_PC12, 0); /* NCS6/CFCE2 */
273
69c5eccd 274 /* nWAIT is _not_ a default setting */
a14d5273 275 at91_set_A_periph(AT91_PIN_PC6, 1); /* nWAIT */
69c5eccd 276
73a59c1c
SP		 277 cf_data = *data;
278 platform_device_register(&at91rm9200_cf_device);
279}
280#else
281void __init at91_add_device_cf(struct at91_cf_data *data) {}
282#endif
283
284
285/* --------------------------------------------------------------------
286 * MMC / SD
287 * -------------------------------------------------------------------- */
288
69c5eccd 289#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
73a59c1c
SP		 290static u64 mmc_dmamask = 0xffffffffUL;
291static struct at91_mmc_data mmc_data;
292
69c5eccd 293static struct resource mmc_resources[] = {
3267c077 294 [0] = {
72729910
AV		 295 .start = AT91RM9200_BASE_MCI,
296 .end = AT91RM9200_BASE_MCI + SZ_16K - 1,
73a59c1c 297 .flags = IORESOURCE_MEM,
3267c077
AV		 298 },
299 [1] = {
72729910
AV		 300 .start = AT91RM9200_ID_MCI,
301 .end = AT91RM9200_ID_MCI,
3267c077
AV		 302 .flags = IORESOURCE_IRQ,
303 },
73a59c1c
SP		 304};
305
306static struct platform_device at91rm9200_mmc_device = {
3267c077 307 .name = "at91_mci",
73a59c1c
SP		 308 .id = -1,
309 .dev = {
310 .dma_mask = &mmc_dmamask,
311 .coherent_dma_mask = 0xffffffff,
312 .platform_data = &mmc_data,
313 },
69c5eccd
AV		 314 .resource = mmc_resources,
315 .num_resources = ARRAY_SIZE(mmc_resources),
73a59c1c
SP		 316};
317
318void __init at91_add_device_mmc(struct at91_mmc_data *data)
319{
320 if (!data)
321 return;
322
323 /* input/irq */
324 if (data->det_pin) {
325 at91_set_gpio_input(data->det_pin, 1);
326 at91_set_deglitch(data->det_pin, 1);
327 }
328 if (data->wp_pin)
329 at91_set_gpio_input(data->wp_pin, 1);
69c5eccd
AV		 330 if (data->vcc_pin)
331 at91_set_gpio_output(data->vcc_pin, 0);
73a59c1c
SP		 332
333 /* CLK */
334 at91_set_A_periph(AT91_PIN_PA27, 0);
335
69c5eccd 336 if (data->slot_b) {
73a59c1c 337 /* CMD */
69c5eccd 338 at91_set_B_periph(AT91_PIN_PA8, 1);
73a59c1c
SP		 339
340 /* DAT0, maybe DAT1..DAT3 */
69c5eccd 341 at91_set_B_periph(AT91_PIN_PA9, 1);
73a59c1c 342 if (data->wire4) {
69c5eccd
AV		 343 at91_set_B_periph(AT91_PIN_PA10, 1);
344 at91_set_B_periph(AT91_PIN_PA11, 1);
345 at91_set_B_periph(AT91_PIN_PA12, 1);
73a59c1c
SP		 346 }
347 } else {
348 /* CMD */
69c5eccd 349 at91_set_A_periph(AT91_PIN_PA28, 1);
73a59c1c
SP		 350
351 /* DAT0, maybe DAT1..DAT3 */
69c5eccd 352 at91_set_A_periph(AT91_PIN_PA29, 1);
73a59c1c 353 if (data->wire4) {
69c5eccd
AV		 354 at91_set_B_periph(AT91_PIN_PB3, 1);
355 at91_set_B_periph(AT91_PIN_PB4, 1);
356 at91_set_B_periph(AT91_PIN_PB5, 1);
73a59c1c
SP		 357 }
358 }
359
360 mmc_data = *data;
361 platform_device_register(&at91rm9200_mmc_device);
362}
363#else
364void __init at91_add_device_mmc(struct at91_mmc_data *data) {}
365#endif
366
2e836402 367
3267c077
AV		 368/* --------------------------------------------------------------------
369 * NAND / SmartMedia
370 * -------------------------------------------------------------------- */
371
372#if defined(CONFIG_MTD_NAND_AT91) || defined(CONFIG_MTD_NAND_AT91_MODULE)
373static struct at91_nand_data nand_data;
374
69c5eccd
AV		 375#define NAND_BASE AT91_CHIPSELECT_3
376
377static struct resource nand_resources[] = {
3267c077 378 {
69c5eccd
AV		 379 .start = NAND_BASE,
380 .end = NAND_BASE + SZ_8M - 1,
3267c077
AV		 381 .flags = IORESOURCE_MEM,
382 }
383};
384
69c5eccd 385static struct platform_device at91rm9200_nand_device = {
3267c077
AV		 386 .name = "at91_nand",
387 .id = -1,
388 .dev = {
389 .platform_data = &nand_data,
390 },
69c5eccd
AV		 391 .resource = nand_resources,
392 .num_resources = ARRAY_SIZE(nand_resources),
3267c077
AV		 393};
394
395void __init at91_add_device_nand(struct at91_nand_data *data)
396{
69c5eccd
AV		 397 unsigned int csa;
398
3267c077
AV		 399 if (!data)
400 return;
401
69c5eccd
AV		 402 /* enable the address range of CS3 */
403 csa = at91_sys_read(AT91_EBI_CSA);
404 at91_sys_write(AT91_EBI_CSA, csa | AT91_EBI_CS3A_SMC_SMARTMEDIA);
405
406 /* set the bus interface characteristics */
407 at91_sys_write(AT91_SMC_CSR(3), AT91_SMC_ACSS_STD | AT91_SMC_DBW_8 | AT91_SMC_WSEN
408 | AT91_SMC_NWS_(5)
409 | AT91_SMC_TDF_(1)
410 | AT91_SMC_RWSETUP_(0) /* tDS Data Set up Time 30 - ns */
411 | AT91_SMC_RWHOLD_(1) /* tDH Data Hold Time 20 - ns */
412 );
413
3267c077
AV		 414 /* enable pin */
415 if (data->enable_pin)
416 at91_set_gpio_output(data->enable_pin, 1);
417
418 /* ready/busy pin */
419 if (data->rdy_pin)
420 at91_set_gpio_input(data->rdy_pin, 1);
421
422 /* card detect pin */
423 if (data->det_pin)
424 at91_set_gpio_input(data->det_pin, 1);
425
426 at91_set_A_periph(AT91_PIN_PC1, 0); /* SMOE */
427 at91_set_A_periph(AT91_PIN_PC3, 0); /* SMWE */
428
429 nand_data = *data;
69c5eccd 430 platform_device_register(&at91rm9200_nand_device);
3267c077
AV		 431}
432#else
433void __init at91_add_device_nand(struct at91_nand_data *data) {}
434#endif
435
436
437/* --------------------------------------------------------------------
438 * TWI (i2c)
439 * -------------------------------------------------------------------- */
440
441#if defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
69c5eccd
AV		 442
443static struct resource twi_resources[] = {
444 [0] = {
445 .start = AT91RM9200_BASE_TWI,
446 .end = AT91RM9200_BASE_TWI + SZ_16K - 1,
447 .flags = IORESOURCE_MEM,
448 },
449 [1] = {
450 .start = AT91RM9200_ID_TWI,
451 .end = AT91RM9200_ID_TWI,
452 .flags = IORESOURCE_IRQ,
453 },
454};
455
3267c077
AV		 456static struct platform_device at91rm9200_twi_device = {
457 .name = "at91_i2c",
458 .id = -1,
69c5eccd
AV		 459 .resource = twi_resources,
460 .num_resources = ARRAY_SIZE(twi_resources),
3267c077
AV		 461};
462
463void __init at91_add_device_i2c(void)
464{
465 /* pins used for TWI interface */
466 at91_set_A_periph(AT91_PIN_PA25, 0); /* TWD */
467 at91_set_multi_drive(AT91_PIN_PA25, 1);
468
469 at91_set_A_periph(AT91_PIN_PA26, 0); /* TWCK */
470 at91_set_multi_drive(AT91_PIN_PA26, 1);
471
472 platform_device_register(&at91rm9200_twi_device);
473}
474#else
475void __init at91_add_device_i2c(void) {}
476#endif
477
478
2e836402
AV		 479/* --------------------------------------------------------------------
480 * SPI
481 * -------------------------------------------------------------------- */
482
483#if defined(CONFIG_SPI_AT91) || defined(CONFIG_SPI_AT91_MODULE) || defined(CONFIG_AT91_SPI) || defined(CONFIG_AT91_SPI_MODULE)
484static u64 spi_dmamask = 0xffffffffUL;
485
69c5eccd 486static struct resource spi_resources[] = {
2e836402 487 [0] = {
72729910
AV		 488 .start = AT91RM9200_BASE_SPI,
489 .end = AT91RM9200_BASE_SPI + SZ_16K - 1,
2e836402
AV		 490 .flags = IORESOURCE_MEM,
491 },
492 [1] = {
72729910
AV		 493 .start = AT91RM9200_ID_SPI,
494 .end = AT91RM9200_ID_SPI,
2e836402
AV		 495 .flags = IORESOURCE_IRQ,
496 },
497};
498
499static struct platform_device at91rm9200_spi_device = {
500 .name = "at91_spi",
501 .id = 0,
502 .dev = {
69c5eccd
AV		 503 .dma_mask = &spi_dmamask,
504 .coherent_dma_mask = 0xffffffff,
2e836402 505 },
69c5eccd
AV		 506 .resource = spi_resources,
507 .num_resources = ARRAY_SIZE(spi_resources),
2e836402
AV		 508};
509
69c5eccd 510static const unsigned spi_standard_cs[4] = { AT91_PIN_PA3, AT91_PIN_PA4, AT91_PIN_PA5, AT91_PIN_PA6 };
2e836402
AV		 511
512void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
513{
514 int i;
515 unsigned long cs_pin;
516
517 at91_set_A_periph(AT91_PIN_PA0, 0); /* MISO */
518 at91_set_A_periph(AT91_PIN_PA1, 0); /* MOSI */
519 at91_set_A_periph(AT91_PIN_PA2, 0); /* SPCK */
520
521 /* Enable SPI chip-selects */
522 for (i = 0; i < nr_devices; i++) {
523 if (devices[i].controller_data)
524 cs_pin = (unsigned long) devices[i].controller_data;
525 else
69c5eccd 526 cs_pin = spi_standard_cs[devices[i].chip_select];
2e836402
AV		 527
528#ifdef CONFIG_SPI_AT91_MANUAL_CS
529 at91_set_gpio_output(cs_pin, 1);
530#else
531 at91_set_A_periph(cs_pin, 0);
532#endif
533
534 /* pass chip-select pin to driver */
535 devices[i].controller_data = (void *) cs_pin;
536 }
537
538 spi_register_board_info(devices, nr_devices);
69c5eccd 539 at91_clock_associate("spi_clk", &at91rm9200_spi_device.dev, "spi");
2e836402
AV		 540 platform_device_register(&at91rm9200_spi_device);
541}
542#else
543void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
544#endif
545
546
3267c077
AV		 547/* --------------------------------------------------------------------
548 * RTC
549 * -------------------------------------------------------------------- */
550
69c5eccd 551#if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE)
3267c077
AV		 552static struct platform_device at91rm9200_rtc_device = {
553 .name = "at91_rtc",
554 .id = -1,
555 .num_resources = 0,
556};
557
2e836402 558static void __init at91_add_device_rtc(void)
3267c077
AV		 559{
560 platform_device_register(&at91rm9200_rtc_device);
561}
562#else
2e836402
AV		 563static void __init at91_add_device_rtc(void) {}
564#endif
565
566
567/* --------------------------------------------------------------------
568 * Watchdog
569 * -------------------------------------------------------------------- */
570
69c5eccd 571#if defined(CONFIG_AT91RM9200_WATCHDOG) || defined(CONFIG_AT91RM9200_WATCHDOG_MODULE)
2e836402
AV		 572static struct platform_device at91rm9200_wdt_device = {
573 .name = "at91_wdt",
574 .id = -1,
575 .num_resources = 0,
576};
577
578static void __init at91_add_device_watchdog(void)
579{
580 platform_device_register(&at91rm9200_wdt_device);
581}
582#else
583static void __init at91_add_device_watchdog(void) {}
3267c077
AV		 584#endif
585
586
cc2832a1
AV		 587/* --------------------------------------------------------------------
588 * LEDs
589 * -------------------------------------------------------------------- */
590
591#if defined(CONFIG_LEDS)
592u8 at91_leds_cpu;
593u8 at91_leds_timer;
594
595void __init at91_init_leds(u8 cpu_led, u8 timer_led)
596{
2e836402
AV		 597 at91_leds_cpu = cpu_led;
598 at91_leds_timer = timer_led;
cc2832a1 599}
cc2832a1
AV		 600#else
601void __init at91_init_leds(u8 cpu_led, u8 timer_led) {}
602#endif
603
604
2e836402
AV		 605/* --------------------------------------------------------------------
606 * UART
607 * -------------------------------------------------------------------- */
608
749c4e60 609#if defined(CONFIG_SERIAL_ATMEL)
2e836402
AV		 610static struct resource dbgu_resources[] = {
611 [0] = {
612 .start = AT91_VA_BASE_SYS + AT91_DBGU,
613 .end = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
614 .flags = IORESOURCE_MEM,
615 },
616 [1] = {
617 .start = AT91_ID_SYS,
618 .end = AT91_ID_SYS,
619 .flags = IORESOURCE_IRQ,
620 },
621};
622
73e2798b 623static struct atmel_uart_data dbgu_data = {
2e836402
AV		 624 .use_dma_tx = 0,
625 .use_dma_rx = 0, /* DBGU not capable of receive DMA */
75d35213 626 .regs = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
2e836402
AV		 627};
628
629static struct platform_device at91rm9200_dbgu_device = {
1e8ea802 630 .name = "atmel_usart",
2e836402
AV		 631 .id = 0,
632 .dev = {
633 .platform_data = &dbgu_data,
634 .coherent_dma_mask = 0xffffffff,
635 },
636 .resource = dbgu_resources,
637 .num_resources = ARRAY_SIZE(dbgu_resources),
638};
639
640static inline void configure_dbgu_pins(void)
641{
642 at91_set_A_periph(AT91_PIN_PA30, 0); /* DRXD */
643 at91_set_A_periph(AT91_PIN_PA31, 1); /* DTXD */
644}
645
646static struct resource uart0_resources[] = {
647 [0] = {
72729910
AV		 648 .start = AT91RM9200_BASE_US0,
649 .end = AT91RM9200_BASE_US0 + SZ_16K - 1,
2e836402
AV		 650 .flags = IORESOURCE_MEM,
651 },
652 [1] = {
72729910
AV		 653 .start = AT91RM9200_ID_US0,
654 .end = AT91RM9200_ID_US0,
2e836402
AV		 655 .flags = IORESOURCE_IRQ,
656 },
657};
658
73e2798b 659static struct atmel_uart_data uart0_data = {
2e836402
AV		 660 .use_dma_tx = 1,
661 .use_dma_rx = 1,
662};
663
664static struct platform_device at91rm9200_uart0_device = {
1e8ea802 665 .name = "atmel_usart",
2e836402
AV		 666 .id = 1,
667 .dev = {
668 .platform_data = &uart0_data,
669 .coherent_dma_mask = 0xffffffff,
670 },
671 .resource = uart0_resources,
672 .num_resources = ARRAY_SIZE(uart0_resources),
673};
674
675static inline void configure_usart0_pins(void)
676{
677 at91_set_A_periph(AT91_PIN_PA17, 1); /* TXD0 */
678 at91_set_A_periph(AT91_PIN_PA18, 0); /* RXD0 */
679 at91_set_A_periph(AT91_PIN_PA20, 0); /* CTS0 */
680
681 /*
682 * AT91RM9200 Errata #39 - RTS0 is not internally connected to PA21.
683 * We need to drive the pin manually. Default is off (RTS is active low).
684 */
685 at91_set_gpio_output(AT91_PIN_PA21, 1);
686}
687
688static struct resource uart1_resources[] = {
689 [0] = {
72729910
AV		 690 .start = AT91RM9200_BASE_US1,
691 .end = AT91RM9200_BASE_US1 + SZ_16K - 1,
2e836402
AV		 692 .flags = IORESOURCE_MEM,
693 },
694 [1] = {
72729910
AV		 695 .start = AT91RM9200_ID_US1,
696 .end = AT91RM9200_ID_US1,
2e836402
AV		 697 .flags = IORESOURCE_IRQ,
698 },
699};
700
73e2798b 701static struct atmel_uart_data uart1_data = {
2e836402
AV		 702 .use_dma_tx = 1,
703 .use_dma_rx = 1,
704};
705
706static struct platform_device at91rm9200_uart1_device = {
1e8ea802 707 .name = "atmel_usart",
2e836402
AV		 708 .id = 2,
709 .dev = {
710 .platform_data = &uart1_data,
711 .coherent_dma_mask = 0xffffffff,
712 },
713 .resource = uart1_resources,
714 .num_resources = ARRAY_SIZE(uart1_resources),
715};
716
717static inline void configure_usart1_pins(void)
718{
719 at91_set_A_periph(AT91_PIN_PB18, 0); /* RI1 */
720 at91_set_A_periph(AT91_PIN_PB19, 0); /* DTR1 */
721 at91_set_A_periph(AT91_PIN_PB20, 1); /* TXD1 */
722 at91_set_A_periph(AT91_PIN_PB21, 0); /* RXD1 */
723 at91_set_A_periph(AT91_PIN_PB23, 0); /* DCD1 */
724 at91_set_A_periph(AT91_PIN_PB24, 0); /* CTS1 */
725 at91_set_A_periph(AT91_PIN_PB25, 0); /* DSR1 */
726 at91_set_A_periph(AT91_PIN_PB26, 0); /* RTS1 */
727}
728
729static struct resource uart2_resources[] = {
730 [0] = {
72729910
AV		 731 .start = AT91RM9200_BASE_US2,
732 .end = AT91RM9200_BASE_US2 + SZ_16K - 1,
2e836402
AV		 733 .flags = IORESOURCE_MEM,
734 },
735 [1] = {
72729910
AV		 736 .start = AT91RM9200_ID_US2,
737 .end = AT91RM9200_ID_US2,
2e836402
AV		 738 .flags = IORESOURCE_IRQ,
739 },
740};
741
73e2798b 742static struct atmel_uart_data uart2_data = {
2e836402
AV		 743 .use_dma_tx = 1,
744 .use_dma_rx = 1,
745};
746
747static struct platform_device at91rm9200_uart2_device = {
1e8ea802 748 .name = "atmel_usart",
2e836402
AV		 749 .id = 3,
750 .dev = {
751 .platform_data = &uart2_data,
752 .coherent_dma_mask = 0xffffffff,
753 },
754 .resource = uart2_resources,
755 .num_resources = ARRAY_SIZE(uart2_resources),
756};
757
758static inline void configure_usart2_pins(void)
759{
760 at91_set_A_periph(AT91_PIN_PA22, 0); /* RXD2 */
761 at91_set_A_periph(AT91_PIN_PA23, 1); /* TXD2 */
762}
763
764static struct resource uart3_resources[] = {
765 [0] = {
72729910
AV		 766 .start = AT91RM9200_BASE_US3,
767 .end = AT91RM9200_BASE_US3 + SZ_16K - 1,
2e836402
AV		 768 .flags = IORESOURCE_MEM,
769 },
770 [1] = {
72729910
AV		 771 .start = AT91RM9200_ID_US3,
772 .end = AT91RM9200_ID_US3,
2e836402
AV		 773 .flags = IORESOURCE_IRQ,
774 },
775};
776
73e2798b 777static struct atmel_uart_data uart3_data = {
2e836402
AV		 778 .use_dma_tx = 1,
779 .use_dma_rx = 1,
780};
781
782static struct platform_device at91rm9200_uart3_device = {
1e8ea802 783 .name = "atmel_usart",
2e836402
AV		 784 .id = 4,
785 .dev = {
786 .platform_data = &uart3_data,
787 .coherent_dma_mask = 0xffffffff,
788 },
789 .resource = uart3_resources,
790 .num_resources = ARRAY_SIZE(uart3_resources),
791};
792
793static inline void configure_usart3_pins(void)
794{
795 at91_set_B_periph(AT91_PIN_PA5, 1); /* TXD3 */
796 at91_set_B_periph(AT91_PIN_PA6, 0); /* RXD3 */
797}
798
73e2798b
HS		 799struct platform_device *at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
800struct platform_device *atmel_default_console_device; /* the serial console device */
2e836402
AV		 801
802void __init at91_init_serial(struct at91_uart_config *config)
803{
804 int i;
805
806 /* Fill in list of supported UARTs */
807 for (i = 0; i < config->nr_tty; i++) {
808 switch (config->tty_map[i]) {
809 case 0:
810 configure_usart0_pins();
811 at91_uarts[i] = &at91rm9200_uart0_device;
812 at91_clock_associate("usart0_clk", &at91rm9200_uart0_device.dev, "usart");
813 break;
814 case 1:
815 configure_usart1_pins();
816 at91_uarts[i] = &at91rm9200_uart1_device;
817 at91_clock_associate("usart1_clk", &at91rm9200_uart1_device.dev, "usart");
818 break;
819 case 2:
820 configure_usart2_pins();
821 at91_uarts[i] = &at91rm9200_uart2_device;
822 at91_clock_associate("usart2_clk", &at91rm9200_uart2_device.dev, "usart");
823 break;
824 case 3:
825 configure_usart3_pins();
826 at91_uarts[i] = &at91rm9200_uart3_device;
827 at91_clock_associate("usart3_clk", &at91rm9200_uart3_device.dev, "usart");
828 break;
829 case 4:
830 configure_dbgu_pins();
831 at91_uarts[i] = &at91rm9200_dbgu_device;
832 at91_clock_associate("mck", &at91rm9200_dbgu_device.dev, "usart");
833 break;
834 default:
835 continue;
836 }
837 at91_uarts[i]->id = i; /* update ID number to mapped ID */
838 }
839
840 /* Set serial console device */
73e2798b
HS		 841 if (config->console_tty < ATMEL_MAX_UART)
842 atmel_default_console_device = at91_uarts[config->console_tty];
843 if (!atmel_default_console_device)
2e836402
AV		 844 printk(KERN_INFO "AT91: No default serial console defined.\n");
845}
846
847void __init at91_add_device_serial(void)
848{
849 int i;
850
73e2798b 851 for (i = 0; i < ATMEL_MAX_UART; i++) {
2e836402
AV		 852 if (at91_uarts[i])
853 platform_device_register(at91_uarts[i]);
854 }
855}
856#else
857void __init at91_init_serial(struct at91_uart_config *config) {}
858void __init at91_add_device_serial(void) {}
859#endif
860
861
73a59c1c 862/* -------------------------------------------------------------------- */
2e836402
AV		 863
864/*
865 * These devices are always present and don't need any board-specific
866 * setup.
867 */
868static int __init at91_add_standard_devices(void)
869{
870 at91_add_device_rtc();
871 at91_add_device_watchdog();
872 return 0;
873}
874
875arch_initcall(at91_add_standard_devices);
Linux kernel - Deliverables
This page took 0.25294 seconds and 5 git commands to generate.