Commit | Line | Data |
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73a59c1c | 1 | /* |
9d041268 | 2 | * linux/arch/arm/mach-at91/at91rm9200_time.c |
73a59c1c SP |
3 | * |
4 | * Copyright (C) 2003 SAN People | |
5 | * Copyright (C) 2003 ATMEL | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
20 | */ | |
21 | ||
5e802dfa | 22 | #include <linux/kernel.h> |
73a59c1c | 23 | #include <linux/interrupt.h> |
07d265dd | 24 | #include <linux/irq.h> |
5e802dfa | 25 | #include <linux/clockchips.h> |
9fce85c7 | 26 | #include <linux/export.h> |
73a59c1c | 27 | |
73a59c1c SP |
28 | #include <asm/mach/time.h> |
29 | ||
a09e64fb | 30 | #include <mach/at91_st.h> |
55d8baee | 31 | |
963151f2 | 32 | static unsigned long last_crtr; |
5e802dfa DB |
33 | static u32 irqmask; |
34 | static struct clock_event_device clkevt; | |
963151f2 | 35 | |
2f5893cf JCPV |
36 | #define RM9200_TIMER_LATCH ((AT91_SLOW_CLOCK + HZ/2) / HZ) |
37 | ||
73a59c1c | 38 | /* |
5e802dfa DB |
39 | * The ST_CRTR is updated asynchronously to the master clock ... but |
40 | * the updates as seen by the CPU don't seem to be strictly monotonic. | |
41 | * Waiting until we read the same value twice avoids glitching. | |
73a59c1c | 42 | */ |
5e802dfa DB |
43 | static inline unsigned long read_CRTR(void) |
44 | { | |
73a59c1c SP |
45 | unsigned long x1, x2; |
46 | ||
5e9cf5e1 | 47 | x1 = at91_st_read(AT91_ST_CRTR); |
73a59c1c | 48 | do { |
5e9cf5e1 | 49 | x2 = at91_st_read(AT91_ST_CRTR); |
5e802dfa DB |
50 | if (x1 == x2) |
51 | break; | |
52 | x1 = x2; | |
53 | } while (1); | |
73a59c1c SP |
54 | return x1; |
55 | } | |
56 | ||
73a59c1c SP |
57 | /* |
58 | * IRQ handler for the timer. | |
59 | */ | |
0cd61b68 | 60 | static irqreturn_t at91rm9200_timer_interrupt(int irq, void *dev_id) |
73a59c1c | 61 | { |
5e9cf5e1 | 62 | u32 sr = at91_st_read(AT91_ST_SR) & irqmask; |
73a59c1c | 63 | |
501d7038 UKK |
64 | /* |
65 | * irqs should be disabled here, but as the irq is shared they are only | |
66 | * guaranteed to be off if the timer irq is registered first. | |
67 | */ | |
68 | WARN_ON_ONCE(!irqs_disabled()); | |
69 | ||
5e802dfa DB |
70 | /* simulate "oneshot" timer with alarm */ |
71 | if (sr & AT91_ST_ALMS) { | |
72 | clkevt.event_handler(&clkevt); | |
73 | return IRQ_HANDLED; | |
74 | } | |
73a59c1c | 75 | |
5e802dfa DB |
76 | /* periodic mode should handle delayed ticks */ |
77 | if (sr & AT91_ST_PITS) { | |
78 | u32 crtr = read_CRTR(); | |
73a59c1c | 79 | |
2f5893cf JCPV |
80 | while (((crtr - last_crtr) & AT91_ST_CRTV) >= RM9200_TIMER_LATCH) { |
81 | last_crtr += RM9200_TIMER_LATCH; | |
5e802dfa DB |
82 | clkevt.event_handler(&clkevt); |
83 | } | |
73a59c1c SP |
84 | return IRQ_HANDLED; |
85 | } | |
5e802dfa DB |
86 | |
87 | /* this irq is shared ... */ | |
88 | return IRQ_NONE; | |
73a59c1c SP |
89 | } |
90 | ||
91 | static struct irqaction at91rm9200_timer_irq = { | |
92 | .name = "at91_tick", | |
b30fabad | 93 | .flags = IRQF_SHARED | IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, |
73a59c1c SP |
94 | .handler = at91rm9200_timer_interrupt |
95 | }; | |
96 | ||
8e19608e | 97 | static cycle_t read_clk32k(struct clocksource *cs) |
2a6f9902 | 98 | { |
5e802dfa DB |
99 | return read_CRTR(); |
100 | } | |
2a6f9902 | 101 | |
5e802dfa DB |
102 | static struct clocksource clk32k = { |
103 | .name = "32k_counter", | |
104 | .rating = 150, | |
105 | .read = read_clk32k, | |
106 | .mask = CLOCKSOURCE_MASK(20), | |
5e802dfa DB |
107 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
108 | }; | |
109 | ||
110 | static void | |
111 | clkevt32k_mode(enum clock_event_mode mode, struct clock_event_device *dev) | |
112 | { | |
113 | /* Disable and flush pending timer interrupts */ | |
5e9cf5e1 | 114 | at91_st_write(AT91_ST_IDR, AT91_ST_PITS | AT91_ST_ALMS); |
9e1c0b2e | 115 | at91_st_read(AT91_ST_SR); |
2a6f9902 | 116 | |
5e802dfa DB |
117 | last_crtr = read_CRTR(); |
118 | switch (mode) { | |
119 | case CLOCK_EVT_MODE_PERIODIC: | |
120 | /* PIT for periodic irqs; fixed rate of 1/HZ */ | |
121 | irqmask = AT91_ST_PITS; | |
5e9cf5e1 | 122 | at91_st_write(AT91_ST_PIMR, RM9200_TIMER_LATCH); |
5e802dfa DB |
123 | break; |
124 | case CLOCK_EVT_MODE_ONESHOT: | |
125 | /* ALM for oneshot irqs, set by next_event() | |
126 | * before 32 seconds have passed | |
127 | */ | |
128 | irqmask = AT91_ST_ALMS; | |
5e9cf5e1 | 129 | at91_st_write(AT91_ST_RTAR, last_crtr); |
5e802dfa DB |
130 | break; |
131 | case CLOCK_EVT_MODE_SHUTDOWN: | |
132 | case CLOCK_EVT_MODE_UNUSED: | |
133 | case CLOCK_EVT_MODE_RESUME: | |
134 | irqmask = 0; | |
135 | break; | |
136 | } | |
5e9cf5e1 | 137 | at91_st_write(AT91_ST_IER, irqmask); |
5e802dfa | 138 | } |
2a6f9902 | 139 | |
5e802dfa DB |
140 | static int |
141 | clkevt32k_next_event(unsigned long delta, struct clock_event_device *dev) | |
142 | { | |
5e802dfa DB |
143 | u32 alm; |
144 | int status = 0; | |
145 | ||
146 | BUG_ON(delta < 2); | |
147 | ||
5e802dfa DB |
148 | /* The alarm IRQ uses absolute time (now+delta), not the relative |
149 | * time (delta) in our calling convention. Like all clockevents | |
150 | * using such "match" hardware, we have a race to defend against. | |
151 | * | |
152 | * Our defense here is to have set up the clockevent device so the | |
153 | * delta is at least two. That way we never end up writing RTAR | |
154 | * with the value then held in CRTR ... which would mean the match | |
155 | * wouldn't trigger until 32 seconds later, after CRTR wraps. | |
156 | */ | |
157 | alm = read_CRTR(); | |
158 | ||
159 | /* Cancel any pending alarm; flush any pending IRQ */ | |
5e9cf5e1 | 160 | at91_st_write(AT91_ST_RTAR, alm); |
9e1c0b2e | 161 | at91_st_read(AT91_ST_SR); |
d100f259 | 162 | |
5e802dfa DB |
163 | /* Schedule alarm by writing RTAR. */ |
164 | alm += delta; | |
5e9cf5e1 | 165 | at91_st_write(AT91_ST_RTAR, alm); |
5e802dfa | 166 | |
5e802dfa | 167 | return status; |
2a6f9902 AV |
168 | } |
169 | ||
5e802dfa DB |
170 | static struct clock_event_device clkevt = { |
171 | .name = "at91_tick", | |
172 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, | |
173 | .shift = 32, | |
174 | .rating = 150, | |
5e802dfa DB |
175 | .set_next_event = clkevt32k_next_event, |
176 | .set_mode = clkevt32k_mode, | |
177 | }; | |
178 | ||
5e9cf5e1 | 179 | void __iomem *at91_st_base; |
9fce85c7 | 180 | EXPORT_SYMBOL_GPL(at91_st_base); |
5e9cf5e1 JCPV |
181 | |
182 | void __init at91rm9200_ioremap_st(u32 addr) | |
183 | { | |
184 | at91_st_base = ioremap(addr, 256); | |
185 | if (!at91_st_base) | |
186 | panic("Impossible to ioremap ST\n"); | |
187 | } | |
188 | ||
73a59c1c | 189 | /* |
5e802dfa | 190 | * ST (system timer) module supports both clockevents and clocksource. |
73a59c1c SP |
191 | */ |
192 | void __init at91rm9200_timer_init(void) | |
193 | { | |
5e802dfa | 194 | /* Disable all timer interrupts, and clear any pending ones */ |
5e9cf5e1 | 195 | at91_st_write(AT91_ST_IDR, |
5e802dfa | 196 | AT91_ST_PITS | AT91_ST_WDOVF | AT91_ST_RTTINC | AT91_ST_ALMS); |
9e1c0b2e | 197 | at91_st_read(AT91_ST_SR); |
73a59c1c | 198 | |
2a6f9902 | 199 | /* Make IRQs happen for the system timer */ |
85ebea12 | 200 | setup_irq(NR_IRQS_LEGACY + AT91_ID_SYS, &at91rm9200_timer_irq); |
73a59c1c | 201 | |
5e802dfa DB |
202 | /* The 32KiHz "Slow Clock" (tick every 30517.58 nanoseconds) is used |
203 | * directly for the clocksource and all clockevents, after adjusting | |
204 | * its prescaler from the 1 Hz default. | |
205 | */ | |
5e9cf5e1 | 206 | at91_st_write(AT91_ST_RTMR, 1); |
73a59c1c | 207 | |
5e802dfa DB |
208 | /* Setup timer clockevent, with minimum of two ticks (important!!) */ |
209 | clkevt.mult = div_sc(AT91_SLOW_CLOCK, NSEC_PER_SEC, clkevt.shift); | |
210 | clkevt.max_delta_ns = clockevent_delta2ns(AT91_ST_ALMV, &clkevt); | |
211 | clkevt.min_delta_ns = clockevent_delta2ns(2, &clkevt) + 1; | |
320ab2b0 | 212 | clkevt.cpumask = cpumask_of(0); |
5e802dfa | 213 | clockevents_register_device(&clkevt); |
2a6f9902 | 214 | |
5e802dfa | 215 | /* register clocksource */ |
132b1632 | 216 | clocksource_register_hz(&clk32k, AT91_SLOW_CLOCK); |
73a59c1c SP |
217 | } |
218 | ||
219 | struct sys_timer at91rm9200_timer = { | |
220 | .init = at91rm9200_timer_init, | |
73a59c1c | 221 | }; |
2a6f9902 | 222 |