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ARM: EXYNOS: fix the secondary CPU boot of exynos4212
[deliverable/linux.git] / arch / arm / mach-at91 / at91sam9260_devices.c
CommitLineData
86ad76bb 1/*
9d041268 2 * arch/arm/mach-at91/at91sam9260_devices.c
86ad76bb
AV		 3 *
4 * Copyright (C) 2006 Atmel
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 */
12#include <asm/mach/arch.h>
13#include <asm/mach/map.h>
14
c6686ff9 15#include <linux/dma-mapping.h>
2f8163ba 16#include <linux/gpio.h>
86ad76bb 17#include <linux/platform_device.h>
f230d3f5 18#include <linux/i2c-gpio.h>
86ad76bb 19
67b5d7b3
MR		 20#include <linux/platform_data/at91_adc.h>
21
a09e64fb
RK		 22#include <mach/cpu.h>
23#include <mach/at91sam9260.h>
24#include <mach/at91sam9260_matrix.h>
4342d647 25#include <mach/at91_matrix.h>
a09e64fb 26#include <mach/at91sam9_smc.h>
67b5d7b3 27#include <mach/at91_adc.h>
ac11a1d4 28#include <mach/hardware.h>
86ad76bb 29
43d2f532 30#include "board.h"
86ad76bb
AV		 31#include "generic.h"
32
86ad76bb
AV		 33
34/* --------------------------------------------------------------------
35 * USB Host
36 * -------------------------------------------------------------------- */
37
38#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
c6686ff9 39static u64 ohci_dmamask = DMA_BIT_MASK(32);
86ad76bb
AV		 40static struct at91_usbh_data usbh_data;
41
42static struct resource usbh_resources[] = {
43 [0] = {
44 .start = AT91SAM9260_UHP_BASE,
45 .end = AT91SAM9260_UHP_BASE + SZ_1M - 1,
46 .flags = IORESOURCE_MEM,
47 },
48 [1] = {
8fe82a55
LD		 49 .start = NR_IRQS_LEGACY + AT91SAM9260_ID_UHP,
50 .end = NR_IRQS_LEGACY + AT91SAM9260_ID_UHP,
86ad76bb
AV		 51 .flags = IORESOURCE_IRQ,
52 },
53};
54
55static struct platform_device at91_usbh_device = {
56 .name = "at91_ohci",
57 .id = -1,
58 .dev = {
59 .dma_mask = &ohci_dmamask,
c6686ff9 60 .coherent_dma_mask = DMA_BIT_MASK(32),
86ad76bb
AV		 61 .platform_data = &usbh_data,
62 },
63 .resource = usbh_resources,
64 .num_resources = ARRAY_SIZE(usbh_resources),
65};
66
67void __init at91_add_device_usbh(struct at91_usbh_data *data)
68{
1fcaea7e
TP		 69 int i;
70
86ad76bb
AV		 71 if (!data)
72 return;
73
1fcaea7e
TP		 74 /* Enable overcurrent notification */
75 for (i = 0; i < data->ports; i++) {
641f3ce6 76 if (gpio_is_valid(data->overcurrent_pin[i]))
1fcaea7e
TP		 77 at91_set_gpio_input(data->overcurrent_pin[i], 1);
78 }
79
86ad76bb
AV		 80 usbh_data = *data;
81 platform_device_register(&at91_usbh_device);
82}
83#else
84void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
85#endif
86
87
88/* --------------------------------------------------------------------
89 * USB Device (Gadget)
90 * -------------------------------------------------------------------- */
91
e8c9dc93 92#if defined(CONFIG_USB_AT91) || defined(CONFIG_USB_AT91_MODULE)
86ad76bb
AV		 93static struct at91_udc_data udc_data;
94
95static struct resource udc_resources[] = {
96 [0] = {
97 .start = AT91SAM9260_BASE_UDP,
98 .end = AT91SAM9260_BASE_UDP + SZ_16K - 1,
99 .flags = IORESOURCE_MEM,
100 },
101 [1] = {
8fe82a55
LD		 102 .start = NR_IRQS_LEGACY + AT91SAM9260_ID_UDP,
103 .end = NR_IRQS_LEGACY + AT91SAM9260_ID_UDP,
86ad76bb
AV		 104 .flags = IORESOURCE_IRQ,
105 },
106};
107
108static struct platform_device at91_udc_device = {
109 .name = "at91_udc",
110 .id = -1,
111 .dev = {
112 .platform_data = &udc_data,
113 },
114 .resource = udc_resources,
115 .num_resources = ARRAY_SIZE(udc_resources),
116};
117
118void __init at91_add_device_udc(struct at91_udc_data *data)
119{
120 if (!data)
121 return;
122
cc9f9aef 123 if (gpio_is_valid(data->vbus_pin)) {
86ad76bb
AV		 124 at91_set_gpio_input(data->vbus_pin, 0);
125 at91_set_deglitch(data->vbus_pin, 1);
126 }
127
128 /* Pullup pin is handled internally by USB device peripheral */
129
130 udc_data = *data;
131 platform_device_register(&at91_udc_device);
132}
133#else
134void __init at91_add_device_udc(struct at91_udc_data *data) {}
135#endif
136
137
138/* --------------------------------------------------------------------
139 * Ethernet
140 * -------------------------------------------------------------------- */
141
142#if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
c6686ff9 143static u64 eth_dmamask = DMA_BIT_MASK(32);
84e0cdb0 144static struct macb_platform_data eth_data;
86ad76bb
AV		 145
146static struct resource eth_resources[] = {
147 [0] = {
148 .start = AT91SAM9260_BASE_EMAC,
149 .end = AT91SAM9260_BASE_EMAC + SZ_16K - 1,
150 .flags = IORESOURCE_MEM,
151 },
152 [1] = {
8fe82a55
LD		 153 .start = NR_IRQS_LEGACY + AT91SAM9260_ID_EMAC,
154 .end = NR_IRQS_LEGACY + AT91SAM9260_ID_EMAC,
86ad76bb
AV		 155 .flags = IORESOURCE_IRQ,
156 },
157};
158
159static struct platform_device at91sam9260_eth_device = {
160 .name = "macb",
161 .id = -1,
162 .dev = {
163 .dma_mask = &eth_dmamask,
c6686ff9 164 .coherent_dma_mask = DMA_BIT_MASK(32),
86ad76bb
AV		 165 .platform_data = &eth_data,
166 },
167 .resource = eth_resources,
168 .num_resources = ARRAY_SIZE(eth_resources),
169};
170
84e0cdb0 171void __init at91_add_device_eth(struct macb_platform_data *data)
86ad76bb
AV		 172{
173 if (!data)
174 return;
175
cc9f9aef 176 if (gpio_is_valid(data->phy_irq_pin)) {
86ad76bb
AV		 177 at91_set_gpio_input(data->phy_irq_pin, 0);
178 at91_set_deglitch(data->phy_irq_pin, 1);
179 }
180
181 /* Pins used for MII and RMII */
182 at91_set_A_periph(AT91_PIN_PA19, 0); /* ETXCK_EREFCK */
183 at91_set_A_periph(AT91_PIN_PA17, 0); /* ERXDV */
184 at91_set_A_periph(AT91_PIN_PA14, 0); /* ERX0 */
185 at91_set_A_periph(AT91_PIN_PA15, 0); /* ERX1 */
186 at91_set_A_periph(AT91_PIN_PA18, 0); /* ERXER */
187 at91_set_A_periph(AT91_PIN_PA16, 0); /* ETXEN */
188 at91_set_A_periph(AT91_PIN_PA12, 0); /* ETX0 */
189 at91_set_A_periph(AT91_PIN_PA13, 0); /* ETX1 */
190 at91_set_A_periph(AT91_PIN_PA21, 0); /* EMDIO */
191 at91_set_A_periph(AT91_PIN_PA20, 0); /* EMDC */
192
193 if (!data->is_rmii) {
194 at91_set_B_periph(AT91_PIN_PA28, 0); /* ECRS */
195 at91_set_B_periph(AT91_PIN_PA29, 0); /* ECOL */
196 at91_set_B_periph(AT91_PIN_PA25, 0); /* ERX2 */
197 at91_set_B_periph(AT91_PIN_PA26, 0); /* ERX3 */
198 at91_set_B_periph(AT91_PIN_PA27, 0); /* ERXCK */
199 at91_set_B_periph(AT91_PIN_PA23, 0); /* ETX2 */
200 at91_set_B_periph(AT91_PIN_PA24, 0); /* ETX3 */
201 at91_set_B_periph(AT91_PIN_PA22, 0); /* ETXER */
202 }
203
204 eth_data = *data;
205 platform_device_register(&at91sam9260_eth_device);
206}
207#else
84e0cdb0 208void __init at91_add_device_eth(struct macb_platform_data *data) {}
86ad76bb
AV		 209#endif
210
211
864f38eb
RE		 212/* --------------------------------------------------------------------
213 * MMC / SD Slot for Atmel MCI Driver
214 * -------------------------------------------------------------------- */
215
4cf3326a 216#if IS_ENABLED(CONFIG_MMC_ATMELMCI)
864f38eb
RE		 217static u64 mmc_dmamask = DMA_BIT_MASK(32);
218static struct mci_platform_data mmc_data;
219
220static struct resource mmc_resources[] = {
221 [0] = {
222 .start = AT91SAM9260_BASE_MCI,
223 .end = AT91SAM9260_BASE_MCI + SZ_16K - 1,
224 .flags = IORESOURCE_MEM,
225 },
226 [1] = {
8fe82a55
LD		 227 .start = NR_IRQS_LEGACY + AT91SAM9260_ID_MCI,
228 .end = NR_IRQS_LEGACY + AT91SAM9260_ID_MCI,
864f38eb
RE		 229 .flags = IORESOURCE_IRQ,
230 },
231};
232
233static struct platform_device at91sam9260_mmc_device = {
234 .name = "atmel_mci",
235 .id = -1,
236 .dev = {
237 .dma_mask = &mmc_dmamask,
238 .coherent_dma_mask = DMA_BIT_MASK(32),
239 .platform_data = &mmc_data,
240 },
241 .resource = mmc_resources,
242 .num_resources = ARRAY_SIZE(mmc_resources),
243};
244
245void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data)
246{
247 unsigned int i;
248 unsigned int slot_count = 0;
249
250 if (!data)
251 return;
252
2c96a293 253 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
864f38eb
RE		 254 if (data->slot[i].bus_width) {
255 /* input/irq */
cc9f9aef 256 if (gpio_is_valid(data->slot[i].detect_pin)) {
864f38eb
RE		 257 at91_set_gpio_input(data->slot[i].detect_pin, 1);
258 at91_set_deglitch(data->slot[i].detect_pin, 1);
259 }
cc9f9aef 260 if (gpio_is_valid(data->slot[i].wp_pin))
864f38eb
RE		 261 at91_set_gpio_input(data->slot[i].wp_pin, 1);
262
263 switch (i) {
264 case 0:
265 /* CMD */
266 at91_set_A_periph(AT91_PIN_PA7, 1);
267 /* DAT0, maybe DAT1..DAT3 */
268 at91_set_A_periph(AT91_PIN_PA6, 1);
269 if (data->slot[i].bus_width == 4) {
270 at91_set_A_periph(AT91_PIN_PA9, 1);
271 at91_set_A_periph(AT91_PIN_PA10, 1);
272 at91_set_A_periph(AT91_PIN_PA11, 1);
273 }
274 slot_count++;
275 break;
276 case 1:
277 /* CMD */
278 at91_set_B_periph(AT91_PIN_PA1, 1);
279 /* DAT0, maybe DAT1..DAT3 */
280 at91_set_B_periph(AT91_PIN_PA0, 1);
281 if (data->slot[i].bus_width == 4) {
282 at91_set_B_periph(AT91_PIN_PA5, 1);
283 at91_set_B_periph(AT91_PIN_PA4, 1);
284 at91_set_B_periph(AT91_PIN_PA3, 1);
285 }
286 slot_count++;
287 break;
288 default:
289 printk(KERN_ERR
290 "AT91: SD/MMC slot %d not available\n", i);
291 break;
292 }
293 }
294 }
295
296 if (slot_count) {
297 /* CLK */
298 at91_set_A_periph(AT91_PIN_PA8, 0);
299
300 mmc_data = *data;
301 platform_device_register(&at91sam9260_mmc_device);
302 }
303}
304#else
305void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data) {}
306#endif
307
86ad76bb
AV		 308
309/* --------------------------------------------------------------------
310 * NAND / SmartMedia
311 * -------------------------------------------------------------------- */
312
f6ed6f78 313#if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
3c3796cc 314static struct atmel_nand_data nand_data;
86ad76bb
AV		 315
316#define NAND_BASE AT91_CHIPSELECT_3
317
318static struct resource nand_resources[] = {
d7a2415f 319 [0] = {
86ad76bb 320 .start = NAND_BASE,
22823558 321 .end = NAND_BASE + SZ_256M - 1,
86ad76bb 322 .flags = IORESOURCE_MEM,
d7a2415f
AV		 323 },
324 [1] = {
d28edd1b
JCPV		 325 .start = AT91SAM9260_BASE_ECC,
326 .end = AT91SAM9260_BASE_ECC + SZ_512 - 1,
d7a2415f 327 .flags = IORESOURCE_MEM,
86ad76bb
AV		 328 }
329};
330
331static struct platform_device at91sam9260_nand_device = {
3c3796cc 332 .name = "atmel_nand",
86ad76bb
AV		 333 .id = -1,
334 .dev = {
335 .platform_data = &nand_data,
336 },
337 .resource = nand_resources,
338 .num_resources = ARRAY_SIZE(nand_resources),
339};
340
3c3796cc 341void __init at91_add_device_nand(struct atmel_nand_data *data)
86ad76bb 342{
461d3b4d 343 unsigned long csa;
86ad76bb
AV		 344
345 if (!data)
346 return;
347
4342d647
JCPV		 348 csa = at91_matrix_read(AT91_MATRIX_EBICSA);
349 at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
86ad76bb 350
86ad76bb 351 /* enable pin */
cc9f9aef 352 if (gpio_is_valid(data->enable_pin))
86ad76bb
AV		 353 at91_set_gpio_output(data->enable_pin, 1);
354
355 /* ready/busy pin */
cc9f9aef 356 if (gpio_is_valid(data->rdy_pin))
86ad76bb
AV		 357 at91_set_gpio_input(data->rdy_pin, 1);
358
359 /* card detect pin */
cc9f9aef 360 if (gpio_is_valid(data->det_pin))
86ad76bb
AV		 361 at91_set_gpio_input(data->det_pin, 1);
362
363 nand_data = *data;
364 platform_device_register(&at91sam9260_nand_device);
365}
366#else
3c3796cc 367void __init at91_add_device_nand(struct atmel_nand_data *data) {}
86ad76bb
AV		 368#endif
369
370
371/* --------------------------------------------------------------------
372 * TWI (i2c)
373 * -------------------------------------------------------------------- */
374
f230d3f5
AV		 375/*
376 * Prefer the GPIO code since the TWI controller isn't robust
377 * (gets overruns and underruns under load) and can only issue
378 * repeated STARTs in one scenario (the driver doesn't yet handle them).
379 */
380
381#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
382
383static struct i2c_gpio_platform_data pdata = {
384 .sda_pin = AT91_PIN_PA23,
385 .sda_is_open_drain = 1,
386 .scl_pin = AT91_PIN_PA24,
387 .scl_is_open_drain = 1,
388 .udelay = 2, /* ~100 kHz */
389};
390
391static struct platform_device at91sam9260_twi_device = {
392 .name = "i2c-gpio",
7840487c 393 .id = 0,
f230d3f5
AV		 394 .dev.platform_data = &pdata,
395};
396
397void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
398{
399 at91_set_GPIO_periph(AT91_PIN_PA23, 1); /* TWD (SDA) */
400 at91_set_multi_drive(AT91_PIN_PA23, 1);
401
402 at91_set_GPIO_periph(AT91_PIN_PA24, 1); /* TWCK (SCL) */
403 at91_set_multi_drive(AT91_PIN_PA24, 1);
404
405 i2c_register_board_info(0, devices, nr_devices);
406 platform_device_register(&at91sam9260_twi_device);
407}
408
409#elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
86ad76bb
AV		 410
411static struct resource twi_resources[] = {
412 [0] = {
413 .start = AT91SAM9260_BASE_TWI,
414 .end = AT91SAM9260_BASE_TWI + SZ_16K - 1,
415 .flags = IORESOURCE_MEM,
416 },
417 [1] = {
8fe82a55
LD		 418 .start = NR_IRQS_LEGACY + AT91SAM9260_ID_TWI,
419 .end = NR_IRQS_LEGACY + AT91SAM9260_ID_TWI,
86ad76bb
AV		 420 .flags = IORESOURCE_IRQ,
421 },
422};
423
424static struct platform_device at91sam9260_twi_device = {
302090a6 425 .id = 0,
86ad76bb
AV		 426 .resource = twi_resources,
427 .num_resources = ARRAY_SIZE(twi_resources),
428};
429
f230d3f5 430void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
86ad76bb 431{
fac368a0
NV		 432 /* IP version is not the same on 9260 and g20 */
433 if (cpu_is_at91sam9g20()) {
434 at91sam9260_twi_device.name = "i2c-at91sam9g20";
435 } else {
436 at91sam9260_twi_device.name = "i2c-at91sam9260";
437 }
438
86ad76bb
AV		 439 /* pins used for TWI interface */
440 at91_set_A_periph(AT91_PIN_PA23, 0); /* TWD */
441 at91_set_multi_drive(AT91_PIN_PA23, 1);
442
443 at91_set_A_periph(AT91_PIN_PA24, 0); /* TWCK */
444 at91_set_multi_drive(AT91_PIN_PA24, 1);
445
f230d3f5 446 i2c_register_board_info(0, devices, nr_devices);
86ad76bb
AV		 447 platform_device_register(&at91sam9260_twi_device);
448}
449#else
f230d3f5 450void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
86ad76bb
AV		 451#endif
452
453
454/* --------------------------------------------------------------------
455 * SPI
456 * -------------------------------------------------------------------- */
457
458#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
c6686ff9 459static u64 spi_dmamask = DMA_BIT_MASK(32);
86ad76bb
AV		 460
461static struct resource spi0_resources[] = {
462 [0] = {
463 .start = AT91SAM9260_BASE_SPI0,
464 .end = AT91SAM9260_BASE_SPI0 + SZ_16K - 1,
465 .flags = IORESOURCE_MEM,
466 },
467 [1] = {
8fe82a55
LD		 468 .start = NR_IRQS_LEGACY + AT91SAM9260_ID_SPI0,
469 .end = NR_IRQS_LEGACY + AT91SAM9260_ID_SPI0,
86ad76bb
AV		 470 .flags = IORESOURCE_IRQ,
471 },
472};
473
474static struct platform_device at91sam9260_spi0_device = {
475 .name = "atmel_spi",
476 .id = 0,
477 .dev = {
478 .dma_mask = &spi_dmamask,
c6686ff9 479 .coherent_dma_mask = DMA_BIT_MASK(32),
86ad76bb
AV		 480 },
481 .resource = spi0_resources,
482 .num_resources = ARRAY_SIZE(spi0_resources),
483};
484
485static const unsigned spi0_standard_cs[4] = { AT91_PIN_PA3, AT91_PIN_PC11, AT91_PIN_PC16, AT91_PIN_PC17 };
486
487static struct resource spi1_resources[] = {
488 [0] = {
489 .start = AT91SAM9260_BASE_SPI1,
490 .end = AT91SAM9260_BASE_SPI1 + SZ_16K - 1,
491 .flags = IORESOURCE_MEM,
492 },
493 [1] = {
8fe82a55
LD		 494 .start = NR_IRQS_LEGACY + AT91SAM9260_ID_SPI1,
495 .end = NR_IRQS_LEGACY + AT91SAM9260_ID_SPI1,
86ad76bb
AV		 496 .flags = IORESOURCE_IRQ,
497 },
498};
499
500static struct platform_device at91sam9260_spi1_device = {
501 .name = "atmel_spi",
502 .id = 1,
503 .dev = {
504 .dma_mask = &spi_dmamask,
c6686ff9 505 .coherent_dma_mask = DMA_BIT_MASK(32),
86ad76bb
AV		 506 },
507 .resource = spi1_resources,
508 .num_resources = ARRAY_SIZE(spi1_resources),
509};
510
511static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB3, AT91_PIN_PC5, AT91_PIN_PC4, AT91_PIN_PC3 };
512
513void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
514{
515 int i;
516 unsigned long cs_pin;
517 short enable_spi0 = 0;
518 short enable_spi1 = 0;
519
520 /* Choose SPI chip-selects */
521 for (i = 0; i < nr_devices; i++) {
522 if (devices[i].controller_data)
523 cs_pin = (unsigned long) devices[i].controller_data;
524 else if (devices[i].bus_num == 0)
525 cs_pin = spi0_standard_cs[devices[i].chip_select];
526 else
527 cs_pin = spi1_standard_cs[devices[i].chip_select];
528
0c2c1f62
NF		 529 if (!gpio_is_valid(cs_pin))
530 continue;
531
86ad76bb
AV		 532 if (devices[i].bus_num == 0)
533 enable_spi0 = 1;
534 else
535 enable_spi1 = 1;
536
537 /* enable chip-select pin */
538 at91_set_gpio_output(cs_pin, 1);
539
540 /* pass chip-select pin to driver */
541 devices[i].controller_data = (void *) cs_pin;
542 }
543
544 spi_register_board_info(devices, nr_devices);
545
546 /* Configure SPI bus(es) */
547 if (enable_spi0) {
548 at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
549 at91_set_A_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
550 at91_set_A_periph(AT91_PIN_PA2, 0); /* SPI1_SPCK */
551
86ad76bb
AV		 552 platform_device_register(&at91sam9260_spi0_device);
553 }
554 if (enable_spi1) {
555 at91_set_A_periph(AT91_PIN_PB0, 0); /* SPI1_MISO */
556 at91_set_A_periph(AT91_PIN_PB1, 0); /* SPI1_MOSI */
557 at91_set_A_periph(AT91_PIN_PB2, 0); /* SPI1_SPCK */
558
86ad76bb
AV		 559 platform_device_register(&at91sam9260_spi1_device);
560 }
561}
562#else
563void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
564#endif
565
566
e5f40bfa
AV		 567/* --------------------------------------------------------------------
568 * Timer/Counter blocks
569 * -------------------------------------------------------------------- */
570
571#ifdef CONFIG_ATMEL_TCLIB
572
573static struct resource tcb0_resources[] = {
574 [0] = {
575 .start = AT91SAM9260_BASE_TCB0,
29831297 576 .end = AT91SAM9260_BASE_TCB0 + SZ_256 - 1,
e5f40bfa
AV		 577 .flags = IORESOURCE_MEM,
578 },
579 [1] = {
8fe82a55
LD		 580 .start = NR_IRQS_LEGACY + AT91SAM9260_ID_TC0,
581 .end = NR_IRQS_LEGACY + AT91SAM9260_ID_TC0,
e5f40bfa
AV		 582 .flags = IORESOURCE_IRQ,
583 },
584 [2] = {
8fe82a55
LD		 585 .start = NR_IRQS_LEGACY + AT91SAM9260_ID_TC1,
586 .end = NR_IRQS_LEGACY + AT91SAM9260_ID_TC1,
e5f40bfa
AV		 587 .flags = IORESOURCE_IRQ,
588 },
589 [3] = {
8fe82a55
LD		 590 .start = NR_IRQS_LEGACY + AT91SAM9260_ID_TC2,
591 .end = NR_IRQS_LEGACY + AT91SAM9260_ID_TC2,
e5f40bfa
AV		 592 .flags = IORESOURCE_IRQ,
593 },
594};
595
596static struct platform_device at91sam9260_tcb0_device = {
597 .name = "atmel_tcb",
598 .id = 0,
599 .resource = tcb0_resources,
600 .num_resources = ARRAY_SIZE(tcb0_resources),
601};
602
603static struct resource tcb1_resources[] = {
604 [0] = {
605 .start = AT91SAM9260_BASE_TCB1,
29831297 606 .end = AT91SAM9260_BASE_TCB1 + SZ_256 - 1,
e5f40bfa
AV		 607 .flags = IORESOURCE_MEM,
608 },
609 [1] = {
8fe82a55
LD		 610 .start = NR_IRQS_LEGACY + AT91SAM9260_ID_TC3,
611 .end = NR_IRQS_LEGACY + AT91SAM9260_ID_TC3,
e5f40bfa
AV		 612 .flags = IORESOURCE_IRQ,
613 },
614 [2] = {
8fe82a55
LD		 615 .start = NR_IRQS_LEGACY + AT91SAM9260_ID_TC4,
616 .end = NR_IRQS_LEGACY + AT91SAM9260_ID_TC4,
e5f40bfa
AV		 617 .flags = IORESOURCE_IRQ,
618 },
619 [3] = {
8fe82a55
LD		 620 .start = NR_IRQS_LEGACY + AT91SAM9260_ID_TC5,
621 .end = NR_IRQS_LEGACY + AT91SAM9260_ID_TC5,
e5f40bfa
AV		 622 .flags = IORESOURCE_IRQ,
623 },
624};
625
626static struct platform_device at91sam9260_tcb1_device = {
627 .name = "atmel_tcb",
628 .id = 1,
629 .resource = tcb1_resources,
630 .num_resources = ARRAY_SIZE(tcb1_resources),
631};
632
633static void __init at91_add_device_tc(void)
634{
e5f40bfa 635 platform_device_register(&at91sam9260_tcb0_device);
e5f40bfa
AV		 636 platform_device_register(&at91sam9260_tcb1_device);
637}
638#else
639static void __init at91_add_device_tc(void) { }
640#endif
641
642
884f5a6a
AV		 643/* --------------------------------------------------------------------
644 * RTT
645 * -------------------------------------------------------------------- */
646
647static struct resource rtt_resources[] = {
648 {
eab5fd67
JCPV		 649 .start = AT91SAM9260_BASE_RTT,
650 .end = AT91SAM9260_BASE_RTT + SZ_16 - 1,
884f5a6a 651 .flags = IORESOURCE_MEM,
b3af8b49
JCPV		 652 }, {
653 .flags = IORESOURCE_MEM,
e402af6c
LD		 654 }, {
655 .flags = IORESOURCE_IRQ,
b3af8b49 656 },
884f5a6a
AV		 657};
658
659static struct platform_device at91sam9260_rtt_device = {
660 .name = "at91_rtt",
4fd9212c 661 .id = 0,
884f5a6a 662 .resource = rtt_resources,
884f5a6a
AV		 663};
664
205056a3
JCPV		 665
666#if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
667static void __init at91_add_device_rtt_rtc(void)
668{
669 at91sam9260_rtt_device.name = "rtc-at91sam9";
b3af8b49
JCPV		 670 /*
671 * The second resource is needed:
672 * GPBR will serve as the storage for RTC time offset
673 */
e402af6c 674 at91sam9260_rtt_device.num_resources = 3;
b3af8b49
JCPV		 675 rtt_resources[1].start = AT91SAM9260_BASE_GPBR +
676 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
677 rtt_resources[1].end = rtt_resources[1].start + 3;
e402af6c
LD		 678 rtt_resources[2].start = NR_IRQS_LEGACY + AT91_ID_SYS;
679 rtt_resources[2].end = NR_IRQS_LEGACY + AT91_ID_SYS;
205056a3
JCPV		 680}
681#else
b3af8b49
JCPV		 682static void __init at91_add_device_rtt_rtc(void)
683{
684 /* Only one resource is needed: RTT not used as RTC */
685 at91sam9260_rtt_device.num_resources = 1;
686}
205056a3
JCPV		 687#endif
688
884f5a6a
AV		 689static void __init at91_add_device_rtt(void)
690{
205056a3 691 at91_add_device_rtt_rtc();
884f5a6a
AV		 692 platform_device_register(&at91sam9260_rtt_device);
693}
694
695
696/* --------------------------------------------------------------------
697 * Watchdog
698 * -------------------------------------------------------------------- */
699
2af29b78 700#if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
c1c30a29
JCPV		 701static struct resource wdt_resources[] = {
702 {
703 .start = AT91SAM9260_BASE_WDT,
704 .end = AT91SAM9260_BASE_WDT + SZ_16 - 1,
705 .flags = IORESOURCE_MEM,
706 }
707};
708
884f5a6a
AV		 709static struct platform_device at91sam9260_wdt_device = {
710 .name = "at91_wdt",
711 .id = -1,
c1c30a29
JCPV		 712 .resource = wdt_resources,
713 .num_resources = ARRAY_SIZE(wdt_resources),
884f5a6a
AV		 714};
715
716static void __init at91_add_device_watchdog(void)
717{
718 platform_device_register(&at91sam9260_wdt_device);
719}
720#else
721static void __init at91_add_device_watchdog(void) {}
722#endif
723
724
bfbc3266
AV		 725/* --------------------------------------------------------------------
726 * SSC -- Synchronous Serial Controller
727 * -------------------------------------------------------------------- */
728
729#if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
730static u64 ssc_dmamask = DMA_BIT_MASK(32);
731
732static struct resource ssc_resources[] = {
733 [0] = {
734 .start = AT91SAM9260_BASE_SSC,
735 .end = AT91SAM9260_BASE_SSC + SZ_16K - 1,
736 .flags = IORESOURCE_MEM,
737 },
738 [1] = {
8fe82a55
LD		 739 .start = NR_IRQS_LEGACY + AT91SAM9260_ID_SSC,
740 .end = NR_IRQS_LEGACY + AT91SAM9260_ID_SSC,
bfbc3266
AV		 741 .flags = IORESOURCE_IRQ,
742 },
743};
744
745static struct platform_device at91sam9260_ssc_device = {
636036d2 746 .name = "at91rm9200_ssc",
bfbc3266
AV		 747 .id = 0,
748 .dev = {
749 .dma_mask = &ssc_dmamask,
750 .coherent_dma_mask = DMA_BIT_MASK(32),
751 },
752 .resource = ssc_resources,
753 .num_resources = ARRAY_SIZE(ssc_resources),
754};
755
756static inline void configure_ssc_pins(unsigned pins)
757{
758 if (pins & ATMEL_SSC_TF)
759 at91_set_A_periph(AT91_PIN_PB17, 1);
760 if (pins & ATMEL_SSC_TK)
761 at91_set_A_periph(AT91_PIN_PB16, 1);
762 if (pins & ATMEL_SSC_TD)
763 at91_set_A_periph(AT91_PIN_PB18, 1);
764 if (pins & ATMEL_SSC_RD)
765 at91_set_A_periph(AT91_PIN_PB19, 1);
766 if (pins & ATMEL_SSC_RK)
767 at91_set_A_periph(AT91_PIN_PB20, 1);
768 if (pins & ATMEL_SSC_RF)
769 at91_set_A_periph(AT91_PIN_PB21, 1);
770}
771
772/*
773 * SSC controllers are accessed through library code, instead of any
774 * kind of all-singing/all-dancing driver. For example one could be
775 * used by a particular I2S audio codec's driver, while another one
776 * on the same system might be used by a custom data capture driver.
777 */
778void __init at91_add_device_ssc(unsigned id, unsigned pins)
779{
780 struct platform_device *pdev;
781
782 /*
783 * NOTE: caller is responsible for passing information matching
784 * "pins" to whatever will be using each particular controller.
785 */
786 switch (id) {
787 case AT91SAM9260_ID_SSC:
788 pdev = &at91sam9260_ssc_device;
789 configure_ssc_pins(pins);
bfbc3266
AV		 790 break;
791 default:
792 return;
793 }
794
795 platform_device_register(pdev);
796}
797
798#else
799void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
800#endif
801
802
86ad76bb
AV		 803/* --------------------------------------------------------------------
804 * UART
805 * -------------------------------------------------------------------- */
806#if defined(CONFIG_SERIAL_ATMEL)
807static struct resource dbgu_resources[] = {
808 [0] = {
13079a73
JCPV		 809 .start = AT91SAM9260_BASE_DBGU,
810 .end = AT91SAM9260_BASE_DBGU + SZ_512 - 1,
86ad76bb
AV		 811 .flags = IORESOURCE_MEM,
812 },
813 [1] = {
8fe82a55
LD		 814 .start = NR_IRQS_LEGACY + AT91_ID_SYS,
815 .end = NR_IRQS_LEGACY + AT91_ID_SYS,
86ad76bb
AV		 816 .flags = IORESOURCE_IRQ,
817 },
818};
819
820static struct atmel_uart_data dbgu_data = {
821 .use_dma_tx = 0,
822 .use_dma_rx = 0, /* DBGU not capable of receive DMA */
354e57f3 823 .rts_gpio = -EINVAL,
86ad76bb
AV		 824};
825
c6686ff9
AV		 826static u64 dbgu_dmamask = DMA_BIT_MASK(32);
827
86ad76bb
AV		 828static struct platform_device at91sam9260_dbgu_device = {
829 .name = "atmel_usart",
830 .id = 0,
831 .dev = {
c6686ff9
AV		 832 .dma_mask = &dbgu_dmamask,
833 .coherent_dma_mask = DMA_BIT_MASK(32),
834 .platform_data = &dbgu_data,
86ad76bb
AV		 835 },
836 .resource = dbgu_resources,
837 .num_resources = ARRAY_SIZE(dbgu_resources),
838};
839
840static inline void configure_dbgu_pins(void)
841{
842 at91_set_A_periph(AT91_PIN_PB14, 0); /* DRXD */
843 at91_set_A_periph(AT91_PIN_PB15, 1); /* DTXD */
844}
845
846static struct resource uart0_resources[] = {
847 [0] = {
848 .start = AT91SAM9260_BASE_US0,
849 .end = AT91SAM9260_BASE_US0 + SZ_16K - 1,
850 .flags = IORESOURCE_MEM,
851 },
852 [1] = {
8fe82a55
LD		 853 .start = NR_IRQS_LEGACY + AT91SAM9260_ID_US0,
854 .end = NR_IRQS_LEGACY + AT91SAM9260_ID_US0,
86ad76bb
AV		 855 .flags = IORESOURCE_IRQ,
856 },
857};
858
859static struct atmel_uart_data uart0_data = {
860 .use_dma_tx = 1,
861 .use_dma_rx = 1,
354e57f3 862 .rts_gpio = -EINVAL,
86ad76bb
AV		 863};
864
c6686ff9
AV		 865static u64 uart0_dmamask = DMA_BIT_MASK(32);
866
86ad76bb
AV		 867static struct platform_device at91sam9260_uart0_device = {
868 .name = "atmel_usart",
869 .id = 1,
870 .dev = {
c6686ff9
AV		 871 .dma_mask = &uart0_dmamask,
872 .coherent_dma_mask = DMA_BIT_MASK(32),
873 .platform_data = &uart0_data,
86ad76bb
AV		 874 },
875 .resource = uart0_resources,
876 .num_resources = ARRAY_SIZE(uart0_resources),
877};
878
c8f385a6 879static inline void configure_usart0_pins(unsigned pins)
86ad76bb
AV		 880{
881 at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD0 */
882 at91_set_A_periph(AT91_PIN_PB5, 0); /* RXD0 */
c8f385a6
AV		 883
884 if (pins & ATMEL_UART_RTS)
885 at91_set_A_periph(AT91_PIN_PB26, 0); /* RTS0 */
886 if (pins & ATMEL_UART_CTS)
887 at91_set_A_periph(AT91_PIN_PB27, 0); /* CTS0 */
888 if (pins & ATMEL_UART_DTR)
889 at91_set_A_periph(AT91_PIN_PB24, 0); /* DTR0 */
890 if (pins & ATMEL_UART_DSR)
891 at91_set_A_periph(AT91_PIN_PB22, 0); /* DSR0 */
892 if (pins & ATMEL_UART_DCD)
893 at91_set_A_periph(AT91_PIN_PB23, 0); /* DCD0 */
894 if (pins & ATMEL_UART_RI)
895 at91_set_A_periph(AT91_PIN_PB25, 0); /* RI0 */
86ad76bb
AV		 896}
897
898static struct resource uart1_resources[] = {
899 [0] = {
900 .start = AT91SAM9260_BASE_US1,
901 .end = AT91SAM9260_BASE_US1 + SZ_16K - 1,
902 .flags = IORESOURCE_MEM,
903 },
904 [1] = {
8fe82a55
LD		 905 .start = NR_IRQS_LEGACY + AT91SAM9260_ID_US1,
906 .end = NR_IRQS_LEGACY + AT91SAM9260_ID_US1,
86ad76bb
AV		 907 .flags = IORESOURCE_IRQ,
908 },
909};
910
911static struct atmel_uart_data uart1_data = {
912 .use_dma_tx = 1,
913 .use_dma_rx = 1,
354e57f3 914 .rts_gpio = -EINVAL,
86ad76bb
AV		 915};
916
c6686ff9
AV		 917static u64 uart1_dmamask = DMA_BIT_MASK(32);
918
86ad76bb
AV		 919static struct platform_device at91sam9260_uart1_device = {
920 .name = "atmel_usart",
921 .id = 2,
922 .dev = {
c6686ff9
AV		 923 .dma_mask = &uart1_dmamask,
924 .coherent_dma_mask = DMA_BIT_MASK(32),
925 .platform_data = &uart1_data,
86ad76bb
AV		 926 },
927 .resource = uart1_resources,
928 .num_resources = ARRAY_SIZE(uart1_resources),
929};
930
c8f385a6 931static inline void configure_usart1_pins(unsigned pins)
86ad76bb
AV		 932{
933 at91_set_A_periph(AT91_PIN_PB6, 1); /* TXD1 */
934 at91_set_A_periph(AT91_PIN_PB7, 0); /* RXD1 */
c8f385a6
AV		 935
936 if (pins & ATMEL_UART_RTS)
937 at91_set_A_periph(AT91_PIN_PB28, 0); /* RTS1 */
938 if (pins & ATMEL_UART_CTS)
939 at91_set_A_periph(AT91_PIN_PB29, 0); /* CTS1 */
86ad76bb
AV		 940}
941
942static struct resource uart2_resources[] = {
943 [0] = {
944 .start = AT91SAM9260_BASE_US2,
945 .end = AT91SAM9260_BASE_US2 + SZ_16K - 1,
946 .flags = IORESOURCE_MEM,
947 },
948 [1] = {
8fe82a55
LD		 949 .start = NR_IRQS_LEGACY + AT91SAM9260_ID_US2,
950 .end = NR_IRQS_LEGACY + AT91SAM9260_ID_US2,
86ad76bb
AV		 951 .flags = IORESOURCE_IRQ,
952 },
953};
954
955static struct atmel_uart_data uart2_data = {
956 .use_dma_tx = 1,
957 .use_dma_rx = 1,
354e57f3 958 .rts_gpio = -EINVAL,
86ad76bb
AV		 959};
960
c6686ff9
AV		 961static u64 uart2_dmamask = DMA_BIT_MASK(32);
962
86ad76bb
AV		 963static struct platform_device at91sam9260_uart2_device = {
964 .name = "atmel_usart",
965 .id = 3,
966 .dev = {
c6686ff9
AV		 967 .dma_mask = &uart2_dmamask,
968 .coherent_dma_mask = DMA_BIT_MASK(32),
969 .platform_data = &uart2_data,
86ad76bb
AV		 970 },
971 .resource = uart2_resources,
972 .num_resources = ARRAY_SIZE(uart2_resources),
973};
974
c8f385a6 975static inline void configure_usart2_pins(unsigned pins)
86ad76bb
AV		 976{
977 at91_set_A_periph(AT91_PIN_PB8, 1); /* TXD2 */
978 at91_set_A_periph(AT91_PIN_PB9, 0); /* RXD2 */
c8f385a6
AV		 979
980 if (pins & ATMEL_UART_RTS)
981 at91_set_A_periph(AT91_PIN_PA4, 0); /* RTS2 */
982 if (pins & ATMEL_UART_CTS)
983 at91_set_A_periph(AT91_PIN_PA5, 0); /* CTS2 */
86ad76bb
AV		 984}
985
986static struct resource uart3_resources[] = {
987 [0] = {
988 .start = AT91SAM9260_BASE_US3,
989 .end = AT91SAM9260_BASE_US3 + SZ_16K - 1,
990 .flags = IORESOURCE_MEM,
991 },
992 [1] = {
8fe82a55
LD		 993 .start = NR_IRQS_LEGACY + AT91SAM9260_ID_US3,
994 .end = NR_IRQS_LEGACY + AT91SAM9260_ID_US3,
86ad76bb
AV		 995 .flags = IORESOURCE_IRQ,
996 },
997};
998
999static struct atmel_uart_data uart3_data = {
1000 .use_dma_tx = 1,
1001 .use_dma_rx = 1,
354e57f3 1002 .rts_gpio = -EINVAL,
86ad76bb
AV		 1003};
1004
c6686ff9
AV		 1005static u64 uart3_dmamask = DMA_BIT_MASK(32);
1006
86ad76bb
AV		 1007static struct platform_device at91sam9260_uart3_device = {
1008 .name = "atmel_usart",
1009 .id = 4,
1010 .dev = {
c6686ff9
AV		 1011 .dma_mask = &uart3_dmamask,
1012 .coherent_dma_mask = DMA_BIT_MASK(32),
1013 .platform_data = &uart3_data,
86ad76bb
AV		 1014 },
1015 .resource = uart3_resources,
1016 .num_resources = ARRAY_SIZE(uart3_resources),
1017};
1018
c8f385a6 1019static inline void configure_usart3_pins(unsigned pins)
86ad76bb
AV		 1020{
1021 at91_set_A_periph(AT91_PIN_PB10, 1); /* TXD3 */
1022 at91_set_A_periph(AT91_PIN_PB11, 0); /* RXD3 */
c8f385a6
AV		 1023
1024 if (pins & ATMEL_UART_RTS)
1025 at91_set_B_periph(AT91_PIN_PC8, 0); /* RTS3 */
1026 if (pins & ATMEL_UART_CTS)
1027 at91_set_B_periph(AT91_PIN_PC10, 0); /* CTS3 */
86ad76bb
AV		 1028}
1029
1030static struct resource uart4_resources[] = {
1031 [0] = {
1032 .start = AT91SAM9260_BASE_US4,
1033 .end = AT91SAM9260_BASE_US4 + SZ_16K - 1,
1034 .flags = IORESOURCE_MEM,
1035 },
1036 [1] = {
8fe82a55
LD		 1037 .start = NR_IRQS_LEGACY + AT91SAM9260_ID_US4,
1038 .end = NR_IRQS_LEGACY + AT91SAM9260_ID_US4,
86ad76bb
AV		 1039 .flags = IORESOURCE_IRQ,
1040 },
1041};
1042
1043static struct atmel_uart_data uart4_data = {
1044 .use_dma_tx = 1,
1045 .use_dma_rx = 1,
354e57f3 1046 .rts_gpio = -EINVAL,
86ad76bb
AV		 1047};
1048
c6686ff9
AV		 1049static u64 uart4_dmamask = DMA_BIT_MASK(32);
1050
86ad76bb
AV		 1051static struct platform_device at91sam9260_uart4_device = {
1052 .name = "atmel_usart",
1053 .id = 5,
1054 .dev = {
c6686ff9
AV		 1055 .dma_mask = &uart4_dmamask,
1056 .coherent_dma_mask = DMA_BIT_MASK(32),
1057 .platform_data = &uart4_data,
86ad76bb
AV		 1058 },
1059 .resource = uart4_resources,
1060 .num_resources = ARRAY_SIZE(uart4_resources),
1061};
1062
1063static inline void configure_usart4_pins(void)
1064{
1065 at91_set_B_periph(AT91_PIN_PA31, 1); /* TXD4 */
1066 at91_set_B_periph(AT91_PIN_PA30, 0); /* RXD4 */
1067}
1068
1069static struct resource uart5_resources[] = {
1070 [0] = {
1071 .start = AT91SAM9260_BASE_US5,
1072 .end = AT91SAM9260_BASE_US5 + SZ_16K - 1,
1073 .flags = IORESOURCE_MEM,
1074 },
1075 [1] = {
8fe82a55
LD		 1076 .start = NR_IRQS_LEGACY + AT91SAM9260_ID_US5,
1077 .end = NR_IRQS_LEGACY + AT91SAM9260_ID_US5,
86ad76bb
AV		 1078 .flags = IORESOURCE_IRQ,
1079 },
1080};
1081
1082static struct atmel_uart_data uart5_data = {
1083 .use_dma_tx = 1,
1084 .use_dma_rx = 1,
354e57f3 1085 .rts_gpio = -EINVAL,
86ad76bb
AV		 1086};
1087
c6686ff9
AV		 1088static u64 uart5_dmamask = DMA_BIT_MASK(32);
1089
86ad76bb
AV		 1090static struct platform_device at91sam9260_uart5_device = {
1091 .name = "atmel_usart",
1092 .id = 6,
1093 .dev = {
c6686ff9
AV		 1094 .dma_mask = &uart5_dmamask,
1095 .coherent_dma_mask = DMA_BIT_MASK(32),
1096 .platform_data = &uart5_data,
86ad76bb
AV		 1097 },
1098 .resource = uart5_resources,
1099 .num_resources = ARRAY_SIZE(uart5_resources),
1100};
1101
1102static inline void configure_usart5_pins(void)
1103{
1104 at91_set_A_periph(AT91_PIN_PB12, 1); /* TXD5 */
1105 at91_set_A_periph(AT91_PIN_PB13, 0); /* RXD5 */
1106}
1107
11aadac4 1108static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
86ad76bb 1109
c8f385a6
AV		 1110void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1111{
1112 struct platform_device *pdev;
2b348e2f 1113 struct atmel_uart_data *pdata;
c8f385a6
AV		 1114
1115 switch (id) {
1116 case 0: /* DBGU */
1117 pdev = &at91sam9260_dbgu_device;
1118 configure_dbgu_pins();
c8f385a6
AV		 1119 break;
1120 case AT91SAM9260_ID_US0:
1121 pdev = &at91sam9260_uart0_device;
1122 configure_usart0_pins(pins);
c8f385a6
AV		 1123 break;
1124 case AT91SAM9260_ID_US1:
1125 pdev = &at91sam9260_uart1_device;
1126 configure_usart1_pins(pins);
c8f385a6
AV		 1127 break;
1128 case AT91SAM9260_ID_US2:
1129 pdev = &at91sam9260_uart2_device;
1130 configure_usart2_pins(pins);
c8f385a6
AV		 1131 break;
1132 case AT91SAM9260_ID_US3:
1133 pdev = &at91sam9260_uart3_device;
1134 configure_usart3_pins(pins);
c8f385a6
AV		 1135 break;
1136 case AT91SAM9260_ID_US4:
1137 pdev = &at91sam9260_uart4_device;
1138 configure_usart4_pins();
c8f385a6
AV		 1139 break;
1140 case AT91SAM9260_ID_US5:
1141 pdev = &at91sam9260_uart5_device;
1142 configure_usart5_pins();
c8f385a6
AV		 1143 break;
1144 default:
1145 return;
1146 }
2b348e2f
JCPV		 1147 pdata = pdev->dev.platform_data;
1148 pdata->num = portnr; /* update to mapped ID */
c8f385a6
AV		 1149
1150 if (portnr < ATMEL_MAX_UART)
1151 at91_uarts[portnr] = pdev;
1152}
1153
86ad76bb
AV		 1154void __init at91_add_device_serial(void)
1155{
1156 int i;
1157
1158 for (i = 0; i < ATMEL_MAX_UART; i++) {
1159 if (at91_uarts[i])
1160 platform_device_register(at91_uarts[i]);
1161 }
1162}
1163#else
c8f385a6 1164void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
86ad76bb
AV		 1165void __init at91_add_device_serial(void) {}
1166#endif
1167
fb85205a
SM		 1168/* --------------------------------------------------------------------
1169 * CF/IDE
1170 * -------------------------------------------------------------------- */
1171
cf844751 1172#if defined(CONFIG_PATA_AT91) || defined(CONFIG_PATA_AT91_MODULE) || \
fb85205a
SM		 1173 defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE)
1174
1175static struct at91_cf_data cf0_data;
1176
1177static struct resource cf0_resources[] = {
1178 [0] = {
1179 .start = AT91_CHIPSELECT_4,
1180 .end = AT91_CHIPSELECT_4 + SZ_256M - 1,
1181 .flags = IORESOURCE_MEM,
1182 }
1183};
1184
1185static struct platform_device cf0_device = {
1186 .id = 0,
1187 .dev = {
1188 .platform_data = &cf0_data,
1189 },
1190 .resource = cf0_resources,
1191 .num_resources = ARRAY_SIZE(cf0_resources),
1192};
1193
1194static struct at91_cf_data cf1_data;
1195
1196static struct resource cf1_resources[] = {
1197 [0] = {
1198 .start = AT91_CHIPSELECT_5,
1199 .end = AT91_CHIPSELECT_5 + SZ_256M - 1,
1200 .flags = IORESOURCE_MEM,
1201 }
1202};
1203
1204static struct platform_device cf1_device = {
1205 .id = 1,
1206 .dev = {
1207 .platform_data = &cf1_data,
1208 },
1209 .resource = cf1_resources,
1210 .num_resources = ARRAY_SIZE(cf1_resources),
1211};
1212
1213void __init at91_add_device_cf(struct at91_cf_data *data)
1214{
1215 struct platform_device *pdev;
1216 unsigned long csa;
1217
1218 if (!data)
1219 return;
1220
4342d647 1221 csa = at91_matrix_read(AT91_MATRIX_EBICSA);
fb85205a
SM		 1222
1223 switch (data->chipselect) {
1224 case 4:
1225 at91_set_multi_drive(AT91_PIN_PC8, 0);
1226 at91_set_A_periph(AT91_PIN_PC8, 0);
1227 csa |= AT91_MATRIX_CS4A_SMC_CF1;
1228 cf0_data = *data;
1229 pdev = &cf0_device;
1230 break;
1231 case 5:
1232 at91_set_multi_drive(AT91_PIN_PC9, 0);
1233 at91_set_A_periph(AT91_PIN_PC9, 0);
1234 csa |= AT91_MATRIX_CS5A_SMC_CF2;
1235 cf1_data = *data;
1236 pdev = &cf1_device;
1237 break;
1238 default:
1239 printk(KERN_ERR "AT91 CF: bad chip-select requested (%u)\n",
1240 data->chipselect);
1241 return;
1242 }
1243
4342d647 1244 at91_matrix_write(AT91_MATRIX_EBICSA, csa);
fb85205a 1245
cc9f9aef 1246 if (gpio_is_valid(data->rst_pin)) {
fb85205a
SM		 1247 at91_set_multi_drive(data->rst_pin, 0);
1248 at91_set_gpio_output(data->rst_pin, 1);
1249 }
1250
cc9f9aef 1251 if (gpio_is_valid(data->irq_pin)) {
fb85205a
SM		 1252 at91_set_gpio_input(data->irq_pin, 0);
1253 at91_set_deglitch(data->irq_pin, 1);
1254 }
1255
cc9f9aef 1256 if (gpio_is_valid(data->det_pin)) {
fb85205a
SM		 1257 at91_set_gpio_input(data->det_pin, 0);
1258 at91_set_deglitch(data->det_pin, 1);
1259 }
1260
1261 at91_set_B_periph(AT91_PIN_PC6, 0); /* CFCE1 */
1262 at91_set_B_periph(AT91_PIN_PC7, 0); /* CFCE2 */
1263 at91_set_A_periph(AT91_PIN_PC10, 0); /* CFRNW */
1264 at91_set_A_periph(AT91_PIN_PC15, 1); /* NWAIT */
1265
cb46a256 1266 if (IS_ENABLED(CONFIG_PATA_AT91) && (data->flags & AT91_CF_TRUE_IDE))
fb85205a 1267 pdev->name = "pata_at91";
fb85205a
SM		 1268 else
1269 pdev->name = "at91_cf";
1270
1271 platform_device_register(pdev);
1272}
1273
1274#else
1275void __init at91_add_device_cf(struct at91_cf_data * data) {}
1276#endif
86ad76bb 1277
67b5d7b3
MR		 1278/* --------------------------------------------------------------------
1279 * ADCs
1280 * -------------------------------------------------------------------- */
1281
1282#if IS_ENABLED(CONFIG_AT91_ADC)
1283static struct at91_adc_data adc_data;
1284
1285static struct resource adc_resources[] = {
1286 [0] = {
1287 .start = AT91SAM9260_BASE_ADC,
1288 .end = AT91SAM9260_BASE_ADC + SZ_16K - 1,
1289 .flags = IORESOURCE_MEM,
1290 },
1291 [1] = {
8fe82a55
LD		 1292 .start = NR_IRQS_LEGACY + AT91SAM9260_ID_ADC,
1293 .end = NR_IRQS_LEGACY + AT91SAM9260_ID_ADC,
67b5d7b3
MR		 1294 .flags = IORESOURCE_IRQ,
1295 },
1296};
1297
1298static struct platform_device at91_adc_device = {
301841a6 1299 .name = "at91sam9260-adc",
67b5d7b3
MR		 1300 .id = -1,
1301 .dev = {
1302 .platform_data = &adc_data,
1303 },
1304 .resource = adc_resources,
1305 .num_resources = ARRAY_SIZE(adc_resources),
1306};
1307
1308static struct at91_adc_trigger at91_adc_triggers[] = {
1309 [0] = {
1310 .name = "timer-counter-0",
1311 .value = AT91_ADC_TRGSEL_TC0 | AT91_ADC_TRGEN,
1312 },
1313 [1] = {
1314 .name = "timer-counter-1",
1315 .value = AT91_ADC_TRGSEL_TC1 | AT91_ADC_TRGEN,
1316 },
1317 [2] = {
1318 .name = "timer-counter-2",
1319 .value = AT91_ADC_TRGSEL_TC2 | AT91_ADC_TRGEN,
1320 },
1321 [3] = {
1322 .name = "external",
1323 .value = AT91_ADC_TRGSEL_EXTERNAL | AT91_ADC_TRGEN,
1324 .is_external = true,
1325 },
1326};
1327
1328static struct at91_adc_reg_desc at91_adc_register_g20 = {
1329 .channel_base = AT91_ADC_CHR(0),
1330 .drdy_mask = AT91_ADC_DRDY,
1331 .status_register = AT91_ADC_SR,
1332 .trigger_register = AT91_ADC_MR,
1333};
1334
1335void __init at91_add_device_adc(struct at91_adc_data *data)
1336{
1337 if (!data)
1338 return;
1339
1340 if (test_bit(0, &data->channels_used))
1341 at91_set_A_periph(AT91_PIN_PC0, 0);
1342 if (test_bit(1, &data->channels_used))
1343 at91_set_A_periph(AT91_PIN_PC1, 0);
1344 if (test_bit(2, &data->channels_used))
1345 at91_set_A_periph(AT91_PIN_PC2, 0);
1346 if (test_bit(3, &data->channels_used))
1347 at91_set_A_periph(AT91_PIN_PC3, 0);
1348
1349 if (data->use_external_triggers)
1350 at91_set_A_periph(AT91_PIN_PA22, 0);
1351
1352 data->num_channels = 4;
1353 data->startup_time = 10;
1354 data->registers = &at91_adc_register_g20;
1355 data->trigger_number = 4;
1356 data->trigger_list = at91_adc_triggers;
1357
1358 adc_data = *data;
1359 platform_device_register(&at91_adc_device);
1360}
1361#else
1362void __init at91_add_device_adc(struct at91_adc_data *data) {}
1363#endif
1364
86ad76bb
AV		 1365/* -------------------------------------------------------------------- */
1366/*
1367 * These devices are always present and don't need any board-specific
1368 * setup.
1369 */
1370static int __init at91_add_standard_devices(void)
1371{
8cf93b9c
JCPV		 1372 if (of_have_populated_dt())
1373 return 0;
1374
884f5a6a
AV		 1375 at91_add_device_rtt();
1376 at91_add_device_watchdog();
e5f40bfa 1377 at91_add_device_tc();
86ad76bb
AV		 1378 return 0;
1379}
1380
1381arch_initcall(at91_add_standard_devices);
Linux kernel - Deliverables
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