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Merge tag 'timer' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
[deliverable/linux.git] / arch / arm / mach-at91 / at91sam9260_devices.c
CommitLineData
86ad76bb 1/*
9d041268 2 * arch/arm/mach-at91/at91sam9260_devices.c
86ad76bb
AV		 3 *
4 * Copyright (C) 2006 Atmel
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 */
12#include <asm/mach/arch.h>
13#include <asm/mach/map.h>
14
c6686ff9 15#include <linux/dma-mapping.h>
2f8163ba 16#include <linux/gpio.h>
86ad76bb 17#include <linux/platform_device.h>
f230d3f5 18#include <linux/i2c-gpio.h>
86ad76bb 19
67b5d7b3
MR		 20#include <linux/platform_data/at91_adc.h>
21
a09e64fb 22#include <mach/board.h>
a09e64fb
RK		 23#include <mach/cpu.h>
24#include <mach/at91sam9260.h>
25#include <mach/at91sam9260_matrix.h>
4342d647 26#include <mach/at91_matrix.h>
a09e64fb 27#include <mach/at91sam9_smc.h>
67b5d7b3 28#include <mach/at91_adc.h>
86ad76bb
AV		 29
30#include "generic.h"
31
86ad76bb
AV		 32
33/* --------------------------------------------------------------------
34 * USB Host
35 * -------------------------------------------------------------------- */
36
37#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
c6686ff9 38static u64 ohci_dmamask = DMA_BIT_MASK(32);
86ad76bb
AV		 39static struct at91_usbh_data usbh_data;
40
41static struct resource usbh_resources[] = {
42 [0] = {
43 .start = AT91SAM9260_UHP_BASE,
44 .end = AT91SAM9260_UHP_BASE + SZ_1M - 1,
45 .flags = IORESOURCE_MEM,
46 },
47 [1] = {
8fe82a55
LD		 48 .start = NR_IRQS_LEGACY + AT91SAM9260_ID_UHP,
49 .end = NR_IRQS_LEGACY + AT91SAM9260_ID_UHP,
86ad76bb
AV		 50 .flags = IORESOURCE_IRQ,
51 },
52};
53
54static struct platform_device at91_usbh_device = {
55 .name = "at91_ohci",
56 .id = -1,
57 .dev = {
58 .dma_mask = &ohci_dmamask,
c6686ff9 59 .coherent_dma_mask = DMA_BIT_MASK(32),
86ad76bb
AV		 60 .platform_data = &usbh_data,
61 },
62 .resource = usbh_resources,
63 .num_resources = ARRAY_SIZE(usbh_resources),
64};
65
66void __init at91_add_device_usbh(struct at91_usbh_data *data)
67{
1fcaea7e
TP		 68 int i;
69
86ad76bb
AV		 70 if (!data)
71 return;
72
1fcaea7e
TP		 73 /* Enable overcurrent notification */
74 for (i = 0; i < data->ports; i++) {
75 if (data->overcurrent_pin[i])
76 at91_set_gpio_input(data->overcurrent_pin[i], 1);
77 }
78
86ad76bb
AV		 79 usbh_data = *data;
80 platform_device_register(&at91_usbh_device);
81}
82#else
83void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
84#endif
85
86
87/* --------------------------------------------------------------------
88 * USB Device (Gadget)
89 * -------------------------------------------------------------------- */
90
e8c9dc93 91#if defined(CONFIG_USB_AT91) || defined(CONFIG_USB_AT91_MODULE)
86ad76bb
AV		 92static struct at91_udc_data udc_data;
93
94static struct resource udc_resources[] = {
95 [0] = {
96 .start = AT91SAM9260_BASE_UDP,
97 .end = AT91SAM9260_BASE_UDP + SZ_16K - 1,
98 .flags = IORESOURCE_MEM,
99 },
100 [1] = {
8fe82a55
LD		 101 .start = NR_IRQS_LEGACY + AT91SAM9260_ID_UDP,
102 .end = NR_IRQS_LEGACY + AT91SAM9260_ID_UDP,
86ad76bb
AV		 103 .flags = IORESOURCE_IRQ,
104 },
105};
106
107static struct platform_device at91_udc_device = {
108 .name = "at91_udc",
109 .id = -1,
110 .dev = {
111 .platform_data = &udc_data,
112 },
113 .resource = udc_resources,
114 .num_resources = ARRAY_SIZE(udc_resources),
115};
116
117void __init at91_add_device_udc(struct at91_udc_data *data)
118{
119 if (!data)
120 return;
121
cc9f9aef 122 if (gpio_is_valid(data->vbus_pin)) {
86ad76bb
AV		 123 at91_set_gpio_input(data->vbus_pin, 0);
124 at91_set_deglitch(data->vbus_pin, 1);
125 }
126
127 /* Pullup pin is handled internally by USB device peripheral */
128
129 udc_data = *data;
130 platform_device_register(&at91_udc_device);
131}
132#else
133void __init at91_add_device_udc(struct at91_udc_data *data) {}
134#endif
135
136
137/* --------------------------------------------------------------------
138 * Ethernet
139 * -------------------------------------------------------------------- */
140
141#if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
c6686ff9 142static u64 eth_dmamask = DMA_BIT_MASK(32);
84e0cdb0 143static struct macb_platform_data eth_data;
86ad76bb
AV		 144
145static struct resource eth_resources[] = {
146 [0] = {
147 .start = AT91SAM9260_BASE_EMAC,
148 .end = AT91SAM9260_BASE_EMAC + SZ_16K - 1,
149 .flags = IORESOURCE_MEM,
150 },
151 [1] = {
8fe82a55
LD		 152 .start = NR_IRQS_LEGACY + AT91SAM9260_ID_EMAC,
153 .end = NR_IRQS_LEGACY + AT91SAM9260_ID_EMAC,
86ad76bb
AV		 154 .flags = IORESOURCE_IRQ,
155 },
156};
157
158static struct platform_device at91sam9260_eth_device = {
159 .name = "macb",
160 .id = -1,
161 .dev = {
162 .dma_mask = &eth_dmamask,
c6686ff9 163 .coherent_dma_mask = DMA_BIT_MASK(32),
86ad76bb
AV		 164 .platform_data = &eth_data,
165 },
166 .resource = eth_resources,
167 .num_resources = ARRAY_SIZE(eth_resources),
168};
169
84e0cdb0 170void __init at91_add_device_eth(struct macb_platform_data *data)
86ad76bb
AV		 171{
172 if (!data)
173 return;
174
cc9f9aef 175 if (gpio_is_valid(data->phy_irq_pin)) {
86ad76bb
AV		 176 at91_set_gpio_input(data->phy_irq_pin, 0);
177 at91_set_deglitch(data->phy_irq_pin, 1);
178 }
179
180 /* Pins used for MII and RMII */
181 at91_set_A_periph(AT91_PIN_PA19, 0); /* ETXCK_EREFCK */
182 at91_set_A_periph(AT91_PIN_PA17, 0); /* ERXDV */
183 at91_set_A_periph(AT91_PIN_PA14, 0); /* ERX0 */
184 at91_set_A_periph(AT91_PIN_PA15, 0); /* ERX1 */
185 at91_set_A_periph(AT91_PIN_PA18, 0); /* ERXER */
186 at91_set_A_periph(AT91_PIN_PA16, 0); /* ETXEN */
187 at91_set_A_periph(AT91_PIN_PA12, 0); /* ETX0 */
188 at91_set_A_periph(AT91_PIN_PA13, 0); /* ETX1 */
189 at91_set_A_periph(AT91_PIN_PA21, 0); /* EMDIO */
190 at91_set_A_periph(AT91_PIN_PA20, 0); /* EMDC */
191
192 if (!data->is_rmii) {
193 at91_set_B_periph(AT91_PIN_PA28, 0); /* ECRS */
194 at91_set_B_periph(AT91_PIN_PA29, 0); /* ECOL */
195 at91_set_B_periph(AT91_PIN_PA25, 0); /* ERX2 */
196 at91_set_B_periph(AT91_PIN_PA26, 0); /* ERX3 */
197 at91_set_B_periph(AT91_PIN_PA27, 0); /* ERXCK */
198 at91_set_B_periph(AT91_PIN_PA23, 0); /* ETX2 */
199 at91_set_B_periph(AT91_PIN_PA24, 0); /* ETX3 */
200 at91_set_B_periph(AT91_PIN_PA22, 0); /* ETXER */
201 }
202
203 eth_data = *data;
204 platform_device_register(&at91sam9260_eth_device);
205}
206#else
84e0cdb0 207void __init at91_add_device_eth(struct macb_platform_data *data) {}
86ad76bb
AV		 208#endif
209
210
211/* --------------------------------------------------------------------
212 * MMC / SD
213 * -------------------------------------------------------------------- */
214
215#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
c6686ff9 216static u64 mmc_dmamask = DMA_BIT_MASK(32);
86ad76bb
AV		 217static struct at91_mmc_data mmc_data;
218
219static struct resource mmc_resources[] = {
220 [0] = {
221 .start = AT91SAM9260_BASE_MCI,
222 .end = AT91SAM9260_BASE_MCI + SZ_16K - 1,
223 .flags = IORESOURCE_MEM,
224 },
225 [1] = {
8fe82a55
LD		 226 .start = NR_IRQS_LEGACY + AT91SAM9260_ID_MCI,
227 .end = NR_IRQS_LEGACY + AT91SAM9260_ID_MCI,
86ad76bb
AV		 228 .flags = IORESOURCE_IRQ,
229 },
230};
231
232static struct platform_device at91sam9260_mmc_device = {
233 .name = "at91_mci",
234 .id = -1,
235 .dev = {
236 .dma_mask = &mmc_dmamask,
c6686ff9 237 .coherent_dma_mask = DMA_BIT_MASK(32),
86ad76bb
AV		 238 .platform_data = &mmc_data,
239 },
240 .resource = mmc_resources,
241 .num_resources = ARRAY_SIZE(mmc_resources),
242};
243
d0760b3b 244void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
86ad76bb
AV		 245{
246 if (!data)
247 return;
248
249 /* input/irq */
cc9f9aef 250 if (gpio_is_valid(data->det_pin)) {
86ad76bb
AV		 251 at91_set_gpio_input(data->det_pin, 1);
252 at91_set_deglitch(data->det_pin, 1);
253 }
cc9f9aef 254 if (gpio_is_valid(data->wp_pin))
86ad76bb 255 at91_set_gpio_input(data->wp_pin, 1);
cc9f9aef 256 if (gpio_is_valid(data->vcc_pin))
86ad76bb
AV		 257 at91_set_gpio_output(data->vcc_pin, 0);
258
259 /* CLK */
260 at91_set_A_periph(AT91_PIN_PA8, 0);
261
262 if (data->slot_b) {
263 /* CMD */
264 at91_set_B_periph(AT91_PIN_PA1, 1);
265
266 /* DAT0, maybe DAT1..DAT3 */
267 at91_set_B_periph(AT91_PIN_PA0, 1);
268 if (data->wire4) {
269 at91_set_B_periph(AT91_PIN_PA5, 1);
270 at91_set_B_periph(AT91_PIN_PA4, 1);
271 at91_set_B_periph(AT91_PIN_PA3, 1);
272 }
273 } else {
274 /* CMD */
275 at91_set_A_periph(AT91_PIN_PA7, 1);
276
277 /* DAT0, maybe DAT1..DAT3 */
278 at91_set_A_periph(AT91_PIN_PA6, 1);
279 if (data->wire4) {
280 at91_set_A_periph(AT91_PIN_PA9, 1);
281 at91_set_A_periph(AT91_PIN_PA10, 1);
282 at91_set_A_periph(AT91_PIN_PA11, 1);
283 }
284 }
285
286 mmc_data = *data;
287 platform_device_register(&at91sam9260_mmc_device);
288}
289#else
d0760b3b 290void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
86ad76bb
AV		 291#endif
292
864f38eb
RE		 293/* --------------------------------------------------------------------
294 * MMC / SD Slot for Atmel MCI Driver
295 * -------------------------------------------------------------------- */
296
297#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE)
298static u64 mmc_dmamask = DMA_BIT_MASK(32);
299static struct mci_platform_data mmc_data;
300
301static struct resource mmc_resources[] = {
302 [0] = {
303 .start = AT91SAM9260_BASE_MCI,
304 .end = AT91SAM9260_BASE_MCI + SZ_16K - 1,
305 .flags = IORESOURCE_MEM,
306 },
307 [1] = {
8fe82a55
LD		 308 .start = NR_IRQS_LEGACY + AT91SAM9260_ID_MCI,
309 .end = NR_IRQS_LEGACY + AT91SAM9260_ID_MCI,
864f38eb
RE		 310 .flags = IORESOURCE_IRQ,
311 },
312};
313
314static struct platform_device at91sam9260_mmc_device = {
315 .name = "atmel_mci",
316 .id = -1,
317 .dev = {
318 .dma_mask = &mmc_dmamask,
319 .coherent_dma_mask = DMA_BIT_MASK(32),
320 .platform_data = &mmc_data,
321 },
322 .resource = mmc_resources,
323 .num_resources = ARRAY_SIZE(mmc_resources),
324};
325
326void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data)
327{
328 unsigned int i;
329 unsigned int slot_count = 0;
330
331 if (!data)
332 return;
333
2c96a293 334 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
864f38eb
RE		 335 if (data->slot[i].bus_width) {
336 /* input/irq */
cc9f9aef 337 if (gpio_is_valid(data->slot[i].detect_pin)) {
864f38eb
RE		 338 at91_set_gpio_input(data->slot[i].detect_pin, 1);
339 at91_set_deglitch(data->slot[i].detect_pin, 1);
340 }
cc9f9aef 341 if (gpio_is_valid(data->slot[i].wp_pin))
864f38eb
RE		 342 at91_set_gpio_input(data->slot[i].wp_pin, 1);
343
344 switch (i) {
345 case 0:
346 /* CMD */
347 at91_set_A_periph(AT91_PIN_PA7, 1);
348 /* DAT0, maybe DAT1..DAT3 */
349 at91_set_A_periph(AT91_PIN_PA6, 1);
350 if (data->slot[i].bus_width == 4) {
351 at91_set_A_periph(AT91_PIN_PA9, 1);
352 at91_set_A_periph(AT91_PIN_PA10, 1);
353 at91_set_A_periph(AT91_PIN_PA11, 1);
354 }
355 slot_count++;
356 break;
357 case 1:
358 /* CMD */
359 at91_set_B_periph(AT91_PIN_PA1, 1);
360 /* DAT0, maybe DAT1..DAT3 */
361 at91_set_B_periph(AT91_PIN_PA0, 1);
362 if (data->slot[i].bus_width == 4) {
363 at91_set_B_periph(AT91_PIN_PA5, 1);
364 at91_set_B_periph(AT91_PIN_PA4, 1);
365 at91_set_B_periph(AT91_PIN_PA3, 1);
366 }
367 slot_count++;
368 break;
369 default:
370 printk(KERN_ERR
371 "AT91: SD/MMC slot %d not available\n", i);
372 break;
373 }
374 }
375 }
376
377 if (slot_count) {
378 /* CLK */
379 at91_set_A_periph(AT91_PIN_PA8, 0);
380
381 mmc_data = *data;
382 platform_device_register(&at91sam9260_mmc_device);
383 }
384}
385#else
386void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data) {}
387#endif
388
86ad76bb
AV		 389
390/* --------------------------------------------------------------------
391 * NAND / SmartMedia
392 * -------------------------------------------------------------------- */
393
f6ed6f78 394#if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
3c3796cc 395static struct atmel_nand_data nand_data;
86ad76bb
AV		 396
397#define NAND_BASE AT91_CHIPSELECT_3
398
399static struct resource nand_resources[] = {
d7a2415f 400 [0] = {
86ad76bb 401 .start = NAND_BASE,
22823558 402 .end = NAND_BASE + SZ_256M - 1,
86ad76bb 403 .flags = IORESOURCE_MEM,
d7a2415f
AV		 404 },
405 [1] = {
d28edd1b
JCPV		 406 .start = AT91SAM9260_BASE_ECC,
407 .end = AT91SAM9260_BASE_ECC + SZ_512 - 1,
d7a2415f 408 .flags = IORESOURCE_MEM,
86ad76bb
AV		 409 }
410};
411
412static struct platform_device at91sam9260_nand_device = {
3c3796cc 413 .name = "atmel_nand",
86ad76bb
AV		 414 .id = -1,
415 .dev = {
416 .platform_data = &nand_data,
417 },
418 .resource = nand_resources,
419 .num_resources = ARRAY_SIZE(nand_resources),
420};
421
3c3796cc 422void __init at91_add_device_nand(struct atmel_nand_data *data)
86ad76bb 423{
461d3b4d 424 unsigned long csa;
86ad76bb
AV		 425
426 if (!data)
427 return;
428
4342d647
JCPV		 429 csa = at91_matrix_read(AT91_MATRIX_EBICSA);
430 at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
86ad76bb 431
86ad76bb 432 /* enable pin */
cc9f9aef 433 if (gpio_is_valid(data->enable_pin))
86ad76bb
AV		 434 at91_set_gpio_output(data->enable_pin, 1);
435
436 /* ready/busy pin */
cc9f9aef 437 if (gpio_is_valid(data->rdy_pin))
86ad76bb
AV		 438 at91_set_gpio_input(data->rdy_pin, 1);
439
440 /* card detect pin */
cc9f9aef 441 if (gpio_is_valid(data->det_pin))
86ad76bb
AV		 442 at91_set_gpio_input(data->det_pin, 1);
443
444 nand_data = *data;
445 platform_device_register(&at91sam9260_nand_device);
446}
447#else
3c3796cc 448void __init at91_add_device_nand(struct atmel_nand_data *data) {}
86ad76bb
AV		 449#endif
450
451
452/* --------------------------------------------------------------------
453 * TWI (i2c)
454 * -------------------------------------------------------------------- */
455
f230d3f5
AV		 456/*
457 * Prefer the GPIO code since the TWI controller isn't robust
458 * (gets overruns and underruns under load) and can only issue
459 * repeated STARTs in one scenario (the driver doesn't yet handle them).
460 */
461
462#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
463
464static struct i2c_gpio_platform_data pdata = {
465 .sda_pin = AT91_PIN_PA23,
466 .sda_is_open_drain = 1,
467 .scl_pin = AT91_PIN_PA24,
468 .scl_is_open_drain = 1,
469 .udelay = 2, /* ~100 kHz */
470};
471
472static struct platform_device at91sam9260_twi_device = {
473 .name = "i2c-gpio",
474 .id = -1,
475 .dev.platform_data = &pdata,
476};
477
478void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
479{
480 at91_set_GPIO_periph(AT91_PIN_PA23, 1); /* TWD (SDA) */
481 at91_set_multi_drive(AT91_PIN_PA23, 1);
482
483 at91_set_GPIO_periph(AT91_PIN_PA24, 1); /* TWCK (SCL) */
484 at91_set_multi_drive(AT91_PIN_PA24, 1);
485
486 i2c_register_board_info(0, devices, nr_devices);
487 platform_device_register(&at91sam9260_twi_device);
488}
489
490#elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
86ad76bb
AV		 491
492static struct resource twi_resources[] = {
493 [0] = {
494 .start = AT91SAM9260_BASE_TWI,
495 .end = AT91SAM9260_BASE_TWI + SZ_16K - 1,
496 .flags = IORESOURCE_MEM,
497 },
498 [1] = {
8fe82a55
LD		 499 .start = NR_IRQS_LEGACY + AT91SAM9260_ID_TWI,
500 .end = NR_IRQS_LEGACY + AT91SAM9260_ID_TWI,
86ad76bb
AV		 501 .flags = IORESOURCE_IRQ,
502 },
503};
504
505static struct platform_device at91sam9260_twi_device = {
506 .name = "at91_i2c",
507 .id = -1,
508 .resource = twi_resources,
509 .num_resources = ARRAY_SIZE(twi_resources),
510};
511
f230d3f5 512void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
86ad76bb
AV		 513{
514 /* pins used for TWI interface */
515 at91_set_A_periph(AT91_PIN_PA23, 0); /* TWD */
516 at91_set_multi_drive(AT91_PIN_PA23, 1);
517
518 at91_set_A_periph(AT91_PIN_PA24, 0); /* TWCK */
519 at91_set_multi_drive(AT91_PIN_PA24, 1);
520
f230d3f5 521 i2c_register_board_info(0, devices, nr_devices);
86ad76bb
AV		 522 platform_device_register(&at91sam9260_twi_device);
523}
524#else
f230d3f5 525void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
86ad76bb
AV		 526#endif
527
528
529/* --------------------------------------------------------------------
530 * SPI
531 * -------------------------------------------------------------------- */
532
533#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
c6686ff9 534static u64 spi_dmamask = DMA_BIT_MASK(32);
86ad76bb
AV		 535
536static struct resource spi0_resources[] = {
537 [0] = {
538 .start = AT91SAM9260_BASE_SPI0,
539 .end = AT91SAM9260_BASE_SPI0 + SZ_16K - 1,
540 .flags = IORESOURCE_MEM,
541 },
542 [1] = {
8fe82a55
LD		 543 .start = NR_IRQS_LEGACY + AT91SAM9260_ID_SPI0,
544 .end = NR_IRQS_LEGACY + AT91SAM9260_ID_SPI0,
86ad76bb
AV		 545 .flags = IORESOURCE_IRQ,
546 },
547};
548
549static struct platform_device at91sam9260_spi0_device = {
550 .name = "atmel_spi",
551 .id = 0,
552 .dev = {
553 .dma_mask = &spi_dmamask,
c6686ff9 554 .coherent_dma_mask = DMA_BIT_MASK(32),
86ad76bb
AV		 555 },
556 .resource = spi0_resources,
557 .num_resources = ARRAY_SIZE(spi0_resources),
558};
559
560static const unsigned spi0_standard_cs[4] = { AT91_PIN_PA3, AT91_PIN_PC11, AT91_PIN_PC16, AT91_PIN_PC17 };
561
562static struct resource spi1_resources[] = {
563 [0] = {
564 .start = AT91SAM9260_BASE_SPI1,
565 .end = AT91SAM9260_BASE_SPI1 + SZ_16K - 1,
566 .flags = IORESOURCE_MEM,
567 },
568 [1] = {
8fe82a55
LD		 569 .start = NR_IRQS_LEGACY + AT91SAM9260_ID_SPI1,
570 .end = NR_IRQS_LEGACY + AT91SAM9260_ID_SPI1,
86ad76bb
AV		 571 .flags = IORESOURCE_IRQ,
572 },
573};
574
575static struct platform_device at91sam9260_spi1_device = {
576 .name = "atmel_spi",
577 .id = 1,
578 .dev = {
579 .dma_mask = &spi_dmamask,
c6686ff9 580 .coherent_dma_mask = DMA_BIT_MASK(32),
86ad76bb
AV		 581 },
582 .resource = spi1_resources,
583 .num_resources = ARRAY_SIZE(spi1_resources),
584};
585
586static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB3, AT91_PIN_PC5, AT91_PIN_PC4, AT91_PIN_PC3 };
587
588void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
589{
590 int i;
591 unsigned long cs_pin;
592 short enable_spi0 = 0;
593 short enable_spi1 = 0;
594
595 /* Choose SPI chip-selects */
596 for (i = 0; i < nr_devices; i++) {
597 if (devices[i].controller_data)
598 cs_pin = (unsigned long) devices[i].controller_data;
599 else if (devices[i].bus_num == 0)
600 cs_pin = spi0_standard_cs[devices[i].chip_select];
601 else
602 cs_pin = spi1_standard_cs[devices[i].chip_select];
603
0c2c1f62
NF		 604 if (!gpio_is_valid(cs_pin))
605 continue;
606
86ad76bb
AV		 607 if (devices[i].bus_num == 0)
608 enable_spi0 = 1;
609 else
610 enable_spi1 = 1;
611
612 /* enable chip-select pin */
613 at91_set_gpio_output(cs_pin, 1);
614
615 /* pass chip-select pin to driver */
616 devices[i].controller_data = (void *) cs_pin;
617 }
618
619 spi_register_board_info(devices, nr_devices);
620
621 /* Configure SPI bus(es) */
622 if (enable_spi0) {
623 at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
624 at91_set_A_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
625 at91_set_A_periph(AT91_PIN_PA2, 0); /* SPI1_SPCK */
626
86ad76bb
AV		 627 platform_device_register(&at91sam9260_spi0_device);
628 }
629 if (enable_spi1) {
630 at91_set_A_periph(AT91_PIN_PB0, 0); /* SPI1_MISO */
631 at91_set_A_periph(AT91_PIN_PB1, 0); /* SPI1_MOSI */
632 at91_set_A_periph(AT91_PIN_PB2, 0); /* SPI1_SPCK */
633
86ad76bb
AV		 634 platform_device_register(&at91sam9260_spi1_device);
635 }
636}
637#else
638void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
639#endif
640
641
e5f40bfa
AV		 642/* --------------------------------------------------------------------
643 * Timer/Counter blocks
644 * -------------------------------------------------------------------- */
645
646#ifdef CONFIG_ATMEL_TCLIB
647
648static struct resource tcb0_resources[] = {
649 [0] = {
650 .start = AT91SAM9260_BASE_TCB0,
29831297 651 .end = AT91SAM9260_BASE_TCB0 + SZ_256 - 1,
e5f40bfa
AV		 652 .flags = IORESOURCE_MEM,
653 },
654 [1] = {
8fe82a55
LD		 655 .start = NR_IRQS_LEGACY + AT91SAM9260_ID_TC0,
656 .end = NR_IRQS_LEGACY + AT91SAM9260_ID_TC0,
e5f40bfa
AV		 657 .flags = IORESOURCE_IRQ,
658 },
659 [2] = {
8fe82a55
LD		 660 .start = NR_IRQS_LEGACY + AT91SAM9260_ID_TC1,
661 .end = NR_IRQS_LEGACY + AT91SAM9260_ID_TC1,
e5f40bfa
AV		 662 .flags = IORESOURCE_IRQ,
663 },
664 [3] = {
8fe82a55
LD		 665 .start = NR_IRQS_LEGACY + AT91SAM9260_ID_TC2,
666 .end = NR_IRQS_LEGACY + AT91SAM9260_ID_TC2,
e5f40bfa
AV		 667 .flags = IORESOURCE_IRQ,
668 },
669};
670
671static struct platform_device at91sam9260_tcb0_device = {
672 .name = "atmel_tcb",
673 .id = 0,
674 .resource = tcb0_resources,
675 .num_resources = ARRAY_SIZE(tcb0_resources),
676};
677
678static struct resource tcb1_resources[] = {
679 [0] = {
680 .start = AT91SAM9260_BASE_TCB1,
29831297 681 .end = AT91SAM9260_BASE_TCB1 + SZ_256 - 1,
e5f40bfa
AV		 682 .flags = IORESOURCE_MEM,
683 },
684 [1] = {
8fe82a55
LD		 685 .start = NR_IRQS_LEGACY + AT91SAM9260_ID_TC3,
686 .end = NR_IRQS_LEGACY + AT91SAM9260_ID_TC3,
e5f40bfa
AV		 687 .flags = IORESOURCE_IRQ,
688 },
689 [2] = {
8fe82a55
LD		 690 .start = NR_IRQS_LEGACY + AT91SAM9260_ID_TC4,
691 .end = NR_IRQS_LEGACY + AT91SAM9260_ID_TC4,
e5f40bfa
AV		 692 .flags = IORESOURCE_IRQ,
693 },
694 [3] = {
8fe82a55
LD		 695 .start = NR_IRQS_LEGACY + AT91SAM9260_ID_TC5,
696 .end = NR_IRQS_LEGACY + AT91SAM9260_ID_TC5,
e5f40bfa
AV		 697 .flags = IORESOURCE_IRQ,
698 },
699};
700
701static struct platform_device at91sam9260_tcb1_device = {
702 .name = "atmel_tcb",
703 .id = 1,
704 .resource = tcb1_resources,
705 .num_resources = ARRAY_SIZE(tcb1_resources),
706};
707
708static void __init at91_add_device_tc(void)
709{
e5f40bfa 710 platform_device_register(&at91sam9260_tcb0_device);
e5f40bfa
AV		 711 platform_device_register(&at91sam9260_tcb1_device);
712}
713#else
714static void __init at91_add_device_tc(void) { }
715#endif
716
717
884f5a6a
AV		 718/* --------------------------------------------------------------------
719 * RTT
720 * -------------------------------------------------------------------- */
721
722static struct resource rtt_resources[] = {
723 {
eab5fd67
JCPV		 724 .start = AT91SAM9260_BASE_RTT,
725 .end = AT91SAM9260_BASE_RTT + SZ_16 - 1,
884f5a6a 726 .flags = IORESOURCE_MEM,
b3af8b49
JCPV		 727 }, {
728 .flags = IORESOURCE_MEM,
729 },
884f5a6a
AV		 730};
731
732static struct platform_device at91sam9260_rtt_device = {
733 .name = "at91_rtt",
4fd9212c 734 .id = 0,
884f5a6a 735 .resource = rtt_resources,
884f5a6a
AV		 736};
737
205056a3
JCPV		 738
739#if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
740static void __init at91_add_device_rtt_rtc(void)
741{
742 at91sam9260_rtt_device.name = "rtc-at91sam9";
b3af8b49
JCPV		 743 /*
744 * The second resource is needed:
745 * GPBR will serve as the storage for RTC time offset
746 */
747 at91sam9260_rtt_device.num_resources = 2;
748 rtt_resources[1].start = AT91SAM9260_BASE_GPBR +
749 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
750 rtt_resources[1].end = rtt_resources[1].start + 3;
205056a3
JCPV		 751}
752#else
b3af8b49
JCPV		 753static void __init at91_add_device_rtt_rtc(void)
754{
755 /* Only one resource is needed: RTT not used as RTC */
756 at91sam9260_rtt_device.num_resources = 1;
757}
205056a3
JCPV		 758#endif
759
884f5a6a
AV		 760static void __init at91_add_device_rtt(void)
761{
205056a3 762 at91_add_device_rtt_rtc();
884f5a6a
AV		 763 platform_device_register(&at91sam9260_rtt_device);
764}
765
766
767/* --------------------------------------------------------------------
768 * Watchdog
769 * -------------------------------------------------------------------- */
770
2af29b78 771#if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
c1c30a29
JCPV		 772static struct resource wdt_resources[] = {
773 {
774 .start = AT91SAM9260_BASE_WDT,
775 .end = AT91SAM9260_BASE_WDT + SZ_16 - 1,
776 .flags = IORESOURCE_MEM,
777 }
778};
779
884f5a6a
AV		 780static struct platform_device at91sam9260_wdt_device = {
781 .name = "at91_wdt",
782 .id = -1,
c1c30a29
JCPV		 783 .resource = wdt_resources,
784 .num_resources = ARRAY_SIZE(wdt_resources),
884f5a6a
AV		 785};
786
787static void __init at91_add_device_watchdog(void)
788{
789 platform_device_register(&at91sam9260_wdt_device);
790}
791#else
792static void __init at91_add_device_watchdog(void) {}
793#endif
794
795
bfbc3266
AV		 796/* --------------------------------------------------------------------
797 * SSC -- Synchronous Serial Controller
798 * -------------------------------------------------------------------- */
799
800#if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
801static u64 ssc_dmamask = DMA_BIT_MASK(32);
802
803static struct resource ssc_resources[] = {
804 [0] = {
805 .start = AT91SAM9260_BASE_SSC,
806 .end = AT91SAM9260_BASE_SSC + SZ_16K - 1,
807 .flags = IORESOURCE_MEM,
808 },
809 [1] = {
8fe82a55
LD		 810 .start = NR_IRQS_LEGACY + AT91SAM9260_ID_SSC,
811 .end = NR_IRQS_LEGACY + AT91SAM9260_ID_SSC,
bfbc3266
AV		 812 .flags = IORESOURCE_IRQ,
813 },
814};
815
816static struct platform_device at91sam9260_ssc_device = {
817 .name = "ssc",
818 .id = 0,
819 .dev = {
820 .dma_mask = &ssc_dmamask,
821 .coherent_dma_mask = DMA_BIT_MASK(32),
822 },
823 .resource = ssc_resources,
824 .num_resources = ARRAY_SIZE(ssc_resources),
825};
826
827static inline void configure_ssc_pins(unsigned pins)
828{
829 if (pins & ATMEL_SSC_TF)
830 at91_set_A_periph(AT91_PIN_PB17, 1);
831 if (pins & ATMEL_SSC_TK)
832 at91_set_A_periph(AT91_PIN_PB16, 1);
833 if (pins & ATMEL_SSC_TD)
834 at91_set_A_periph(AT91_PIN_PB18, 1);
835 if (pins & ATMEL_SSC_RD)
836 at91_set_A_periph(AT91_PIN_PB19, 1);
837 if (pins & ATMEL_SSC_RK)
838 at91_set_A_periph(AT91_PIN_PB20, 1);
839 if (pins & ATMEL_SSC_RF)
840 at91_set_A_periph(AT91_PIN_PB21, 1);
841}
842
843/*
844 * SSC controllers are accessed through library code, instead of any
845 * kind of all-singing/all-dancing driver. For example one could be
846 * used by a particular I2S audio codec's driver, while another one
847 * on the same system might be used by a custom data capture driver.
848 */
849void __init at91_add_device_ssc(unsigned id, unsigned pins)
850{
851 struct platform_device *pdev;
852
853 /*
854 * NOTE: caller is responsible for passing information matching
855 * "pins" to whatever will be using each particular controller.
856 */
857 switch (id) {
858 case AT91SAM9260_ID_SSC:
859 pdev = &at91sam9260_ssc_device;
860 configure_ssc_pins(pins);
bfbc3266
AV		 861 break;
862 default:
863 return;
864 }
865
866 platform_device_register(pdev);
867}
868
869#else
870void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
871#endif
872
873
86ad76bb
AV		 874/* --------------------------------------------------------------------
875 * UART
876 * -------------------------------------------------------------------- */
877#if defined(CONFIG_SERIAL_ATMEL)
878static struct resource dbgu_resources[] = {
879 [0] = {
13079a73
JCPV		 880 .start = AT91SAM9260_BASE_DBGU,
881 .end = AT91SAM9260_BASE_DBGU + SZ_512 - 1,
86ad76bb
AV		 882 .flags = IORESOURCE_MEM,
883 },
884 [1] = {
8fe82a55
LD		 885 .start = NR_IRQS_LEGACY + AT91_ID_SYS,
886 .end = NR_IRQS_LEGACY + AT91_ID_SYS,
86ad76bb
AV		 887 .flags = IORESOURCE_IRQ,
888 },
889};
890
891static struct atmel_uart_data dbgu_data = {
892 .use_dma_tx = 0,
893 .use_dma_rx = 0, /* DBGU not capable of receive DMA */
86ad76bb
AV		 894};
895
c6686ff9
AV		 896static u64 dbgu_dmamask = DMA_BIT_MASK(32);
897
86ad76bb
AV		 898static struct platform_device at91sam9260_dbgu_device = {
899 .name = "atmel_usart",
900 .id = 0,
901 .dev = {
c6686ff9
AV		 902 .dma_mask = &dbgu_dmamask,
903 .coherent_dma_mask = DMA_BIT_MASK(32),
904 .platform_data = &dbgu_data,
86ad76bb
AV		 905 },
906 .resource = dbgu_resources,
907 .num_resources = ARRAY_SIZE(dbgu_resources),
908};
909
910static inline void configure_dbgu_pins(void)
911{
912 at91_set_A_periph(AT91_PIN_PB14, 0); /* DRXD */
913 at91_set_A_periph(AT91_PIN_PB15, 1); /* DTXD */
914}
915
916static struct resource uart0_resources[] = {
917 [0] = {
918 .start = AT91SAM9260_BASE_US0,
919 .end = AT91SAM9260_BASE_US0 + SZ_16K - 1,
920 .flags = IORESOURCE_MEM,
921 },
922 [1] = {
8fe82a55
LD		 923 .start = NR_IRQS_LEGACY + AT91SAM9260_ID_US0,
924 .end = NR_IRQS_LEGACY + AT91SAM9260_ID_US0,
86ad76bb
AV		 925 .flags = IORESOURCE_IRQ,
926 },
927};
928
929static struct atmel_uart_data uart0_data = {
930 .use_dma_tx = 1,
931 .use_dma_rx = 1,
932};
933
c6686ff9
AV		 934static u64 uart0_dmamask = DMA_BIT_MASK(32);
935
86ad76bb
AV		 936static struct platform_device at91sam9260_uart0_device = {
937 .name = "atmel_usart",
938 .id = 1,
939 .dev = {
c6686ff9
AV		 940 .dma_mask = &uart0_dmamask,
941 .coherent_dma_mask = DMA_BIT_MASK(32),
942 .platform_data = &uart0_data,
86ad76bb
AV		 943 },
944 .resource = uart0_resources,
945 .num_resources = ARRAY_SIZE(uart0_resources),
946};
947
c8f385a6 948static inline void configure_usart0_pins(unsigned pins)
86ad76bb
AV		 949{
950 at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD0 */
951 at91_set_A_periph(AT91_PIN_PB5, 0); /* RXD0 */
c8f385a6
AV		 952
953 if (pins & ATMEL_UART_RTS)
954 at91_set_A_periph(AT91_PIN_PB26, 0); /* RTS0 */
955 if (pins & ATMEL_UART_CTS)
956 at91_set_A_periph(AT91_PIN_PB27, 0); /* CTS0 */
957 if (pins & ATMEL_UART_DTR)
958 at91_set_A_periph(AT91_PIN_PB24, 0); /* DTR0 */
959 if (pins & ATMEL_UART_DSR)
960 at91_set_A_periph(AT91_PIN_PB22, 0); /* DSR0 */
961 if (pins & ATMEL_UART_DCD)
962 at91_set_A_periph(AT91_PIN_PB23, 0); /* DCD0 */
963 if (pins & ATMEL_UART_RI)
964 at91_set_A_periph(AT91_PIN_PB25, 0); /* RI0 */
86ad76bb
AV		 965}
966
967static struct resource uart1_resources[] = {
968 [0] = {
969 .start = AT91SAM9260_BASE_US1,
970 .end = AT91SAM9260_BASE_US1 + SZ_16K - 1,
971 .flags = IORESOURCE_MEM,
972 },
973 [1] = {
8fe82a55
LD		 974 .start = NR_IRQS_LEGACY + AT91SAM9260_ID_US1,
975 .end = NR_IRQS_LEGACY + AT91SAM9260_ID_US1,
86ad76bb
AV		 976 .flags = IORESOURCE_IRQ,
977 },
978};
979
980static struct atmel_uart_data uart1_data = {
981 .use_dma_tx = 1,
982 .use_dma_rx = 1,
983};
984
c6686ff9
AV		 985static u64 uart1_dmamask = DMA_BIT_MASK(32);
986
86ad76bb
AV		 987static struct platform_device at91sam9260_uart1_device = {
988 .name = "atmel_usart",
989 .id = 2,
990 .dev = {
c6686ff9
AV		 991 .dma_mask = &uart1_dmamask,
992 .coherent_dma_mask = DMA_BIT_MASK(32),
993 .platform_data = &uart1_data,
86ad76bb
AV		 994 },
995 .resource = uart1_resources,
996 .num_resources = ARRAY_SIZE(uart1_resources),
997};
998
c8f385a6 999static inline void configure_usart1_pins(unsigned pins)
86ad76bb
AV		 1000{
1001 at91_set_A_periph(AT91_PIN_PB6, 1); /* TXD1 */
1002 at91_set_A_periph(AT91_PIN_PB7, 0); /* RXD1 */
c8f385a6
AV		 1003
1004 if (pins & ATMEL_UART_RTS)
1005 at91_set_A_periph(AT91_PIN_PB28, 0); /* RTS1 */
1006 if (pins & ATMEL_UART_CTS)
1007 at91_set_A_periph(AT91_PIN_PB29, 0); /* CTS1 */
86ad76bb
AV		 1008}
1009
1010static struct resource uart2_resources[] = {
1011 [0] = {
1012 .start = AT91SAM9260_BASE_US2,
1013 .end = AT91SAM9260_BASE_US2 + SZ_16K - 1,
1014 .flags = IORESOURCE_MEM,
1015 },
1016 [1] = {
8fe82a55
LD		 1017 .start = NR_IRQS_LEGACY + AT91SAM9260_ID_US2,
1018 .end = NR_IRQS_LEGACY + AT91SAM9260_ID_US2,
86ad76bb
AV		 1019 .flags = IORESOURCE_IRQ,
1020 },
1021};
1022
1023static struct atmel_uart_data uart2_data = {
1024 .use_dma_tx = 1,
1025 .use_dma_rx = 1,
1026};
1027
c6686ff9
AV		 1028static u64 uart2_dmamask = DMA_BIT_MASK(32);
1029
86ad76bb
AV		 1030static struct platform_device at91sam9260_uart2_device = {
1031 .name = "atmel_usart",
1032 .id = 3,
1033 .dev = {
c6686ff9
AV		 1034 .dma_mask = &uart2_dmamask,
1035 .coherent_dma_mask = DMA_BIT_MASK(32),
1036 .platform_data = &uart2_data,
86ad76bb
AV		 1037 },
1038 .resource = uart2_resources,
1039 .num_resources = ARRAY_SIZE(uart2_resources),
1040};
1041
c8f385a6 1042static inline void configure_usart2_pins(unsigned pins)
86ad76bb
AV		 1043{
1044 at91_set_A_periph(AT91_PIN_PB8, 1); /* TXD2 */
1045 at91_set_A_periph(AT91_PIN_PB9, 0); /* RXD2 */
c8f385a6
AV		 1046
1047 if (pins & ATMEL_UART_RTS)
1048 at91_set_A_periph(AT91_PIN_PA4, 0); /* RTS2 */
1049 if (pins & ATMEL_UART_CTS)
1050 at91_set_A_periph(AT91_PIN_PA5, 0); /* CTS2 */
86ad76bb
AV		 1051}
1052
1053static struct resource uart3_resources[] = {
1054 [0] = {
1055 .start = AT91SAM9260_BASE_US3,
1056 .end = AT91SAM9260_BASE_US3 + SZ_16K - 1,
1057 .flags = IORESOURCE_MEM,
1058 },
1059 [1] = {
8fe82a55
LD		 1060 .start = NR_IRQS_LEGACY + AT91SAM9260_ID_US3,
1061 .end = NR_IRQS_LEGACY + AT91SAM9260_ID_US3,
86ad76bb
AV		 1062 .flags = IORESOURCE_IRQ,
1063 },
1064};
1065
1066static struct atmel_uart_data uart3_data = {
1067 .use_dma_tx = 1,
1068 .use_dma_rx = 1,
1069};
1070
c6686ff9
AV		 1071static u64 uart3_dmamask = DMA_BIT_MASK(32);
1072
86ad76bb
AV		 1073static struct platform_device at91sam9260_uart3_device = {
1074 .name = "atmel_usart",
1075 .id = 4,
1076 .dev = {
c6686ff9
AV		 1077 .dma_mask = &uart3_dmamask,
1078 .coherent_dma_mask = DMA_BIT_MASK(32),
1079 .platform_data = &uart3_data,
86ad76bb
AV		 1080 },
1081 .resource = uart3_resources,
1082 .num_resources = ARRAY_SIZE(uart3_resources),
1083};
1084
c8f385a6 1085static inline void configure_usart3_pins(unsigned pins)
86ad76bb
AV		 1086{
1087 at91_set_A_periph(AT91_PIN_PB10, 1); /* TXD3 */
1088 at91_set_A_periph(AT91_PIN_PB11, 0); /* RXD3 */
c8f385a6
AV		 1089
1090 if (pins & ATMEL_UART_RTS)
1091 at91_set_B_periph(AT91_PIN_PC8, 0); /* RTS3 */
1092 if (pins & ATMEL_UART_CTS)
1093 at91_set_B_periph(AT91_PIN_PC10, 0); /* CTS3 */
86ad76bb
AV		 1094}
1095
1096static struct resource uart4_resources[] = {
1097 [0] = {
1098 .start = AT91SAM9260_BASE_US4,
1099 .end = AT91SAM9260_BASE_US4 + SZ_16K - 1,
1100 .flags = IORESOURCE_MEM,
1101 },
1102 [1] = {
8fe82a55
LD		 1103 .start = NR_IRQS_LEGACY + AT91SAM9260_ID_US4,
1104 .end = NR_IRQS_LEGACY + AT91SAM9260_ID_US4,
86ad76bb
AV		 1105 .flags = IORESOURCE_IRQ,
1106 },
1107};
1108
1109static struct atmel_uart_data uart4_data = {
1110 .use_dma_tx = 1,
1111 .use_dma_rx = 1,
1112};
1113
c6686ff9
AV		 1114static u64 uart4_dmamask = DMA_BIT_MASK(32);
1115
86ad76bb
AV		 1116static struct platform_device at91sam9260_uart4_device = {
1117 .name = "atmel_usart",
1118 .id = 5,
1119 .dev = {
c6686ff9
AV		 1120 .dma_mask = &uart4_dmamask,
1121 .coherent_dma_mask = DMA_BIT_MASK(32),
1122 .platform_data = &uart4_data,
86ad76bb
AV		 1123 },
1124 .resource = uart4_resources,
1125 .num_resources = ARRAY_SIZE(uart4_resources),
1126};
1127
1128static inline void configure_usart4_pins(void)
1129{
1130 at91_set_B_periph(AT91_PIN_PA31, 1); /* TXD4 */
1131 at91_set_B_periph(AT91_PIN_PA30, 0); /* RXD4 */
1132}
1133
1134static struct resource uart5_resources[] = {
1135 [0] = {
1136 .start = AT91SAM9260_BASE_US5,
1137 .end = AT91SAM9260_BASE_US5 + SZ_16K - 1,
1138 .flags = IORESOURCE_MEM,
1139 },
1140 [1] = {
8fe82a55
LD		 1141 .start = NR_IRQS_LEGACY + AT91SAM9260_ID_US5,
1142 .end = NR_IRQS_LEGACY + AT91SAM9260_ID_US5,
86ad76bb
AV		 1143 .flags = IORESOURCE_IRQ,
1144 },
1145};
1146
1147static struct atmel_uart_data uart5_data = {
1148 .use_dma_tx = 1,
1149 .use_dma_rx = 1,
1150};
1151
c6686ff9
AV		 1152static u64 uart5_dmamask = DMA_BIT_MASK(32);
1153
86ad76bb
AV		 1154static struct platform_device at91sam9260_uart5_device = {
1155 .name = "atmel_usart",
1156 .id = 6,
1157 .dev = {
c6686ff9
AV		 1158 .dma_mask = &uart5_dmamask,
1159 .coherent_dma_mask = DMA_BIT_MASK(32),
1160 .platform_data = &uart5_data,
86ad76bb
AV		 1161 },
1162 .resource = uart5_resources,
1163 .num_resources = ARRAY_SIZE(uart5_resources),
1164};
1165
1166static inline void configure_usart5_pins(void)
1167{
1168 at91_set_A_periph(AT91_PIN_PB12, 1); /* TXD5 */
1169 at91_set_A_periph(AT91_PIN_PB13, 0); /* RXD5 */
1170}
1171
11aadac4 1172static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
86ad76bb 1173
c8f385a6
AV		 1174void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1175{
1176 struct platform_device *pdev;
2b348e2f 1177 struct atmel_uart_data *pdata;
c8f385a6
AV		 1178
1179 switch (id) {
1180 case 0: /* DBGU */
1181 pdev = &at91sam9260_dbgu_device;
1182 configure_dbgu_pins();
c8f385a6
AV		 1183 break;
1184 case AT91SAM9260_ID_US0:
1185 pdev = &at91sam9260_uart0_device;
1186 configure_usart0_pins(pins);
c8f385a6
AV		 1187 break;
1188 case AT91SAM9260_ID_US1:
1189 pdev = &at91sam9260_uart1_device;
1190 configure_usart1_pins(pins);
c8f385a6
AV		 1191 break;
1192 case AT91SAM9260_ID_US2:
1193 pdev = &at91sam9260_uart2_device;
1194 configure_usart2_pins(pins);
c8f385a6
AV		 1195 break;
1196 case AT91SAM9260_ID_US3:
1197 pdev = &at91sam9260_uart3_device;
1198 configure_usart3_pins(pins);
c8f385a6
AV		 1199 break;
1200 case AT91SAM9260_ID_US4:
1201 pdev = &at91sam9260_uart4_device;
1202 configure_usart4_pins();
c8f385a6
AV		 1203 break;
1204 case AT91SAM9260_ID_US5:
1205 pdev = &at91sam9260_uart5_device;
1206 configure_usart5_pins();
c8f385a6
AV		 1207 break;
1208 default:
1209 return;
1210 }
2b348e2f
JCPV		 1211 pdata = pdev->dev.platform_data;
1212 pdata->num = portnr; /* update to mapped ID */
c8f385a6
AV		 1213
1214 if (portnr < ATMEL_MAX_UART)
1215 at91_uarts[portnr] = pdev;
1216}
1217
86ad76bb
AV		 1218void __init at91_add_device_serial(void)
1219{
1220 int i;
1221
1222 for (i = 0; i < ATMEL_MAX_UART; i++) {
1223 if (at91_uarts[i])
1224 platform_device_register(at91_uarts[i]);
1225 }
1226}
1227#else
c8f385a6 1228void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
86ad76bb
AV		 1229void __init at91_add_device_serial(void) {}
1230#endif
1231
fb85205a
SM		 1232/* --------------------------------------------------------------------
1233 * CF/IDE
1234 * -------------------------------------------------------------------- */
1235
cf844751 1236#if defined(CONFIG_PATA_AT91) || defined(CONFIG_PATA_AT91_MODULE) || \
fb85205a
SM		 1237 defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE)
1238
1239static struct at91_cf_data cf0_data;
1240
1241static struct resource cf0_resources[] = {
1242 [0] = {
1243 .start = AT91_CHIPSELECT_4,
1244 .end = AT91_CHIPSELECT_4 + SZ_256M - 1,
1245 .flags = IORESOURCE_MEM,
1246 }
1247};
1248
1249static struct platform_device cf0_device = {
1250 .id = 0,
1251 .dev = {
1252 .platform_data = &cf0_data,
1253 },
1254 .resource = cf0_resources,
1255 .num_resources = ARRAY_SIZE(cf0_resources),
1256};
1257
1258static struct at91_cf_data cf1_data;
1259
1260static struct resource cf1_resources[] = {
1261 [0] = {
1262 .start = AT91_CHIPSELECT_5,
1263 .end = AT91_CHIPSELECT_5 + SZ_256M - 1,
1264 .flags = IORESOURCE_MEM,
1265 }
1266};
1267
1268static struct platform_device cf1_device = {
1269 .id = 1,
1270 .dev = {
1271 .platform_data = &cf1_data,
1272 },
1273 .resource = cf1_resources,
1274 .num_resources = ARRAY_SIZE(cf1_resources),
1275};
1276
1277void __init at91_add_device_cf(struct at91_cf_data *data)
1278{
1279 struct platform_device *pdev;
1280 unsigned long csa;
1281
1282 if (!data)
1283 return;
1284
4342d647 1285 csa = at91_matrix_read(AT91_MATRIX_EBICSA);
fb85205a
SM		 1286
1287 switch (data->chipselect) {
1288 case 4:
1289 at91_set_multi_drive(AT91_PIN_PC8, 0);
1290 at91_set_A_periph(AT91_PIN_PC8, 0);
1291 csa |= AT91_MATRIX_CS4A_SMC_CF1;
1292 cf0_data = *data;
1293 pdev = &cf0_device;
1294 break;
1295 case 5:
1296 at91_set_multi_drive(AT91_PIN_PC9, 0);
1297 at91_set_A_periph(AT91_PIN_PC9, 0);
1298 csa |= AT91_MATRIX_CS5A_SMC_CF2;
1299 cf1_data = *data;
1300 pdev = &cf1_device;
1301 break;
1302 default:
1303 printk(KERN_ERR "AT91 CF: bad chip-select requested (%u)\n",
1304 data->chipselect);
1305 return;
1306 }
1307
4342d647 1308 at91_matrix_write(AT91_MATRIX_EBICSA, csa);
fb85205a 1309
cc9f9aef 1310 if (gpio_is_valid(data->rst_pin)) {
fb85205a
SM		 1311 at91_set_multi_drive(data->rst_pin, 0);
1312 at91_set_gpio_output(data->rst_pin, 1);
1313 }
1314
cc9f9aef 1315 if (gpio_is_valid(data->irq_pin)) {
fb85205a
SM		 1316 at91_set_gpio_input(data->irq_pin, 0);
1317 at91_set_deglitch(data->irq_pin, 1);
1318 }
1319
cc9f9aef 1320 if (gpio_is_valid(data->det_pin)) {
fb85205a
SM		 1321 at91_set_gpio_input(data->det_pin, 0);
1322 at91_set_deglitch(data->det_pin, 1);
1323 }
1324
1325 at91_set_B_periph(AT91_PIN_PC6, 0); /* CFCE1 */
1326 at91_set_B_periph(AT91_PIN_PC7, 0); /* CFCE2 */
1327 at91_set_A_periph(AT91_PIN_PC10, 0); /* CFRNW */
1328 at91_set_A_periph(AT91_PIN_PC15, 1); /* NWAIT */
1329
1330 if (data->flags & AT91_CF_TRUE_IDE)
1331#if defined(CONFIG_PATA_AT91) || defined(CONFIG_PATA_AT91_MODULE)
1332 pdev->name = "pata_at91";
fb85205a 1333#else
cf844751 1334#warning "board requires AT91_CF_TRUE_IDE: enable pata_at91"
fb85205a
SM		 1335#endif
1336 else
1337 pdev->name = "at91_cf";
1338
1339 platform_device_register(pdev);
1340}
1341
1342#else
1343void __init at91_add_device_cf(struct at91_cf_data * data) {}
1344#endif
86ad76bb 1345
67b5d7b3
MR		 1346/* --------------------------------------------------------------------
1347 * ADCs
1348 * -------------------------------------------------------------------- */
1349
1350#if IS_ENABLED(CONFIG_AT91_ADC)
1351static struct at91_adc_data adc_data;
1352
1353static struct resource adc_resources[] = {
1354 [0] = {
1355 .start = AT91SAM9260_BASE_ADC,
1356 .end = AT91SAM9260_BASE_ADC + SZ_16K - 1,
1357 .flags = IORESOURCE_MEM,
1358 },
1359 [1] = {
8fe82a55
LD		 1360 .start = NR_IRQS_LEGACY + AT91SAM9260_ID_ADC,
1361 .end = NR_IRQS_LEGACY + AT91SAM9260_ID_ADC,
67b5d7b3
MR		 1362 .flags = IORESOURCE_IRQ,
1363 },
1364};
1365
1366static struct platform_device at91_adc_device = {
1367 .name = "at91_adc",
1368 .id = -1,
1369 .dev = {
1370 .platform_data = &adc_data,
1371 },
1372 .resource = adc_resources,
1373 .num_resources = ARRAY_SIZE(adc_resources),
1374};
1375
1376static struct at91_adc_trigger at91_adc_triggers[] = {
1377 [0] = {
1378 .name = "timer-counter-0",
1379 .value = AT91_ADC_TRGSEL_TC0 | AT91_ADC_TRGEN,
1380 },
1381 [1] = {
1382 .name = "timer-counter-1",
1383 .value = AT91_ADC_TRGSEL_TC1 | AT91_ADC_TRGEN,
1384 },
1385 [2] = {
1386 .name = "timer-counter-2",
1387 .value = AT91_ADC_TRGSEL_TC2 | AT91_ADC_TRGEN,
1388 },
1389 [3] = {
1390 .name = "external",
1391 .value = AT91_ADC_TRGSEL_EXTERNAL | AT91_ADC_TRGEN,
1392 .is_external = true,
1393 },
1394};
1395
1396static struct at91_adc_reg_desc at91_adc_register_g20 = {
1397 .channel_base = AT91_ADC_CHR(0),
1398 .drdy_mask = AT91_ADC_DRDY,
1399 .status_register = AT91_ADC_SR,
1400 .trigger_register = AT91_ADC_MR,
1401};
1402
1403void __init at91_add_device_adc(struct at91_adc_data *data)
1404{
1405 if (!data)
1406 return;
1407
1408 if (test_bit(0, &data->channels_used))
1409 at91_set_A_periph(AT91_PIN_PC0, 0);
1410 if (test_bit(1, &data->channels_used))
1411 at91_set_A_periph(AT91_PIN_PC1, 0);
1412 if (test_bit(2, &data->channels_used))
1413 at91_set_A_periph(AT91_PIN_PC2, 0);
1414 if (test_bit(3, &data->channels_used))
1415 at91_set_A_periph(AT91_PIN_PC3, 0);
1416
1417 if (data->use_external_triggers)
1418 at91_set_A_periph(AT91_PIN_PA22, 0);
1419
1420 data->num_channels = 4;
1421 data->startup_time = 10;
1422 data->registers = &at91_adc_register_g20;
1423 data->trigger_number = 4;
1424 data->trigger_list = at91_adc_triggers;
1425
1426 adc_data = *data;
1427 platform_device_register(&at91_adc_device);
1428}
1429#else
1430void __init at91_add_device_adc(struct at91_adc_data *data) {}
1431#endif
1432
86ad76bb
AV		 1433/* -------------------------------------------------------------------- */
1434/*
1435 * These devices are always present and don't need any board-specific
1436 * setup.
1437 */
1438static int __init at91_add_standard_devices(void)
1439{
8cf93b9c
JCPV		 1440 if (of_have_populated_dt())
1441 return 0;
1442
884f5a6a
AV		 1443 at91_add_device_rtt();
1444 at91_add_device_watchdog();
e5f40bfa 1445 at91_add_device_tc();
86ad76bb
AV		 1446 return 0;
1447}
1448
1449arch_initcall(at91_add_standard_devices);
Linux kernel - Deliverables
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