[deliverable/linux.git] / arch / arm / mach-at91 / at91sam9261.c

/*
 * arch/arm/mach-at91/at91sam9261.c
 *
 *  Copyright (C) 2005 SAN People
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 */

#include <linux/module.h>
#include <linux/pm.h>

#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <mach/at91sam9261.h>
#include <mach/at91_pmc.h>
#include <mach/at91_rstc.h>
#include <mach/at91_shdwc.h>

#include "generic.h"
#include "clock.h"

static struct map_desc at91sam9261_io_desc[] __initdata = {
	{
		.virtual	= AT91_VA_BASE_SYS,
		.pfn		= __phys_to_pfn(AT91_BASE_SYS),
		.length		= SZ_16K,
		.type		= MT_DEVICE,
	}, {
		.virtual	= AT91_IO_VIRT_BASE - AT91SAM9261_SRAM_SIZE,
		.pfn		= __phys_to_pfn(AT91SAM9261_SRAM_BASE),
		.length		= AT91SAM9261_SRAM_SIZE,
		.type		= MT_DEVICE,
	},
};

/* --------------------------------------------------------------------
 *  Clocks
 * -------------------------------------------------------------------- */

/*
 * The peripheral clocks.
 */
static struct clk pioA_clk = {
	.name		= "pioA_clk",
	.pmc_mask	= 1 << AT91SAM9261_ID_PIOA,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk pioB_clk = {
	.name		= "pioB_clk",
	.pmc_mask	= 1 << AT91SAM9261_ID_PIOB,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk pioC_clk = {
	.name		= "pioC_clk",
	.pmc_mask	= 1 << AT91SAM9261_ID_PIOC,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart0_clk = {
	.name		= "usart0_clk",
	.pmc_mask	= 1 << AT91SAM9261_ID_US0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart1_clk = {
	.name		= "usart1_clk",
	.pmc_mask	= 1 << AT91SAM9261_ID_US1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart2_clk = {
	.name		= "usart2_clk",
	.pmc_mask	= 1 << AT91SAM9261_ID_US2,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk mmc_clk = {
	.name		= "mci_clk",
	.pmc_mask	= 1 << AT91SAM9261_ID_MCI,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk udc_clk = {
	.name		= "udc_clk",
	.pmc_mask	= 1 << AT91SAM9261_ID_UDP,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk twi_clk = {
	.name		= "twi_clk",
	.pmc_mask	= 1 << AT91SAM9261_ID_TWI,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk spi0_clk = {
	.name		= "spi0_clk",
	.pmc_mask	= 1 << AT91SAM9261_ID_SPI0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk spi1_clk = {
	.name		= "spi1_clk",
	.pmc_mask	= 1 << AT91SAM9261_ID_SPI1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk ssc0_clk = {
	.name		= "ssc0_clk",
	.pmc_mask	= 1 << AT91SAM9261_ID_SSC0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk ssc1_clk = {
	.name		= "ssc1_clk",
	.pmc_mask	= 1 << AT91SAM9261_ID_SSC1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk ssc2_clk = {
	.name		= "ssc2_clk",
	.pmc_mask	= 1 << AT91SAM9261_ID_SSC2,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk tc0_clk = {
	.name		= "tc0_clk",
	.pmc_mask	= 1 << AT91SAM9261_ID_TC0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk tc1_clk = {
	.name		= "tc1_clk",
	.pmc_mask	= 1 << AT91SAM9261_ID_TC1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk tc2_clk = {
	.name		= "tc2_clk",
	.pmc_mask	= 1 << AT91SAM9261_ID_TC2,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk ohci_clk = {
	.name		= "ohci_clk",
	.pmc_mask	= 1 << AT91SAM9261_ID_UHP,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk lcdc_clk = {
	.name		= "lcdc_clk",
	.pmc_mask	= 1 << AT91SAM9261_ID_LCDC,
	.type		= CLK_TYPE_PERIPHERAL,
};

static struct clk *periph_clocks[] __initdata = {
	&pioA_clk,
	&pioB_clk,
	&pioC_clk,
	&usart0_clk,
	&usart1_clk,
	&usart2_clk,
	&mmc_clk,
	&udc_clk,
	&twi_clk,
	&spi0_clk,
	&spi1_clk,
	&ssc0_clk,
	&ssc1_clk,
	&ssc2_clk,
	&tc0_clk,
	&tc1_clk,
	&tc2_clk,
	&ohci_clk,
	&lcdc_clk,
	// irq0 .. irq2
};

/*
 * The four programmable clocks.
 * You must configure pin multiplexing to bring these signals out.
 */
static struct clk pck0 = {
	.name		= "pck0",
	.pmc_mask	= AT91_PMC_PCK0,
	.type		= CLK_TYPE_PROGRAMMABLE,
	.id		= 0,
};
static struct clk pck1 = {
	.name		= "pck1",
	.pmc_mask	= AT91_PMC_PCK1,
	.type		= CLK_TYPE_PROGRAMMABLE,
	.id		= 1,
};
static struct clk pck2 = {
	.name		= "pck2",
	.pmc_mask	= AT91_PMC_PCK2,
	.type		= CLK_TYPE_PROGRAMMABLE,
	.id		= 2,
};
static struct clk pck3 = {
	.name		= "pck3",
	.pmc_mask	= AT91_PMC_PCK3,
	.type		= CLK_TYPE_PROGRAMMABLE,
	.id		= 3,
};

/* HClocks */
static struct clk hck0 = {
	.name		= "hck0",
	.pmc_mask	= AT91_PMC_HCK0,
	.type		= CLK_TYPE_SYSTEM,
	.id		= 0,
};
static struct clk hck1 = {
	.name		= "hck1",
	.pmc_mask	= AT91_PMC_HCK1,
	.type		= CLK_TYPE_SYSTEM,
	.id		= 1,
};

static void __init at91sam9261_register_clocks(void)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
		clk_register(periph_clocks[i]);

	clk_register(&pck0);
	clk_register(&pck1);
	clk_register(&pck2);
	clk_register(&pck3);

	clk_register(&hck0);
	clk_register(&hck1);
}

/* --------------------------------------------------------------------
 *  GPIO
 * -------------------------------------------------------------------- */

static struct at91_gpio_bank at91sam9261_gpio[] = {
	{
		.id		= AT91SAM9261_ID_PIOA,
		.offset		= AT91_PIOA,
		.clock		= &pioA_clk,
	}, {
		.id		= AT91SAM9261_ID_PIOB,
		.offset		= AT91_PIOB,
		.clock		= &pioB_clk,
	}, {
		.id		= AT91SAM9261_ID_PIOC,
		.offset		= AT91_PIOC,
		.clock		= &pioC_clk,
	}
};

static void at91sam9261_reset(void)
{
	at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
}

static void at91sam9261_poweroff(void)
{
	at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
}


/* --------------------------------------------------------------------
 *  AT91SAM9261 processor initialization
 * -------------------------------------------------------------------- */

void __init at91sam9261_initialize(unsigned long main_clock)
{
	/* Map peripherals */
	iotable_init(at91sam9261_io_desc, ARRAY_SIZE(at91sam9261_io_desc));

	at91_arch_reset = at91sam9261_reset;
	pm_power_off = at91sam9261_poweroff;
	at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1)
			| (1 << AT91SAM9261_ID_IRQ2);

	/* Init clock subsystem */
	at91_clock_init(main_clock);

	/* Register the processor-specific clocks */
	at91sam9261_register_clocks();

	/* Register GPIO subsystem */
	at91_gpio_init(at91sam9261_gpio, 3);
}

/* --------------------------------------------------------------------
 *  Interrupt initialization
 * -------------------------------------------------------------------- */

/*
 * The default interrupt priority levels (0 = lowest, 7 = highest).
 */
static unsigned int at91sam9261_default_irq_priority[NR_AIC_IRQS] __initdata = {
	7,	/* Advanced Interrupt Controller */
	7,	/* System Peripherals */
	1,	/* Parallel IO Controller A */
	1,	/* Parallel IO Controller B */
	1,	/* Parallel IO Controller C */
	0,
	5,	/* USART 0 */
	5,	/* USART 1 */
	5,	/* USART 2 */
	0,	/* Multimedia Card Interface */
	2,	/* USB Device Port */
	6,	/* Two-Wire Interface */
	5,	/* Serial Peripheral Interface 0 */
	5,	/* Serial Peripheral Interface 1 */
	4,	/* Serial Synchronous Controller 0 */
	4,	/* Serial Synchronous Controller 1 */
	4,	/* Serial Synchronous Controller 2 */
	0,	/* Timer Counter 0 */
	0,	/* Timer Counter 1 */
	0,	/* Timer Counter 2 */
	2,	/* USB Host port */
	3,	/* LCD Controller */
	0,
	0,
	0,
	0,
	0,
	0,
	0,
	0,	/* Advanced Interrupt Controller */
	0,	/* Advanced Interrupt Controller */
	0,	/* Advanced Interrupt Controller */
};

void __init at91sam9261_init_interrupts(unsigned int priority[NR_AIC_IRQS])
{
	if (!priority)
		priority = at91sam9261_default_irq_priority;

	/* Initialize the AIC interrupt controller */
	at91_aic_init(priority);

	/* Enable GPIO interrupts */
	at91_gpio_irq_setup();
}
Commit	Line	Data
62c1660d	1	/*
9d041268	2	* arch/arm/mach-at91/at91sam9261.c
62c1660d AV	3	*
	4	* Copyright (C) 2005 SAN People
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	*/
	12
	13	#include <linux/module.h>
3ef2fb42	14	#include <linux/pm.h>
62c1660d AV	15
	16	#include <asm/mach/arch.h>
	17	#include <asm/mach/map.h>
a09e64fb RK	18	#include <mach/at91sam9261.h>
	19	#include <mach/at91_pmc.h>
	20	#include <mach/at91_rstc.h>
	21	#include <mach/at91_shdwc.h>
62c1660d AV	22
	23	#include "generic.h"
	24	#include "clock.h"
	25
	26	static struct map_desc at91sam9261_io_desc[] __initdata = {
	27	{
	28	.virtual = AT91_VA_BASE_SYS,
	29	.pfn = __phys_to_pfn(AT91_BASE_SYS),
	30	.length = SZ_16K,
	31	.type = MT_DEVICE,
	32	}, {
	33	.virtual = AT91_IO_VIRT_BASE - AT91SAM9261_SRAM_SIZE,
	34	.pfn = __phys_to_pfn(AT91SAM9261_SRAM_BASE),
	35	.length = AT91SAM9261_SRAM_SIZE,
	36	.type = MT_DEVICE,
	37	},
	38	};
	39
	40	/* --------------------------------------------------------------------
	41	* Clocks
	42	* -------------------------------------------------------------------- */
	43
	44	/*
	45	* The peripheral clocks.
	46	*/
	47	static struct clk pioA_clk = {
	48	.name = "pioA_clk",
	49	.pmc_mask = 1 << AT91SAM9261_ID_PIOA,
	50	.type = CLK_TYPE_PERIPHERAL,
	51	};
	52	static struct clk pioB_clk = {
	53	.name = "pioB_clk",
	54	.pmc_mask = 1 << AT91SAM9261_ID_PIOB,
	55	.type = CLK_TYPE_PERIPHERAL,
	56	};
	57	static struct clk pioC_clk = {
	58	.name = "pioC_clk",
	59	.pmc_mask = 1 << AT91SAM9261_ID_PIOC,
	60	.type = CLK_TYPE_PERIPHERAL,
	61	};
	62	static struct clk usart0_clk = {
	63	.name = "usart0_clk",
	64	.pmc_mask = 1 << AT91SAM9261_ID_US0,
	65	.type = CLK_TYPE_PERIPHERAL,
	66	};
	67	static struct clk usart1_clk = {
	68	.name = "usart1_clk",
	69	.pmc_mask = 1 << AT91SAM9261_ID_US1,
	70	.type = CLK_TYPE_PERIPHERAL,
	71	};
	72	static struct clk usart2_clk = {
	73	.name = "usart2_clk",
	74	.pmc_mask = 1 << AT91SAM9261_ID_US2,
	75	.type = CLK_TYPE_PERIPHERAL,
	76	};
	77	static struct clk mmc_clk = {
	78	.name = "mci_clk",
	79	.pmc_mask = 1 << AT91SAM9261_ID_MCI,
	80	.type = CLK_TYPE_PERIPHERAL,
	81	};
	82	static struct clk udc_clk = {
	83	.name = "udc_clk",
	84	.pmc_mask = 1 << AT91SAM9261_ID_UDP,
	85	.type = CLK_TYPE_PERIPHERAL,
86	};
87	static struct clk twi_clk = {
88	.name = "twi_clk",
89	.pmc_mask = 1 << AT91SAM9261_ID_TWI,
90	.type = CLK_TYPE_PERIPHERAL,
91	};
92	static struct clk spi0_clk = {
93	.name = "spi0_clk",
94	.pmc_mask = 1 << AT91SAM9261_ID_SPI0,
95	.type = CLK_TYPE_PERIPHERAL,
96	};
97	static struct clk spi1_clk = {
98	.name = "spi1_clk",
99	.pmc_mask = 1 << AT91SAM9261_ID_SPI1,
100	.type = CLK_TYPE_PERIPHERAL,
101	};
e8788bab AV	102	static struct clk ssc0_clk = {
	103	.name = "ssc0_clk",
	104	.pmc_mask = 1 << AT91SAM9261_ID_SSC0,
	105	.type = CLK_TYPE_PERIPHERAL,
	106	};
	107	static struct clk ssc1_clk = {
	108	.name = "ssc1_clk",
	109	.pmc_mask = 1 << AT91SAM9261_ID_SSC1,
	110	.type = CLK_TYPE_PERIPHERAL,
	111	};
	112	static struct clk ssc2_clk = {
	113	.name = "ssc2_clk",
	114	.pmc_mask = 1 << AT91SAM9261_ID_SSC2,
	115	.type = CLK_TYPE_PERIPHERAL,
	116	};
c177a1e7 AV	117	static struct clk tc0_clk = {
	118	.name = "tc0_clk",
	119	.pmc_mask = 1 << AT91SAM9261_ID_TC0,
	120	.type = CLK_TYPE_PERIPHERAL,
	121	};
	122	static struct clk tc1_clk = {
	123	.name = "tc1_clk",
	124	.pmc_mask = 1 << AT91SAM9261_ID_TC1,
	125	.type = CLK_TYPE_PERIPHERAL,
	126	};
	127	static struct clk tc2_clk = {
	128	.name = "tc2_clk",
	129	.pmc_mask = 1 << AT91SAM9261_ID_TC2,
	130	.type = CLK_TYPE_PERIPHERAL,
	131	};
62c1660d AV	132	static struct clk ohci_clk = {
	133	.name = "ohci_clk",
	134	.pmc_mask = 1 << AT91SAM9261_ID_UHP,
	135	.type = CLK_TYPE_PERIPHERAL,
	136	};
	137	static struct clk lcdc_clk = {
	138	.name = "lcdc_clk",
	139	.pmc_mask = 1 << AT91SAM9261_ID_LCDC,
	140	.type = CLK_TYPE_PERIPHERAL,
	141	};
	142
	143	static struct clk *periph_clocks[] __initdata = {
	144	&pioA_clk,
	145	&pioB_clk,
	146	&pioC_clk,
	147	&usart0_clk,
	148	&usart1_clk,
	149	&usart2_clk,
	150	&mmc_clk,
	151	&udc_clk,
	152	&twi_clk,
	153	&spi0_clk,
	154	&spi1_clk,
e8788bab AV	155	&ssc0_clk,
	156	&ssc1_clk,
	157	&ssc2_clk,
c177a1e7 AV	158	&tc0_clk,
	159	&tc1_clk,
	160	&tc2_clk,
62c1660d AV	161	&ohci_clk,
	162	&lcdc_clk,
	163	// irq0 .. irq2
	164	};
	165
	166	/*
	167	* The four programmable clocks.
	168	* You must configure pin multiplexing to bring these signals out.
	169	*/
	170	static struct clk pck0 = {
	171	.name = "pck0",
	172	.pmc_mask = AT91_PMC_PCK0,
	173	.type = CLK_TYPE_PROGRAMMABLE,
	174	.id = 0,
	175	};
	176	static struct clk pck1 = {
	177	.name = "pck1",
	178	.pmc_mask = AT91_PMC_PCK1,
	179	.type = CLK_TYPE_PROGRAMMABLE,
	180	.id = 1,
	181	};
	182	static struct clk pck2 = {
	183	.name = "pck2",
	184	.pmc_mask = AT91_PMC_PCK2,
	185	.type = CLK_TYPE_PROGRAMMABLE,
	186	.id = 2,
	187	};
	188	static struct clk pck3 = {
	189	.name = "pck3",
	190	.pmc_mask = AT91_PMC_PCK3,
	191	.type = CLK_TYPE_PROGRAMMABLE,
	192	.id = 3,
	193	};
	194
	195	/* HClocks */
	196	static struct clk hck0 = {
	197	.name = "hck0",
	198	.pmc_mask = AT91_PMC_HCK0,
	199	.type = CLK_TYPE_SYSTEM,
	200	.id = 0,
	201	};
	202	static struct clk hck1 = {
	203	.name = "hck1",
	204	.pmc_mask = AT91_PMC_HCK1,
	205	.type = CLK_TYPE_SYSTEM,
	206	.id = 1,
	207	};
	208
	209	static void __init at91sam9261_register_clocks(void)
	210	{
	211	int i;
	212
	213	for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
	214	clk_register(periph_clocks[i]);
	215
	216	clk_register(&pck0);
	217	clk_register(&pck1);
	218	clk_register(&pck2);
	219	clk_register(&pck3);
	220
	221	clk_register(&hck0);
	222	clk_register(&hck1);
	223	}
	224
225	/* --------------------------------------------------------------------
226	* GPIO
227	* -------------------------------------------------------------------- */
228
229	static struct at91_gpio_bank at91sam9261_gpio[] = {
230	{
231	.id = AT91SAM9261_ID_PIOA,
232	.offset = AT91_PIOA,
233	.clock = &pioA_clk,
234	}, {
235	.id = AT91SAM9261_ID_PIOB,
236	.offset = AT91_PIOB,
237	.clock = &pioB_clk,
238	}, {
239	.id = AT91SAM9261_ID_PIOC,
240	.offset = AT91_PIOC,
241	.clock = &pioC_clk,
242	}
243	};
244
245	static void at91sam9261_reset(void)
246	{
dd1d2f44	247	at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY \| AT91_RSTC_PROCRST \| AT91_RSTC_PERRST);
62c1660d AV	248	}
62c1660d AV	249
3ef2fb42 AV	250	static void at91sam9261_poweroff(void)
	251	{
	252	at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY \| AT91_SHDW_SHDW);
	253	}
	254
62c1660d AV	255
	256	/* --------------------------------------------------------------------
	257	* AT91SAM9261 processor initialization
	258	* -------------------------------------------------------------------- */
	259
	260	void __init at91sam9261_initialize(unsigned long main_clock)
	261	{
	262	/* Map peripherals */
	263	iotable_init(at91sam9261_io_desc, ARRAY_SIZE(at91sam9261_io_desc));
	264
	265	at91_arch_reset = at91sam9261_reset;
3ef2fb42	266	pm_power_off = at91sam9261_poweroff;
62c1660d AV	267	at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) \| (1 << AT91SAM9261_ID_IRQ1)
	268	\| (1 << AT91SAM9261_ID_IRQ2);
	269
	270	/* Init clock subsystem */
	271	at91_clock_init(main_clock);
	272
	273	/* Register the processor-specific clocks */
	274	at91sam9261_register_clocks();
	275
	276	/* Register GPIO subsystem */
	277	at91_gpio_init(at91sam9261_gpio, 3);
	278	}
	279
	280	/* --------------------------------------------------------------------
	281	* Interrupt initialization
	282	* -------------------------------------------------------------------- */
	283
	284	/*
	285	* The default interrupt priority levels (0 = lowest, 7 = highest).
	286	*/
	287	static unsigned int at91sam9261_default_irq_priority[NR_AIC_IRQS] __initdata = {
	288	7, /* Advanced Interrupt Controller */
	289	7, /* System Peripherals */
7cbed2b5 AV	290	1, /* Parallel IO Controller A */
	291	1, /* Parallel IO Controller B */
	292	1, /* Parallel IO Controller C */
62c1660d	293	0,
7cbed2b5 AV	294	5, /* USART 0 */
	295	5, /* USART 1 */
	296	5, /* USART 2 */
62c1660d	297	0, /* Multimedia Card Interface */
7cbed2b5 AV	298	2, /* USB Device Port */
	299	6, /* Two-Wire Interface */
	300	5, /* Serial Peripheral Interface 0 */
	301	5, /* Serial Peripheral Interface 1 */
	302	4, /* Serial Synchronous Controller 0 */
	303	4, /* Serial Synchronous Controller 1 */
	304	4, /* Serial Synchronous Controller 2 */
62c1660d AV	305	0, /* Timer Counter 0 */
	306	0, /* Timer Counter 1 */
	307	0, /* Timer Counter 2 */
7cbed2b5	308	2, /* USB Host port */
62c1660d AV	309	3, /* LCD Controller */
	310	0,
	311	0,
	312	0,
	313	0,
	314	0,
	315	0,
	316	0,
	317	0, /* Advanced Interrupt Controller */
	318	0, /* Advanced Interrupt Controller */
	319	0, /* Advanced Interrupt Controller */
	320	};
	321
	322	void __init at91sam9261_init_interrupts(unsigned int priority[NR_AIC_IRQS])
	323	{
	324	if (!priority)
	325	priority = at91sam9261_default_irq_priority;
	326
	327	/* Initialize the AIC interrupt controller */
	328	at91_aic_init(priority);
	329
	330	/* Enable GPIO interrupts */
	331	at91_gpio_irq_setup();
	332	}