[deliverable/linux.git] / arch / arm / mach-at91 / at91sam9261.c

/*
 * arch/arm/mach-at91/at91sam9261.c
 *
 *  Copyright (C) 2005 SAN People
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 */

#include <linux/module.h>

#include <asm/proc-fns.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/system_misc.h>
#include <mach/cpu.h>
#include <mach/at91sam9261.h>
#include <mach/at91_pmc.h>

#include "at91_aic.h"
#include "at91_rstc.h"
#include "soc.h"
#include "generic.h"
#include "clock.h"
#include "sam9_smc.h"

/* --------------------------------------------------------------------
 *  Clocks
 * -------------------------------------------------------------------- */

/*
 * The peripheral clocks.
 */
static struct clk pioA_clk = {
	.name		= "pioA_clk",
	.pmc_mask	= 1 << AT91SAM9261_ID_PIOA,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk pioB_clk = {
	.name		= "pioB_clk",
	.pmc_mask	= 1 << AT91SAM9261_ID_PIOB,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk pioC_clk = {
	.name		= "pioC_clk",
	.pmc_mask	= 1 << AT91SAM9261_ID_PIOC,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart0_clk = {
	.name		= "usart0_clk",
	.pmc_mask	= 1 << AT91SAM9261_ID_US0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart1_clk = {
	.name		= "usart1_clk",
	.pmc_mask	= 1 << AT91SAM9261_ID_US1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart2_clk = {
	.name		= "usart2_clk",
	.pmc_mask	= 1 << AT91SAM9261_ID_US2,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk mmc_clk = {
	.name		= "mci_clk",
	.pmc_mask	= 1 << AT91SAM9261_ID_MCI,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk udc_clk = {
	.name		= "udc_clk",
	.pmc_mask	= 1 << AT91SAM9261_ID_UDP,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk twi_clk = {
	.name		= "twi_clk",
	.pmc_mask	= 1 << AT91SAM9261_ID_TWI,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk spi0_clk = {
	.name		= "spi0_clk",
	.pmc_mask	= 1 << AT91SAM9261_ID_SPI0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk spi1_clk = {
	.name		= "spi1_clk",
	.pmc_mask	= 1 << AT91SAM9261_ID_SPI1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk ssc0_clk = {
	.name		= "ssc0_clk",
	.pmc_mask	= 1 << AT91SAM9261_ID_SSC0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk ssc1_clk = {
	.name		= "ssc1_clk",
	.pmc_mask	= 1 << AT91SAM9261_ID_SSC1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk ssc2_clk = {
	.name		= "ssc2_clk",
	.pmc_mask	= 1 << AT91SAM9261_ID_SSC2,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk tc0_clk = {
	.name		= "tc0_clk",
	.pmc_mask	= 1 << AT91SAM9261_ID_TC0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk tc1_clk = {
	.name		= "tc1_clk",
	.pmc_mask	= 1 << AT91SAM9261_ID_TC1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk tc2_clk = {
	.name		= "tc2_clk",
	.pmc_mask	= 1 << AT91SAM9261_ID_TC2,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk ohci_clk = {
	.name		= "ohci_clk",
	.pmc_mask	= 1 << AT91SAM9261_ID_UHP,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk lcdc_clk = {
	.name		= "lcdc_clk",
	.pmc_mask	= 1 << AT91SAM9261_ID_LCDC,
	.type		= CLK_TYPE_PERIPHERAL,
};

/* HClocks */
static struct clk hck0 = {
	.name		= "hck0",
	.pmc_mask	= AT91_PMC_HCK0,
	.type		= CLK_TYPE_SYSTEM,
	.id		= 0,
};
static struct clk hck1 = {
	.name		= "hck1",
	.pmc_mask	= AT91_PMC_HCK1,
	.type		= CLK_TYPE_SYSTEM,
	.id		= 1,
};

static struct clk *periph_clocks[] __initdata = {
	&pioA_clk,
	&pioB_clk,
	&pioC_clk,
	&usart0_clk,
	&usart1_clk,
	&usart2_clk,
	&mmc_clk,
	&udc_clk,
	&twi_clk,
	&spi0_clk,
	&spi1_clk,
	&ssc0_clk,
	&ssc1_clk,
	&ssc2_clk,
	&tc0_clk,
	&tc1_clk,
	&tc2_clk,
	&ohci_clk,
	&lcdc_clk,
	// irq0 .. irq2
};

static struct clk_lookup periph_clocks_lookups[] = {
	CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
	CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
	CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
	CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
	CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
	CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk),
	CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
	CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.2", &ssc2_clk),
	CLKDEV_CON_DEV_ID("pclk", "fffbc000.ssc", &ssc0_clk),
	CLKDEV_CON_DEV_ID("pclk", "fffc0000.ssc", &ssc1_clk),
	CLKDEV_CON_DEV_ID("pclk", "fffc4000.ssc", &ssc2_clk),
	CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &hck0),
	CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9261.0", &twi_clk),
	CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.0", &twi_clk),
	CLKDEV_CON_ID("pioA", &pioA_clk),
	CLKDEV_CON_ID("pioB", &pioB_clk),
	CLKDEV_CON_ID("pioC", &pioC_clk),
};

static struct clk_lookup usart_clocks_lookups[] = {
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
};

/*
 * The four programmable clocks.
 * You must configure pin multiplexing to bring these signals out.
 */
static struct clk pck0 = {
	.name		= "pck0",
	.pmc_mask	= AT91_PMC_PCK0,
	.type		= CLK_TYPE_PROGRAMMABLE,
	.id		= 0,
};
static struct clk pck1 = {
	.name		= "pck1",
	.pmc_mask	= AT91_PMC_PCK1,
	.type		= CLK_TYPE_PROGRAMMABLE,
	.id		= 1,
};
static struct clk pck2 = {
	.name		= "pck2",
	.pmc_mask	= AT91_PMC_PCK2,
	.type		= CLK_TYPE_PROGRAMMABLE,
	.id		= 2,
};
static struct clk pck3 = {
	.name		= "pck3",
	.pmc_mask	= AT91_PMC_PCK3,
	.type		= CLK_TYPE_PROGRAMMABLE,
	.id		= 3,
};

static void __init at91sam9261_register_clocks(void)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
		clk_register(periph_clocks[i]);

	clkdev_add_table(periph_clocks_lookups,
			 ARRAY_SIZE(periph_clocks_lookups));
	clkdev_add_table(usart_clocks_lookups,
			 ARRAY_SIZE(usart_clocks_lookups));

	clk_register(&pck0);
	clk_register(&pck1);
	clk_register(&pck2);
	clk_register(&pck3);

	clk_register(&hck0);
	clk_register(&hck1);
}

/* --------------------------------------------------------------------
 *  GPIO
 * -------------------------------------------------------------------- */

static struct at91_gpio_bank at91sam9261_gpio[] __initdata = {
	{
		.id		= AT91SAM9261_ID_PIOA,
		.regbase	= AT91SAM9261_BASE_PIOA,
	}, {
		.id		= AT91SAM9261_ID_PIOB,
		.regbase	= AT91SAM9261_BASE_PIOB,
	}, {
		.id		= AT91SAM9261_ID_PIOC,
		.regbase	= AT91SAM9261_BASE_PIOC,
	}
};

/* --------------------------------------------------------------------
 *  AT91SAM9261 processor initialization
 * -------------------------------------------------------------------- */

static void __init at91sam9261_map_io(void)
{
	if (cpu_is_at91sam9g10())
		at91_init_sram(0, AT91SAM9G10_SRAM_BASE, AT91SAM9G10_SRAM_SIZE);
	else
		at91_init_sram(0, AT91SAM9261_SRAM_BASE, AT91SAM9261_SRAM_SIZE);
}

static void __init at91sam9261_ioremap_registers(void)
{
	at91_ioremap_shdwc(AT91SAM9261_BASE_SHDWC);
	at91_ioremap_rstc(AT91SAM9261_BASE_RSTC);
	at91_ioremap_ramc(0, AT91SAM9261_BASE_SDRAMC, 512);
	at91sam926x_ioremap_pit(AT91SAM9261_BASE_PIT);
	at91sam9_ioremap_smc(0, AT91SAM9261_BASE_SMC);
	at91_ioremap_matrix(AT91SAM9261_BASE_MATRIX);
}

static void __init at91sam9261_initialize(void)
{
	arm_pm_idle = at91sam9_idle;
	arm_pm_restart = at91sam9_alt_restart;
	at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1)
			| (1 << AT91SAM9261_ID_IRQ2);

	/* Register GPIO subsystem */
	at91_gpio_init(at91sam9261_gpio, 3);
}

/* --------------------------------------------------------------------
 *  Interrupt initialization
 * -------------------------------------------------------------------- */

/*
 * The default interrupt priority levels (0 = lowest, 7 = highest).
 */
static unsigned int at91sam9261_default_irq_priority[NR_AIC_IRQS] __initdata = {
	7,	/* Advanced Interrupt Controller */
	7,	/* System Peripherals */
	1,	/* Parallel IO Controller A */
	1,	/* Parallel IO Controller B */
	1,	/* Parallel IO Controller C */
	0,
	5,	/* USART 0 */
	5,	/* USART 1 */
	5,	/* USART 2 */
	0,	/* Multimedia Card Interface */
	2,	/* USB Device Port */
	6,	/* Two-Wire Interface */
	5,	/* Serial Peripheral Interface 0 */
	5,	/* Serial Peripheral Interface 1 */
	4,	/* Serial Synchronous Controller 0 */
	4,	/* Serial Synchronous Controller 1 */
	4,	/* Serial Synchronous Controller 2 */
	0,	/* Timer Counter 0 */
	0,	/* Timer Counter 1 */
	0,	/* Timer Counter 2 */
	2,	/* USB Host port */
	3,	/* LCD Controller */
	0,
	0,
	0,
	0,
	0,
	0,
	0,
	0,	/* Advanced Interrupt Controller */
	0,	/* Advanced Interrupt Controller */
	0,	/* Advanced Interrupt Controller */
};

AT91_SOC_START(at91sam9261)
	.map_io = at91sam9261_map_io,
	.default_irq_priority = at91sam9261_default_irq_priority,
	.ioremap_registers = at91sam9261_ioremap_registers,
	.register_clocks = at91sam9261_register_clocks,
	.init = at91sam9261_initialize,
AT91_SOC_END
Commit	Line	Data
62c1660d	1	/*
9d041268	2	* arch/arm/mach-at91/at91sam9261.c
62c1660d AV	3	*
	4	* Copyright (C) 2005 SAN People
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	*/
	12
	13	#include <linux/module.h>
	14
c9dfafba	15	#include <asm/proc-fns.h>
80b02c17	16	#include <asm/irq.h>
62c1660d AV	17	#include <asm/mach/arch.h>
62c1660d AV	18	#include <asm/mach/map.h>
9f97da78	19	#include <asm/system_misc.h>
b319ff80	20	#include <mach/cpu.h>
a09e64fb RK	21	#include <mach/at91sam9261.h>
a09e64fb RK	22	#include <mach/at91_pmc.h>
62c1660d	23
a510b9ba	24	#include "at91_aic.h"
f0995d08	25	#include "at91_rstc.h"
21d08b9d	26	#include "soc.h"
62c1660d AV	27	#include "generic.h"
62c1660d AV	28	#include "clock.h"
faee0cc3	29	#include "sam9_smc.h"
62c1660d	30
62c1660d AV	31	/* --------------------------------------------------------------------
	32	* Clocks
	33	* -------------------------------------------------------------------- */
	34
	35	/*
	36	* The peripheral clocks.
	37	*/
	38	static struct clk pioA_clk = {
	39	.name = "pioA_clk",
	40	.pmc_mask = 1 << AT91SAM9261_ID_PIOA,
	41	.type = CLK_TYPE_PERIPHERAL,
	42	};
	43	static struct clk pioB_clk = {
	44	.name = "pioB_clk",
	45	.pmc_mask = 1 << AT91SAM9261_ID_PIOB,
	46	.type = CLK_TYPE_PERIPHERAL,
	47	};
	48	static struct clk pioC_clk = {
	49	.name = "pioC_clk",
	50	.pmc_mask = 1 << AT91SAM9261_ID_PIOC,
	51	.type = CLK_TYPE_PERIPHERAL,
	52	};
	53	static struct clk usart0_clk = {
	54	.name = "usart0_clk",
	55	.pmc_mask = 1 << AT91SAM9261_ID_US0,
	56	.type = CLK_TYPE_PERIPHERAL,
	57	};
	58	static struct clk usart1_clk = {
	59	.name = "usart1_clk",
	60	.pmc_mask = 1 << AT91SAM9261_ID_US1,
	61	.type = CLK_TYPE_PERIPHERAL,
	62	};
	63	static struct clk usart2_clk = {
	64	.name = "usart2_clk",
	65	.pmc_mask = 1 << AT91SAM9261_ID_US2,
	66	.type = CLK_TYPE_PERIPHERAL,
	67	};
	68	static struct clk mmc_clk = {
	69	.name = "mci_clk",
	70	.pmc_mask = 1 << AT91SAM9261_ID_MCI,
	71	.type = CLK_TYPE_PERIPHERAL,
	72	};
	73	static struct clk udc_clk = {
	74	.name = "udc_clk",
	75	.pmc_mask = 1 << AT91SAM9261_ID_UDP,
	76	.type = CLK_TYPE_PERIPHERAL,
	77	};
	78	static struct clk twi_clk = {
	79	.name = "twi_clk",
	80	.pmc_mask = 1 << AT91SAM9261_ID_TWI,
	81	.type = CLK_TYPE_PERIPHERAL,
	82	};
	83	static struct clk spi0_clk = {
	84	.name = "spi0_clk",
	85	.pmc_mask = 1 << AT91SAM9261_ID_SPI0,
	86	.type = CLK_TYPE_PERIPHERAL,
	87	};
	88	static struct clk spi1_clk = {
	89	.name = "spi1_clk",
	90	.pmc_mask = 1 << AT91SAM9261_ID_SPI1,
	91	.type = CLK_TYPE_PERIPHERAL,
	92	};
e8788bab AV	93	static struct clk ssc0_clk = {
	94	.name = "ssc0_clk",
	95	.pmc_mask = 1 << AT91SAM9261_ID_SSC0,
	96	.type = CLK_TYPE_PERIPHERAL,
	97	};
	98	static struct clk ssc1_clk = {
	99	.name = "ssc1_clk",
	100	.pmc_mask = 1 << AT91SAM9261_ID_SSC1,
	101	.type = CLK_TYPE_PERIPHERAL,
	102	};
	103	static struct clk ssc2_clk = {
	104	.name = "ssc2_clk",
	105	.pmc_mask = 1 << AT91SAM9261_ID_SSC2,
	106	.type = CLK_TYPE_PERIPHERAL,
	107	};
c177a1e7 AV	108	static struct clk tc0_clk = {
	109	.name = "tc0_clk",
	110	.pmc_mask = 1 << AT91SAM9261_ID_TC0,
	111	.type = CLK_TYPE_PERIPHERAL,
	112	};
	113	static struct clk tc1_clk = {
	114	.name = "tc1_clk",
	115	.pmc_mask = 1 << AT91SAM9261_ID_TC1,
	116	.type = CLK_TYPE_PERIPHERAL,
	117	};
	118	static struct clk tc2_clk = {
	119	.name = "tc2_clk",
	120	.pmc_mask = 1 << AT91SAM9261_ID_TC2,
	121	.type = CLK_TYPE_PERIPHERAL,
	122	};
62c1660d AV	123	static struct clk ohci_clk = {
	124	.name = "ohci_clk",
	125	.pmc_mask = 1 << AT91SAM9261_ID_UHP,
	126	.type = CLK_TYPE_PERIPHERAL,
	127	};
	128	static struct clk lcdc_clk = {
	129	.name = "lcdc_clk",
	130	.pmc_mask = 1 << AT91SAM9261_ID_LCDC,
	131	.type = CLK_TYPE_PERIPHERAL,
	132	};
	133
0af4316b JCPV	134	/* HClocks */
	135	static struct clk hck0 = {
	136	.name = "hck0",
	137	.pmc_mask = AT91_PMC_HCK0,
	138	.type = CLK_TYPE_SYSTEM,
	139	.id = 0,
	140	};
	141	static struct clk hck1 = {
	142	.name = "hck1",
	143	.pmc_mask = AT91_PMC_HCK1,
	144	.type = CLK_TYPE_SYSTEM,
	145	.id = 1,
	146	};
	147
62c1660d AV	148	static struct clk *periph_clocks[] __initdata = {
	149	&pioA_clk,
	150	&pioB_clk,
	151	&pioC_clk,
	152	&usart0_clk,
	153	&usart1_clk,
	154	&usart2_clk,
	155	&mmc_clk,
	156	&udc_clk,
	157	&twi_clk,
	158	&spi0_clk,
	159	&spi1_clk,
e8788bab AV	160	&ssc0_clk,
	161	&ssc1_clk,
	162	&ssc2_clk,
c177a1e7 AV	163	&tc0_clk,
	164	&tc1_clk,
	165	&tc2_clk,
62c1660d AV	166	&ohci_clk,
	167	&lcdc_clk,
	168	// irq0 .. irq2
	169	};
	170
bd602995 JCPV	171	static struct clk_lookup periph_clocks_lookups[] = {
	172	CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
	173	CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
	174	CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
	175	CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
c0764b2a	176	CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
636036d2 BS	177	CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk),
	178	CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
	179	CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.2", &ssc2_clk),
099343c6 BS	180	CLKDEV_CON_DEV_ID("pclk", "fffbc000.ssc", &ssc0_clk),
	181	CLKDEV_CON_DEV_ID("pclk", "fffc0000.ssc", &ssc1_clk),
	182	CLKDEV_CON_DEV_ID("pclk", "fffc4000.ssc", &ssc2_clk),
0af4316b	183	CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &hck0),
302090a6 BS	184	CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9261.0", &twi_clk),
302090a6 BS	185	CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.0", &twi_clk),
619d4a4b JCPV	186	CLKDEV_CON_ID("pioA", &pioA_clk),
	187	CLKDEV_CON_ID("pioB", &pioB_clk),
	188	CLKDEV_CON_ID("pioC", &pioC_clk),
bd602995 JCPV	189	};
	190
	191	static struct clk_lookup usart_clocks_lookups[] = {
	192	CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
	193	CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
	194	CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
	195	CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
	196	};
	197
62c1660d AV	198	/*
	199	* The four programmable clocks.
	200	* You must configure pin multiplexing to bring these signals out.
	201	*/
	202	static struct clk pck0 = {
	203	.name = "pck0",
	204	.pmc_mask = AT91_PMC_PCK0,
	205	.type = CLK_TYPE_PROGRAMMABLE,
	206	.id = 0,
	207	};
	208	static struct clk pck1 = {
	209	.name = "pck1",
	210	.pmc_mask = AT91_PMC_PCK1,
	211	.type = CLK_TYPE_PROGRAMMABLE,
	212	.id = 1,
	213	};
	214	static struct clk pck2 = {
	215	.name = "pck2",
	216	.pmc_mask = AT91_PMC_PCK2,
	217	.type = CLK_TYPE_PROGRAMMABLE,
	218	.id = 2,
	219	};
	220	static struct clk pck3 = {
	221	.name = "pck3",
	222	.pmc_mask = AT91_PMC_PCK3,
	223	.type = CLK_TYPE_PROGRAMMABLE,
	224	.id = 3,
	225	};
	226
62c1660d AV	227	static void __init at91sam9261_register_clocks(void)
	228	{
	229	int i;
	230
	231	for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
	232	clk_register(periph_clocks[i]);
	233
bd602995 JCPV	234	clkdev_add_table(periph_clocks_lookups,
	235	ARRAY_SIZE(periph_clocks_lookups));
	236	clkdev_add_table(usart_clocks_lookups,
	237	ARRAY_SIZE(usart_clocks_lookups));
	238
62c1660d AV	239	clk_register(&pck0);
	240	clk_register(&pck1);
	241	clk_register(&pck2);
	242	clk_register(&pck3);
	243
	244	clk_register(&hck0);
	245	clk_register(&hck1);
	246	}
	247
	248	/* --------------------------------------------------------------------
	249	* GPIO
	250	* -------------------------------------------------------------------- */
	251
1a2d9156	252	static struct at91_gpio_bank at91sam9261_gpio[] __initdata = {
62c1660d AV	253	{
62c1660d AV	254	.id = AT91SAM9261_ID_PIOA,
80e91cb8	255	.regbase = AT91SAM9261_BASE_PIOA,
62c1660d AV	256	}, {
62c1660d AV	257	.id = AT91SAM9261_ID_PIOB,
80e91cb8	258	.regbase = AT91SAM9261_BASE_PIOB,
62c1660d AV	259	}, {
62c1660d AV	260	.id = AT91SAM9261_ID_PIOC,
80e91cb8	261	.regbase = AT91SAM9261_BASE_PIOC,
62c1660d AV	262	}
	263	};
	264
62c1660d AV	265	/* --------------------------------------------------------------------
	266	* AT91SAM9261 processor initialization
	267	* -------------------------------------------------------------------- */
	268
21d08b9d	269	static void __init at91sam9261_map_io(void)
62c1660d	270	{
b319ff80	271	if (cpu_is_at91sam9g10())
f0051d82	272	at91_init_sram(0, AT91SAM9G10_SRAM_BASE, AT91SAM9G10_SRAM_SIZE);
b319ff80	273	else
f0051d82	274	at91_init_sram(0, AT91SAM9261_SRAM_BASE, AT91SAM9261_SRAM_SIZE);
1b021a3b	275	}
b319ff80	276
cfa5a1fe JCPV	277	static void __init at91sam9261_ioremap_registers(void)
cfa5a1fe JCPV	278	{
f22deee5	279	at91_ioremap_shdwc(AT91SAM9261_BASE_SHDWC);
e9f68b5c	280	at91_ioremap_rstc(AT91SAM9261_BASE_RSTC);
f363c407	281	at91_ioremap_ramc(0, AT91SAM9261_BASE_SDRAMC, 512);
4ab0c599	282	at91sam926x_ioremap_pit(AT91SAM9261_BASE_PIT);
faee0cc3	283	at91sam9_ioremap_smc(0, AT91SAM9261_BASE_SMC);
4342d647	284	at91_ioremap_matrix(AT91SAM9261_BASE_MATRIX);
cfa5a1fe JCPV	285	}
cfa5a1fe JCPV	286
46539374	287	static void __init at91sam9261_initialize(void)
1b021a3b	288	{
0d781716	289	arm_pm_idle = at91sam9_idle;
1b2073e7	290	arm_pm_restart = at91sam9_alt_restart;
62c1660d AV	291	at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) \| (1 << AT91SAM9261_ID_IRQ1)
	292	\| (1 << AT91SAM9261_ID_IRQ2);
	293
62c1660d AV	294	/* Register GPIO subsystem */
	295	at91_gpio_init(at91sam9261_gpio, 3);
	296	}
	297
	298	/* --------------------------------------------------------------------
	299	* Interrupt initialization
	300	* -------------------------------------------------------------------- */
	301
	302	/*
	303	* The default interrupt priority levels (0 = lowest, 7 = highest).
	304	*/
	305	static unsigned int at91sam9261_default_irq_priority[NR_AIC_IRQS] __initdata = {
	306	7, /* Advanced Interrupt Controller */
	307	7, /* System Peripherals */
7cbed2b5 AV	308	1, /* Parallel IO Controller A */
	309	1, /* Parallel IO Controller B */
	310	1, /* Parallel IO Controller C */
62c1660d	311	0,
7cbed2b5 AV	312	5, /* USART 0 */
	313	5, /* USART 1 */
	314	5, /* USART 2 */
62c1660d	315	0, /* Multimedia Card Interface */
7cbed2b5 AV	316	2, /* USB Device Port */
	317	6, /* Two-Wire Interface */
	318	5, /* Serial Peripheral Interface 0 */
	319	5, /* Serial Peripheral Interface 1 */
	320	4, /* Serial Synchronous Controller 0 */
	321	4, /* Serial Synchronous Controller 1 */
	322	4, /* Serial Synchronous Controller 2 */
62c1660d AV	323	0, /* Timer Counter 0 */
	324	0, /* Timer Counter 1 */
	325	0, /* Timer Counter 2 */
7cbed2b5	326	2, /* USB Host port */
62c1660d AV	327	3, /* LCD Controller */
	328	0,
	329	0,
	330	0,
	331	0,
	332	0,
	333	0,
	334	0,
	335	0, /* Advanced Interrupt Controller */
	336	0, /* Advanced Interrupt Controller */
	337	0, /* Advanced Interrupt Controller */
	338	};
	339
84ddb087	340	AT91_SOC_START(at91sam9261)
21d08b9d	341	.map_io = at91sam9261_map_io,
92100c12	342	.default_irq_priority = at91sam9261_default_irq_priority,
cfa5a1fe	343	.ioremap_registers = at91sam9261_ioremap_registers,
51ddec76	344	.register_clocks = at91sam9261_register_clocks,
21d08b9d	345	.init = at91sam9261_initialize,
8d39e0fd	346	AT91_SOC_END