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Merge git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6
[deliverable/linux.git] / arch / arm / mach-at91 / at91sam9261_devices.c
CommitLineData
86ad76bb 1/*
9d041268 2 * arch/arm/mach-at91/at91sam9261_devices.c
86ad76bb
AV		 3 *
4 * Copyright (C) 2005 Thibaut VARENE <varenet@parisc-linux.org>
5 * Copyright (C) 2005 David Brownell
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 */
13#include <asm/mach/arch.h>
14#include <asm/mach/map.h>
15
c6686ff9 16#include <linux/dma-mapping.h>
2f8163ba 17#include <linux/gpio.h>
86ad76bb 18#include <linux/platform_device.h>
f230d3f5 19#include <linux/i2c-gpio.h>
86ad76bb 20
f230d3f5 21#include <linux/fb.h>
b8b78609
JA		 22#include <video/atmel_lcdc.h>
23
a09e64fb
RK		 24#include <mach/at91sam9261.h>
25#include <mach/at91sam9261_matrix.h>
4342d647 26#include <mach/at91_matrix.h>
a09e64fb 27#include <mach/at91sam9_smc.h>
86ad76bb 28
43d2f532 29#include "board.h"
86ad76bb
AV		 30#include "generic.h"
31
86ad76bb
AV		 32
33/* --------------------------------------------------------------------
34 * USB Host
35 * -------------------------------------------------------------------- */
36
37#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
c6686ff9 38static u64 ohci_dmamask = DMA_BIT_MASK(32);
86ad76bb
AV		 39static struct at91_usbh_data usbh_data;
40
41static struct resource usbh_resources[] = {
42 [0] = {
43 .start = AT91SAM9261_UHP_BASE,
44 .end = AT91SAM9261_UHP_BASE + SZ_1M - 1,
45 .flags = IORESOURCE_MEM,
46 },
47 [1] = {
8fe82a55
LD		 48 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_UHP,
49 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_UHP,
86ad76bb
AV		 50 .flags = IORESOURCE_IRQ,
51 },
52};
53
54static struct platform_device at91sam9261_usbh_device = {
55 .name = "at91_ohci",
56 .id = -1,
57 .dev = {
58 .dma_mask = &ohci_dmamask,
c6686ff9 59 .coherent_dma_mask = DMA_BIT_MASK(32),
86ad76bb
AV		 60 .platform_data = &usbh_data,
61 },
62 .resource = usbh_resources,
63 .num_resources = ARRAY_SIZE(usbh_resources),
64};
65
66void __init at91_add_device_usbh(struct at91_usbh_data *data)
67{
1fcaea7e
TP		 68 int i;
69
86ad76bb
AV		 70 if (!data)
71 return;
72
1fcaea7e
TP		 73 /* Enable overcurrent notification */
74 for (i = 0; i < data->ports; i++) {
641f3ce6 75 if (gpio_is_valid(data->overcurrent_pin[i]))
1fcaea7e
TP		 76 at91_set_gpio_input(data->overcurrent_pin[i], 1);
77 }
78
86ad76bb
AV		 79 usbh_data = *data;
80 platform_device_register(&at91sam9261_usbh_device);
81}
82#else
83void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
84#endif
85
86
87/* --------------------------------------------------------------------
88 * USB Device (Gadget)
89 * -------------------------------------------------------------------- */
90
e8c9dc93 91#if defined(CONFIG_USB_AT91) || defined(CONFIG_USB_AT91_MODULE)
86ad76bb
AV		 92static struct at91_udc_data udc_data;
93
94static struct resource udc_resources[] = {
95 [0] = {
96 .start = AT91SAM9261_BASE_UDP,
97 .end = AT91SAM9261_BASE_UDP + SZ_16K - 1,
98 .flags = IORESOURCE_MEM,
99 },
100 [1] = {
8fe82a55
LD		 101 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_UDP,
102 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_UDP,
86ad76bb
AV		 103 .flags = IORESOURCE_IRQ,
104 },
105};
106
107static struct platform_device at91sam9261_udc_device = {
108 .name = "at91_udc",
109 .id = -1,
110 .dev = {
111 .platform_data = &udc_data,
112 },
113 .resource = udc_resources,
114 .num_resources = ARRAY_SIZE(udc_resources),
115};
116
117void __init at91_add_device_udc(struct at91_udc_data *data)
118{
86ad76bb
AV		 119 if (!data)
120 return;
121
cc9f9aef 122 if (gpio_is_valid(data->vbus_pin)) {
86ad76bb
AV		 123 at91_set_gpio_input(data->vbus_pin, 0);
124 at91_set_deglitch(data->vbus_pin, 1);
125 }
126
da7a42d6 127 /* Pullup pin is handled internally by USB device peripheral */
86ad76bb
AV		 128
129 udc_data = *data;
130 platform_device_register(&at91sam9261_udc_device);
131}
132#else
133void __init at91_add_device_udc(struct at91_udc_data *data) {}
134#endif
135
136/* --------------------------------------------------------------------
137 * MMC / SD
138 * -------------------------------------------------------------------- */
139
4cf3326a 140#if IS_ENABLED(CONFIG_MMC_ATMELMCI)
c6686ff9 141static u64 mmc_dmamask = DMA_BIT_MASK(32);
4cf3326a 142static struct mci_platform_data mmc_data;
86ad76bb
AV		 143
144static struct resource mmc_resources[] = {
145 [0] = {
146 .start = AT91SAM9261_BASE_MCI,
147 .end = AT91SAM9261_BASE_MCI + SZ_16K - 1,
148 .flags = IORESOURCE_MEM,
149 },
150 [1] = {
8fe82a55
LD		 151 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_MCI,
152 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_MCI,
86ad76bb
AV		 153 .flags = IORESOURCE_IRQ,
154 },
155};
156
157static struct platform_device at91sam9261_mmc_device = {
4cf3326a 158 .name = "atmel_mci",
86ad76bb
AV		 159 .id = -1,
160 .dev = {
161 .dma_mask = &mmc_dmamask,
c6686ff9 162 .coherent_dma_mask = DMA_BIT_MASK(32),
86ad76bb
AV		 163 .platform_data = &mmc_data,
164 },
165 .resource = mmc_resources,
166 .num_resources = ARRAY_SIZE(mmc_resources),
167};
168
4cf3326a 169void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data)
86ad76bb
AV		 170{
171 if (!data)
172 return;
173
4cf3326a
LD		 174 if (data->slot[0].bus_width) {
175 /* input/irq */
176 if (gpio_is_valid(data->slot[0].detect_pin)) {
177 at91_set_gpio_input(data->slot[0].detect_pin, 1);
178 at91_set_deglitch(data->slot[0].detect_pin, 1);
179 }
180 if (gpio_is_valid(data->slot[0].wp_pin))
181 at91_set_gpio_input(data->slot[0].wp_pin, 1);
182
183 /* CLK */
184 at91_set_B_periph(AT91_PIN_PA2, 0);
185
186 /* CMD */
187 at91_set_B_periph(AT91_PIN_PA1, 1);
188
189 /* DAT0, maybe DAT1..DAT3 */
190 at91_set_B_periph(AT91_PIN_PA0, 1);
191 if (data->slot[0].bus_width == 4) {
192 at91_set_B_periph(AT91_PIN_PA4, 1);
193 at91_set_B_periph(AT91_PIN_PA5, 1);
194 at91_set_B_periph(AT91_PIN_PA6, 1);
195 }
196
197 mmc_data = *data;
198 platform_device_register(&at91sam9261_mmc_device);
86ad76bb 199 }
86ad76bb
AV		 200}
201#else
4cf3326a 202void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data) {}
86ad76bb
AV		 203#endif
204
205
206/* --------------------------------------------------------------------
207 * NAND / SmartMedia
208 * -------------------------------------------------------------------- */
209
f6ed6f78 210#if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
3c3796cc 211static struct atmel_nand_data nand_data;
86ad76bb
AV		 212
213#define NAND_BASE AT91_CHIPSELECT_3
214
215static struct resource nand_resources[] = {
216 {
217 .start = NAND_BASE,
218 .end = NAND_BASE + SZ_256M - 1,
219 .flags = IORESOURCE_MEM,
220 }
221};
222
3c3796cc
HS		 223static struct platform_device atmel_nand_device = {
224 .name = "atmel_nand",
86ad76bb
AV		 225 .id = -1,
226 .dev = {
227 .platform_data = &nand_data,
228 },
229 .resource = nand_resources,
230 .num_resources = ARRAY_SIZE(nand_resources),
231};
232
3c3796cc 233void __init at91_add_device_nand(struct atmel_nand_data *data)
86ad76bb 234{
461d3b4d 235 unsigned long csa;
86ad76bb
AV		 236
237 if (!data)
238 return;
239
4342d647
JCPV		 240 csa = at91_matrix_read(AT91_MATRIX_EBICSA);
241 at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
86ad76bb 242
86ad76bb 243 /* enable pin */
cc9f9aef 244 if (gpio_is_valid(data->enable_pin))
86ad76bb
AV		 245 at91_set_gpio_output(data->enable_pin, 1);
246
247 /* ready/busy pin */
cc9f9aef 248 if (gpio_is_valid(data->rdy_pin))
86ad76bb
AV		 249 at91_set_gpio_input(data->rdy_pin, 1);
250
251 /* card detect pin */
cc9f9aef 252 if (gpio_is_valid(data->det_pin))
86ad76bb
AV		 253 at91_set_gpio_input(data->det_pin, 1);
254
255 at91_set_A_periph(AT91_PIN_PC0, 0); /* NANDOE */
256 at91_set_A_periph(AT91_PIN_PC1, 0); /* NANDWE */
257
258 nand_data = *data;
3c3796cc 259 platform_device_register(&atmel_nand_device);
86ad76bb
AV		 260}
261
262#else
3c3796cc 263void __init at91_add_device_nand(struct atmel_nand_data *data) {}
86ad76bb
AV		 264#endif
265
266
267/* --------------------------------------------------------------------
268 * TWI (i2c)
269 * -------------------------------------------------------------------- */
270
f230d3f5
AV		 271/*
272 * Prefer the GPIO code since the TWI controller isn't robust
273 * (gets overruns and underruns under load) and can only issue
274 * repeated STARTs in one scenario (the driver doesn't yet handle them).
275 */
276#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
277
278static struct i2c_gpio_platform_data pdata = {
279 .sda_pin = AT91_PIN_PA7,
280 .sda_is_open_drain = 1,
281 .scl_pin = AT91_PIN_PA8,
282 .scl_is_open_drain = 1,
283 .udelay = 2, /* ~100 kHz */
284};
285
286static struct platform_device at91sam9261_twi_device = {
287 .name = "i2c-gpio",
7840487c 288 .id = 0,
f230d3f5
AV		 289 .dev.platform_data = &pdata,
290};
291
292void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
293{
294 at91_set_GPIO_periph(AT91_PIN_PA7, 1); /* TWD (SDA) */
295 at91_set_multi_drive(AT91_PIN_PA7, 1);
296
297 at91_set_GPIO_periph(AT91_PIN_PA8, 1); /* TWCK (SCL) */
298 at91_set_multi_drive(AT91_PIN_PA8, 1);
299
300 i2c_register_board_info(0, devices, nr_devices);
301 platform_device_register(&at91sam9261_twi_device);
302}
303
304#elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
86ad76bb
AV		 305
306static struct resource twi_resources[] = {
307 [0] = {
308 .start = AT91SAM9261_BASE_TWI,
309 .end = AT91SAM9261_BASE_TWI + SZ_16K - 1,
310 .flags = IORESOURCE_MEM,
311 },
312 [1] = {
8fe82a55
LD		 313 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_TWI,
314 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_TWI,
86ad76bb
AV		 315 .flags = IORESOURCE_IRQ,
316 },
317};
318
319static struct platform_device at91sam9261_twi_device = {
302090a6 320 .id = 0,
86ad76bb
AV		 321 .resource = twi_resources,
322 .num_resources = ARRAY_SIZE(twi_resources),
323};
324
f230d3f5 325void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
86ad76bb 326{
fac368a0
NV		 327 /* IP version is not the same on 9261 and g10 */
328 if (cpu_is_at91sam9g10()) {
329 at91sam9261_twi_device.name = "i2c-at91sam9g10";
94e73465 330 /* I2C PIO must not be configured as open-drain on this chip */
fac368a0
NV		 331 } else {
332 at91sam9261_twi_device.name = "i2c-at91sam9261";
94e73465
LD		 333 at91_set_multi_drive(AT91_PIN_PA7, 1);
334 at91_set_multi_drive(AT91_PIN_PA8, 1);
fac368a0
NV		 335 }
336
86ad76bb
AV		 337 /* pins used for TWI interface */
338 at91_set_A_periph(AT91_PIN_PA7, 0); /* TWD */
86ad76bb 339 at91_set_A_periph(AT91_PIN_PA8, 0); /* TWCK */
86ad76bb 340
f230d3f5 341 i2c_register_board_info(0, devices, nr_devices);
86ad76bb
AV		 342 platform_device_register(&at91sam9261_twi_device);
343}
344#else
f230d3f5 345void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
86ad76bb
AV		 346#endif
347
348
349/* --------------------------------------------------------------------
350 * SPI
351 * -------------------------------------------------------------------- */
352
353#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
c6686ff9 354static u64 spi_dmamask = DMA_BIT_MASK(32);
86ad76bb
AV		 355
356static struct resource spi0_resources[] = {
357 [0] = {
358 .start = AT91SAM9261_BASE_SPI0,
359 .end = AT91SAM9261_BASE_SPI0 + SZ_16K - 1,
360 .flags = IORESOURCE_MEM,
361 },
362 [1] = {
8fe82a55
LD		 363 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_SPI0,
364 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_SPI0,
86ad76bb
AV		 365 .flags = IORESOURCE_IRQ,
366 },
367};
368
369static struct platform_device at91sam9261_spi0_device = {
370 .name = "atmel_spi",
371 .id = 0,
372 .dev = {
373 .dma_mask = &spi_dmamask,
c6686ff9 374 .coherent_dma_mask = DMA_BIT_MASK(32),
86ad76bb
AV		 375 },
376 .resource = spi0_resources,
377 .num_resources = ARRAY_SIZE(spi0_resources),
378};
379
380static const unsigned spi0_standard_cs[4] = { AT91_PIN_PA3, AT91_PIN_PA4, AT91_PIN_PA5, AT91_PIN_PA6 };
381
382static struct resource spi1_resources[] = {
383 [0] = {
384 .start = AT91SAM9261_BASE_SPI1,
385 .end = AT91SAM9261_BASE_SPI1 + SZ_16K - 1,
386 .flags = IORESOURCE_MEM,
387 },
388 [1] = {
8fe82a55
LD		 389 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_SPI1,
390 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_SPI1,
86ad76bb
AV		 391 .flags = IORESOURCE_IRQ,
392 },
393};
394
395static struct platform_device at91sam9261_spi1_device = {
396 .name = "atmel_spi",
397 .id = 1,
398 .dev = {
399 .dma_mask = &spi_dmamask,
c6686ff9 400 .coherent_dma_mask = DMA_BIT_MASK(32),
86ad76bb
AV		 401 },
402 .resource = spi1_resources,
403 .num_resources = ARRAY_SIZE(spi1_resources),
404};
405
406static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB28, AT91_PIN_PA24, AT91_PIN_PA25, AT91_PIN_PA26 };
407
408void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
409{
410 int i;
411 unsigned long cs_pin;
412 short enable_spi0 = 0;
413 short enable_spi1 = 0;
414
415 /* Choose SPI chip-selects */
416 for (i = 0; i < nr_devices; i++) {
417 if (devices[i].controller_data)
418 cs_pin = (unsigned long) devices[i].controller_data;
419 else if (devices[i].bus_num == 0)
420 cs_pin = spi0_standard_cs[devices[i].chip_select];
421 else
422 cs_pin = spi1_standard_cs[devices[i].chip_select];
423
0c2c1f62
NF		 424 if (!gpio_is_valid(cs_pin))
425 continue;
426
86ad76bb
AV		 427 if (devices[i].bus_num == 0)
428 enable_spi0 = 1;
429 else
430 enable_spi1 = 1;
431
432 /* enable chip-select pin */
433 at91_set_gpio_output(cs_pin, 1);
434
435 /* pass chip-select pin to driver */
436 devices[i].controller_data = (void *) cs_pin;
437 }
438
439 spi_register_board_info(devices, nr_devices);
440
441 /* Configure SPI bus(es) */
442 if (enable_spi0) {
443 at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
444 at91_set_A_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
445 at91_set_A_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */
446
86ad76bb
AV		 447 platform_device_register(&at91sam9261_spi0_device);
448 }
449 if (enable_spi1) {
450 at91_set_A_periph(AT91_PIN_PB30, 0); /* SPI1_MISO */
451 at91_set_A_periph(AT91_PIN_PB31, 0); /* SPI1_MOSI */
452 at91_set_A_periph(AT91_PIN_PB29, 0); /* SPI1_SPCK */
453
86ad76bb
AV		 454 platform_device_register(&at91sam9261_spi1_device);
455 }
456}
457#else
458void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
459#endif
460
461
462/* --------------------------------------------------------------------
463 * LCD Controller
464 * -------------------------------------------------------------------- */
465
7776a94c 466#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
c6686ff9 467static u64 lcdc_dmamask = DMA_BIT_MASK(32);
7776a94c 468static struct atmel_lcdfb_info lcdc_data;
86ad76bb
AV		 469
470static struct resource lcdc_resources[] = {
471 [0] = {
472 .start = AT91SAM9261_LCDC_BASE,
473 .end = AT91SAM9261_LCDC_BASE + SZ_4K - 1,
474 .flags = IORESOURCE_MEM,
475 },
476 [1] = {
8fe82a55
LD		 477 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_LCDC,
478 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_LCDC,
86ad76bb
AV		 479 .flags = IORESOURCE_IRQ,
480 },
481#if defined(CONFIG_FB_INTSRAM)
482 [2] = {
483 .start = AT91SAM9261_SRAM_BASE,
484 .end = AT91SAM9261_SRAM_BASE + AT91SAM9261_SRAM_SIZE - 1,
485 .flags = IORESOURCE_MEM,
486 },
487#endif
488};
489
490static struct platform_device at91_lcdc_device = {
7776a94c 491 .name = "atmel_lcdfb",
86ad76bb
AV		 492 .id = 0,
493 .dev = {
494 .dma_mask = &lcdc_dmamask,
c6686ff9 495 .coherent_dma_mask = DMA_BIT_MASK(32),
86ad76bb
AV		 496 .platform_data = &lcdc_data,
497 },
498 .resource = lcdc_resources,
499 .num_resources = ARRAY_SIZE(lcdc_resources),
500};
501
7776a94c 502void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
86ad76bb
AV		 503{
504 if (!data) {
505 return;
506 }
507
f06e656f
AV		 508#if defined(CONFIG_FB_ATMEL_STN)
509 at91_set_A_periph(AT91_PIN_PB0, 0); /* LCDVSYNC */
510 at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */
511 at91_set_A_periph(AT91_PIN_PB2, 0); /* LCDDOTCK */
512 at91_set_A_periph(AT91_PIN_PB3, 0); /* LCDDEN */
513 at91_set_A_periph(AT91_PIN_PB4, 0); /* LCDCC */
514 at91_set_A_periph(AT91_PIN_PB5, 0); /* LCDD0 */
515 at91_set_A_periph(AT91_PIN_PB6, 0); /* LCDD1 */
516 at91_set_A_periph(AT91_PIN_PB7, 0); /* LCDD2 */
517 at91_set_A_periph(AT91_PIN_PB8, 0); /* LCDD3 */
518#else
86ad76bb
AV		 519 at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */
520 at91_set_A_periph(AT91_PIN_PB2, 0); /* LCDDOTCK */
521 at91_set_A_periph(AT91_PIN_PB3, 0); /* LCDDEN */
522 at91_set_A_periph(AT91_PIN_PB4, 0); /* LCDCC */
523 at91_set_A_periph(AT91_PIN_PB7, 0); /* LCDD2 */
524 at91_set_A_periph(AT91_PIN_PB8, 0); /* LCDD3 */
525 at91_set_A_periph(AT91_PIN_PB9, 0); /* LCDD4 */
526 at91_set_A_periph(AT91_PIN_PB10, 0); /* LCDD5 */
527 at91_set_A_periph(AT91_PIN_PB11, 0); /* LCDD6 */
528 at91_set_A_periph(AT91_PIN_PB12, 0); /* LCDD7 */
529 at91_set_A_periph(AT91_PIN_PB15, 0); /* LCDD10 */
530 at91_set_A_periph(AT91_PIN_PB16, 0); /* LCDD11 */
531 at91_set_A_periph(AT91_PIN_PB17, 0); /* LCDD12 */
532 at91_set_A_periph(AT91_PIN_PB18, 0); /* LCDD13 */
533 at91_set_A_periph(AT91_PIN_PB19, 0); /* LCDD14 */
534 at91_set_A_periph(AT91_PIN_PB20, 0); /* LCDD15 */
535 at91_set_B_periph(AT91_PIN_PB23, 0); /* LCDD18 */
536 at91_set_B_periph(AT91_PIN_PB24, 0); /* LCDD19 */
537 at91_set_B_periph(AT91_PIN_PB25, 0); /* LCDD20 */
538 at91_set_B_periph(AT91_PIN_PB26, 0); /* LCDD21 */
539 at91_set_B_periph(AT91_PIN_PB27, 0); /* LCDD22 */
540 at91_set_B_periph(AT91_PIN_PB28, 0); /* LCDD23 */
f06e656f 541#endif
86ad76bb 542
01d3a5e7
HS		 543 if (ARRAY_SIZE(lcdc_resources) > 2) {
544 void __iomem *fb;
545 struct resource *fb_res = &lcdc_resources[2];
28f65c11 546 size_t fb_len = resource_size(fb_res);
01d3a5e7 547
90898709 548 fb = ioremap(fb_res->start, fb_len);
01d3a5e7
HS		 549 if (fb) {
550 memset(fb, 0, fb_len);
90898709 551 iounmap(fb);
01d3a5e7
HS		 552 }
553 }
86ad76bb
AV		 554 lcdc_data = *data;
555 platform_device_register(&at91_lcdc_device);
556}
557#else
7776a94c 558void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
86ad76bb
AV		 559#endif
560
561
e5f40bfa
AV		 562/* --------------------------------------------------------------------
563 * Timer/Counter block
564 * -------------------------------------------------------------------- */
565
566#ifdef CONFIG_ATMEL_TCLIB
567
568static struct resource tcb_resources[] = {
569 [0] = {
570 .start = AT91SAM9261_BASE_TCB0,
571 .end = AT91SAM9261_BASE_TCB0 + SZ_16K - 1,
572 .flags = IORESOURCE_MEM,
573 },
574 [1] = {
8fe82a55
LD		 575 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_TC0,
576 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_TC0,
e5f40bfa
AV		 577 .flags = IORESOURCE_IRQ,
578 },
579 [2] = {
8fe82a55
LD		 580 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_TC1,
581 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_TC1,
e5f40bfa
AV		 582 .flags = IORESOURCE_IRQ,
583 },
584 [3] = {
8fe82a55
LD		 585 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_TC2,
586 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_TC2,
e5f40bfa
AV		 587 .flags = IORESOURCE_IRQ,
588 },
589};
590
591static struct platform_device at91sam9261_tcb_device = {
592 .name = "atmel_tcb",
593 .id = 0,
594 .resource = tcb_resources,
595 .num_resources = ARRAY_SIZE(tcb_resources),
596};
597
598static void __init at91_add_device_tc(void)
599{
e5f40bfa
AV		 600 platform_device_register(&at91sam9261_tcb_device);
601}
602#else
603static void __init at91_add_device_tc(void) { }
604#endif
605
606
884f5a6a
AV		 607/* --------------------------------------------------------------------
608 * RTT
609 * -------------------------------------------------------------------- */
610
611static struct resource rtt_resources[] = {
612 {
eab5fd67
JCPV		 613 .start = AT91SAM9261_BASE_RTT,
614 .end = AT91SAM9261_BASE_RTT + SZ_16 - 1,
884f5a6a 615 .flags = IORESOURCE_MEM,
b3af8b49
JCPV		 616 }, {
617 .flags = IORESOURCE_MEM,
e402af6c
LD		 618 }, {
619 .flags = IORESOURCE_IRQ,
884f5a6a
AV		 620 }
621};
622
623static struct platform_device at91sam9261_rtt_device = {
624 .name = "at91_rtt",
4fd9212c 625 .id = 0,
884f5a6a 626 .resource = rtt_resources,
884f5a6a
AV		 627};
628
205056a3
JCPV		 629#if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
630static void __init at91_add_device_rtt_rtc(void)
631{
632 at91sam9261_rtt_device.name = "rtc-at91sam9";
b3af8b49
JCPV		 633 /*
634 * The second resource is needed:
635 * GPBR will serve as the storage for RTC time offset
636 */
e402af6c 637 at91sam9261_rtt_device.num_resources = 3;
b3af8b49
JCPV		 638 rtt_resources[1].start = AT91SAM9261_BASE_GPBR +
639 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
640 rtt_resources[1].end = rtt_resources[1].start + 3;
e402af6c
LD		 641 rtt_resources[2].start = NR_IRQS_LEGACY + AT91_ID_SYS;
642 rtt_resources[2].end = NR_IRQS_LEGACY + AT91_ID_SYS;
205056a3
JCPV		 643}
644#else
b3af8b49
JCPV		 645static void __init at91_add_device_rtt_rtc(void)
646{
647 /* Only one resource is needed: RTT not used as RTC */
648 at91sam9261_rtt_device.num_resources = 1;
649}
205056a3
JCPV		 650#endif
651
884f5a6a
AV		 652static void __init at91_add_device_rtt(void)
653{
205056a3 654 at91_add_device_rtt_rtc();
884f5a6a
AV		 655 platform_device_register(&at91sam9261_rtt_device);
656}
657
658
659/* --------------------------------------------------------------------
660 * Watchdog
661 * -------------------------------------------------------------------- */
662
2af29b78 663#if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
c1c30a29
JCPV		 664static struct resource wdt_resources[] = {
665 {
666 .start = AT91SAM9261_BASE_WDT,
667 .end = AT91SAM9261_BASE_WDT + SZ_16 - 1,
668 .flags = IORESOURCE_MEM,
669 }
670};
671
884f5a6a
AV		 672static struct platform_device at91sam9261_wdt_device = {
673 .name = "at91_wdt",
674 .id = -1,
c1c30a29
JCPV		 675 .resource = wdt_resources,
676 .num_resources = ARRAY_SIZE(wdt_resources),
884f5a6a
AV		 677};
678
679static void __init at91_add_device_watchdog(void)
680{
681 platform_device_register(&at91sam9261_wdt_device);
682}
683#else
684static void __init at91_add_device_watchdog(void) {}
685#endif
686
687
bfbc3266
AV		 688/* --------------------------------------------------------------------
689 * SSC -- Synchronous Serial Controller
690 * -------------------------------------------------------------------- */
691
692#if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
693static u64 ssc0_dmamask = DMA_BIT_MASK(32);
694
695static struct resource ssc0_resources[] = {
696 [0] = {
697 .start = AT91SAM9261_BASE_SSC0,
698 .end = AT91SAM9261_BASE_SSC0 + SZ_16K - 1,
699 .flags = IORESOURCE_MEM,
700 },
701 [1] = {
8fe82a55
LD		 702 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_SSC0,
703 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_SSC0,
bfbc3266
AV		 704 .flags = IORESOURCE_IRQ,
705 },
706};
707
708static struct platform_device at91sam9261_ssc0_device = {
636036d2 709 .name = "at91rm9200_ssc",
bfbc3266
AV		 710 .id = 0,
711 .dev = {
712 .dma_mask = &ssc0_dmamask,
713 .coherent_dma_mask = DMA_BIT_MASK(32),
714 },
715 .resource = ssc0_resources,
716 .num_resources = ARRAY_SIZE(ssc0_resources),
717};
718
719static inline void configure_ssc0_pins(unsigned pins)
720{
721 if (pins & ATMEL_SSC_TF)
722 at91_set_A_periph(AT91_PIN_PB21, 1);
723 if (pins & ATMEL_SSC_TK)
724 at91_set_A_periph(AT91_PIN_PB22, 1);
725 if (pins & ATMEL_SSC_TD)
726 at91_set_A_periph(AT91_PIN_PB23, 1);
727 if (pins & ATMEL_SSC_RD)
728 at91_set_A_periph(AT91_PIN_PB24, 1);
729 if (pins & ATMEL_SSC_RK)
730 at91_set_A_periph(AT91_PIN_PB25, 1);
731 if (pins & ATMEL_SSC_RF)
732 at91_set_A_periph(AT91_PIN_PB26, 1);
733}
734
735static u64 ssc1_dmamask = DMA_BIT_MASK(32);
736
737static struct resource ssc1_resources[] = {
738 [0] = {
739 .start = AT91SAM9261_BASE_SSC1,
740 .end = AT91SAM9261_BASE_SSC1 + SZ_16K - 1,
741 .flags = IORESOURCE_MEM,
742 },
743 [1] = {
8fe82a55
LD		 744 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_SSC1,
745 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_SSC1,
bfbc3266
AV		 746 .flags = IORESOURCE_IRQ,
747 },
748};
749
750static struct platform_device at91sam9261_ssc1_device = {
636036d2 751 .name = "at91rm9200_ssc",
bfbc3266
AV		 752 .id = 1,
753 .dev = {
754 .dma_mask = &ssc1_dmamask,
755 .coherent_dma_mask = DMA_BIT_MASK(32),
756 },
757 .resource = ssc1_resources,
758 .num_resources = ARRAY_SIZE(ssc1_resources),
759};
760
761static inline void configure_ssc1_pins(unsigned pins)
762{
763 if (pins & ATMEL_SSC_TF)
764 at91_set_B_periph(AT91_PIN_PA17, 1);
765 if (pins & ATMEL_SSC_TK)
766 at91_set_B_periph(AT91_PIN_PA18, 1);
767 if (pins & ATMEL_SSC_TD)
768 at91_set_B_periph(AT91_PIN_PA19, 1);
769 if (pins & ATMEL_SSC_RD)
770 at91_set_B_periph(AT91_PIN_PA20, 1);
771 if (pins & ATMEL_SSC_RK)
772 at91_set_B_periph(AT91_PIN_PA21, 1);
773 if (pins & ATMEL_SSC_RF)
774 at91_set_B_periph(AT91_PIN_PA22, 1);
775}
776
777static u64 ssc2_dmamask = DMA_BIT_MASK(32);
778
779static struct resource ssc2_resources[] = {
780 [0] = {
781 .start = AT91SAM9261_BASE_SSC2,
782 .end = AT91SAM9261_BASE_SSC2 + SZ_16K - 1,
783 .flags = IORESOURCE_MEM,
784 },
785 [1] = {
8fe82a55
LD		 786 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_SSC2,
787 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_SSC2,
bfbc3266
AV		 788 .flags = IORESOURCE_IRQ,
789 },
790};
791
792static struct platform_device at91sam9261_ssc2_device = {
636036d2 793 .name = "at91rm9200_ssc",
bfbc3266
AV		 794 .id = 2,
795 .dev = {
796 .dma_mask = &ssc2_dmamask,
797 .coherent_dma_mask = DMA_BIT_MASK(32),
798 },
799 .resource = ssc2_resources,
800 .num_resources = ARRAY_SIZE(ssc2_resources),
801};
802
803static inline void configure_ssc2_pins(unsigned pins)
804{
805 if (pins & ATMEL_SSC_TF)
806 at91_set_B_periph(AT91_PIN_PC25, 1);
807 if (pins & ATMEL_SSC_TK)
808 at91_set_B_periph(AT91_PIN_PC26, 1);
809 if (pins & ATMEL_SSC_TD)
810 at91_set_B_periph(AT91_PIN_PC27, 1);
811 if (pins & ATMEL_SSC_RD)
812 at91_set_B_periph(AT91_PIN_PC28, 1);
813 if (pins & ATMEL_SSC_RK)
814 at91_set_B_periph(AT91_PIN_PC29, 1);
815 if (pins & ATMEL_SSC_RF)
816 at91_set_B_periph(AT91_PIN_PC30, 1);
817}
818
819/*
820 * SSC controllers are accessed through library code, instead of any
821 * kind of all-singing/all-dancing driver. For example one could be
822 * used by a particular I2S audio codec's driver, while another one
823 * on the same system might be used by a custom data capture driver.
824 */
825void __init at91_add_device_ssc(unsigned id, unsigned pins)
826{
827 struct platform_device *pdev;
828
829 /*
830 * NOTE: caller is responsible for passing information matching
831 * "pins" to whatever will be using each particular controller.
832 */
833 switch (id) {
834 case AT91SAM9261_ID_SSC0:
835 pdev = &at91sam9261_ssc0_device;
836 configure_ssc0_pins(pins);
bfbc3266
AV		 837 break;
838 case AT91SAM9261_ID_SSC1:
839 pdev = &at91sam9261_ssc1_device;
840 configure_ssc1_pins(pins);
bfbc3266
AV		 841 break;
842 case AT91SAM9261_ID_SSC2:
843 pdev = &at91sam9261_ssc2_device;
844 configure_ssc2_pins(pins);
bfbc3266
AV		 845 break;
846 default:
847 return;
848 }
849
850 platform_device_register(pdev);
851}
852
853#else
854void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
855#endif
856
857
86ad76bb
AV		 858/* --------------------------------------------------------------------
859 * UART
860 * -------------------------------------------------------------------- */
861
862#if defined(CONFIG_SERIAL_ATMEL)
863static struct resource dbgu_resources[] = {
864 [0] = {
13079a73
JCPV		 865 .start = AT91SAM9261_BASE_DBGU,
866 .end = AT91SAM9261_BASE_DBGU + SZ_512 - 1,
86ad76bb
AV		 867 .flags = IORESOURCE_MEM,
868 },
869 [1] = {
8fe82a55
LD		 870 .start = NR_IRQS_LEGACY + AT91_ID_SYS,
871 .end = NR_IRQS_LEGACY + AT91_ID_SYS,
86ad76bb
AV		 872 .flags = IORESOURCE_IRQ,
873 },
874};
875
876static struct atmel_uart_data dbgu_data = {
877 .use_dma_tx = 0,
878 .use_dma_rx = 0, /* DBGU not capable of receive DMA */
86ad76bb
AV		 879};
880
c6686ff9
AV		 881static u64 dbgu_dmamask = DMA_BIT_MASK(32);
882
86ad76bb
AV		 883static struct platform_device at91sam9261_dbgu_device = {
884 .name = "atmel_usart",
885 .id = 0,
886 .dev = {
c6686ff9
AV		 887 .dma_mask = &dbgu_dmamask,
888 .coherent_dma_mask = DMA_BIT_MASK(32),
889 .platform_data = &dbgu_data,
86ad76bb
AV		 890 },
891 .resource = dbgu_resources,
892 .num_resources = ARRAY_SIZE(dbgu_resources),
893};
894
895static inline void configure_dbgu_pins(void)
896{
897 at91_set_A_periph(AT91_PIN_PA9, 0); /* DRXD */
898 at91_set_A_periph(AT91_PIN_PA10, 1); /* DTXD */
899}
900
901static struct resource uart0_resources[] = {
902 [0] = {
903 .start = AT91SAM9261_BASE_US0,
904 .end = AT91SAM9261_BASE_US0 + SZ_16K - 1,
905 .flags = IORESOURCE_MEM,
906 },
907 [1] = {
8fe82a55
LD		 908 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_US0,
909 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_US0,
86ad76bb
AV		 910 .flags = IORESOURCE_IRQ,
911 },
912};
913
914static struct atmel_uart_data uart0_data = {
915 .use_dma_tx = 1,
916 .use_dma_rx = 1,
917};
918
c6686ff9
AV		 919static u64 uart0_dmamask = DMA_BIT_MASK(32);
920
86ad76bb
AV		 921static struct platform_device at91sam9261_uart0_device = {
922 .name = "atmel_usart",
923 .id = 1,
924 .dev = {
c6686ff9
AV		 925 .dma_mask = &uart0_dmamask,
926 .coherent_dma_mask = DMA_BIT_MASK(32),
927 .platform_data = &uart0_data,
86ad76bb
AV		 928 },
929 .resource = uart0_resources,
930 .num_resources = ARRAY_SIZE(uart0_resources),
931};
932
c8f385a6 933static inline void configure_usart0_pins(unsigned pins)
86ad76bb
AV		 934{
935 at91_set_A_periph(AT91_PIN_PC8, 1); /* TXD0 */
936 at91_set_A_periph(AT91_PIN_PC9, 0); /* RXD0 */
c8f385a6
AV		 937
938 if (pins & ATMEL_UART_RTS)
939 at91_set_A_periph(AT91_PIN_PC10, 0); /* RTS0 */
940 if (pins & ATMEL_UART_CTS)
941 at91_set_A_periph(AT91_PIN_PC11, 0); /* CTS0 */
86ad76bb
AV		 942}
943
944static struct resource uart1_resources[] = {
945 [0] = {
946 .start = AT91SAM9261_BASE_US1,
947 .end = AT91SAM9261_BASE_US1 + SZ_16K - 1,
948 .flags = IORESOURCE_MEM,
949 },
950 [1] = {
8fe82a55
LD		 951 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_US1,
952 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_US1,
86ad76bb
AV		 953 .flags = IORESOURCE_IRQ,
954 },
955};
956
957static struct atmel_uart_data uart1_data = {
958 .use_dma_tx = 1,
959 .use_dma_rx = 1,
960};
961
c6686ff9
AV		 962static u64 uart1_dmamask = DMA_BIT_MASK(32);
963
86ad76bb
AV		 964static struct platform_device at91sam9261_uart1_device = {
965 .name = "atmel_usart",
966 .id = 2,
967 .dev = {
c6686ff9
AV		 968 .dma_mask = &uart1_dmamask,
969 .coherent_dma_mask = DMA_BIT_MASK(32),
970 .platform_data = &uart1_data,
86ad76bb
AV		 971 },
972 .resource = uart1_resources,
973 .num_resources = ARRAY_SIZE(uart1_resources),
974};
975
c8f385a6 976static inline void configure_usart1_pins(unsigned pins)
86ad76bb
AV		 977{
978 at91_set_A_periph(AT91_PIN_PC12, 1); /* TXD1 */
979 at91_set_A_periph(AT91_PIN_PC13, 0); /* RXD1 */
c8f385a6
AV		 980
981 if (pins & ATMEL_UART_RTS)
982 at91_set_B_periph(AT91_PIN_PA12, 0); /* RTS1 */
983 if (pins & ATMEL_UART_CTS)
984 at91_set_B_periph(AT91_PIN_PA13, 0); /* CTS1 */
86ad76bb
AV		 985}
986
987static struct resource uart2_resources[] = {
988 [0] = {
989 .start = AT91SAM9261_BASE_US2,
990 .end = AT91SAM9261_BASE_US2 + SZ_16K - 1,
991 .flags = IORESOURCE_MEM,
992 },
993 [1] = {
8fe82a55
LD		 994 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_US2,
995 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_US2,
86ad76bb
AV		 996 .flags = IORESOURCE_IRQ,
997 },
998};
999
1000static struct atmel_uart_data uart2_data = {
1001 .use_dma_tx = 1,
1002 .use_dma_rx = 1,
1003};
1004
c6686ff9
AV		 1005static u64 uart2_dmamask = DMA_BIT_MASK(32);
1006
86ad76bb
AV		 1007static struct platform_device at91sam9261_uart2_device = {
1008 .name = "atmel_usart",
1009 .id = 3,
1010 .dev = {
c6686ff9
AV		 1011 .dma_mask = &uart2_dmamask,
1012 .coherent_dma_mask = DMA_BIT_MASK(32),
1013 .platform_data = &uart2_data,
86ad76bb
AV		 1014 },
1015 .resource = uart2_resources,
1016 .num_resources = ARRAY_SIZE(uart2_resources),
1017};
1018
c8f385a6 1019static inline void configure_usart2_pins(unsigned pins)
86ad76bb
AV		 1020{
1021 at91_set_A_periph(AT91_PIN_PC15, 0); /* RXD2 */
1022 at91_set_A_periph(AT91_PIN_PC14, 1); /* TXD2 */
c8f385a6
AV		 1023
1024 if (pins & ATMEL_UART_RTS)
1025 at91_set_B_periph(AT91_PIN_PA15, 0); /* RTS2*/
1026 if (pins & ATMEL_UART_CTS)
1027 at91_set_B_periph(AT91_PIN_PA16, 0); /* CTS2 */
86ad76bb
AV		 1028}
1029
11aadac4 1030static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
86ad76bb 1031
c8f385a6
AV		 1032void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1033{
1034 struct platform_device *pdev;
2b348e2f 1035 struct atmel_uart_data *pdata;
c8f385a6
AV		 1036
1037 switch (id) {
1038 case 0: /* DBGU */
1039 pdev = &at91sam9261_dbgu_device;
1040 configure_dbgu_pins();
c8f385a6
AV		 1041 break;
1042 case AT91SAM9261_ID_US0:
1043 pdev = &at91sam9261_uart0_device;
1044 configure_usart0_pins(pins);
c8f385a6
AV		 1045 break;
1046 case AT91SAM9261_ID_US1:
1047 pdev = &at91sam9261_uart1_device;
1048 configure_usart1_pins(pins);
c8f385a6
AV		 1049 break;
1050 case AT91SAM9261_ID_US2:
1051 pdev = &at91sam9261_uart2_device;
1052 configure_usart2_pins(pins);
c8f385a6
AV		 1053 break;
1054 default:
1055 return;
1056 }
2b348e2f
JCPV		 1057 pdata = pdev->dev.platform_data;
1058 pdata->num = portnr; /* update to mapped ID */
c8f385a6
AV		 1059
1060 if (portnr < ATMEL_MAX_UART)
1061 at91_uarts[portnr] = pdev;
1062}
1063
86ad76bb
AV		 1064void __init at91_add_device_serial(void)
1065{
1066 int i;
1067
1068 for (i = 0; i < ATMEL_MAX_UART; i++) {
1069 if (at91_uarts[i])
1070 platform_device_register(at91_uarts[i]);
1071 }
1072}
1073#else
c8f385a6 1074void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
86ad76bb
AV		 1075void __init at91_add_device_serial(void) {}
1076#endif
1077
1078
1079/* -------------------------------------------------------------------- */
1080
1081/*
1082 * These devices are always present and don't need any board-specific
1083 * setup.
1084 */
1085static int __init at91_add_standard_devices(void)
1086{
884f5a6a
AV		 1087 at91_add_device_rtt();
1088 at91_add_device_watchdog();
e5f40bfa 1089 at91_add_device_tc();
86ad76bb
AV		 1090 return 0;
1091}
1092
1093arch_initcall(at91_add_standard_devices);
Linux kernel - Deliverables
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