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Merge tag 'timer' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
[deliverable/linux.git] / arch / arm / mach-at91 / at91sam9261_devices.c
CommitLineData
86ad76bb 1/*
9d041268 2 * arch/arm/mach-at91/at91sam9261_devices.c
86ad76bb
AV		 3 *
4 * Copyright (C) 2005 Thibaut VARENE <varenet@parisc-linux.org>
5 * Copyright (C) 2005 David Brownell
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 */
13#include <asm/mach/arch.h>
14#include <asm/mach/map.h>
15
c6686ff9 16#include <linux/dma-mapping.h>
2f8163ba 17#include <linux/gpio.h>
86ad76bb 18#include <linux/platform_device.h>
f230d3f5 19#include <linux/i2c-gpio.h>
86ad76bb 20
f230d3f5 21#include <linux/fb.h>
b8b78609
JA		 22#include <video/atmel_lcdc.h>
23
a09e64fb 24#include <mach/board.h>
a09e64fb
RK		 25#include <mach/at91sam9261.h>
26#include <mach/at91sam9261_matrix.h>
4342d647 27#include <mach/at91_matrix.h>
a09e64fb 28#include <mach/at91sam9_smc.h>
86ad76bb
AV		 29
30#include "generic.h"
31
86ad76bb
AV		 32
33/* --------------------------------------------------------------------
34 * USB Host
35 * -------------------------------------------------------------------- */
36
37#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
c6686ff9 38static u64 ohci_dmamask = DMA_BIT_MASK(32);
86ad76bb
AV		 39static struct at91_usbh_data usbh_data;
40
41static struct resource usbh_resources[] = {
42 [0] = {
43 .start = AT91SAM9261_UHP_BASE,
44 .end = AT91SAM9261_UHP_BASE + SZ_1M - 1,
45 .flags = IORESOURCE_MEM,
46 },
47 [1] = {
8fe82a55
LD		 48 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_UHP,
49 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_UHP,
86ad76bb
AV		 50 .flags = IORESOURCE_IRQ,
51 },
52};
53
54static struct platform_device at91sam9261_usbh_device = {
55 .name = "at91_ohci",
56 .id = -1,
57 .dev = {
58 .dma_mask = &ohci_dmamask,
c6686ff9 59 .coherent_dma_mask = DMA_BIT_MASK(32),
86ad76bb
AV		 60 .platform_data = &usbh_data,
61 },
62 .resource = usbh_resources,
63 .num_resources = ARRAY_SIZE(usbh_resources),
64};
65
66void __init at91_add_device_usbh(struct at91_usbh_data *data)
67{
1fcaea7e
TP		 68 int i;
69
86ad76bb
AV		 70 if (!data)
71 return;
72
1fcaea7e
TP		 73 /* Enable overcurrent notification */
74 for (i = 0; i < data->ports; i++) {
75 if (data->overcurrent_pin[i])
76 at91_set_gpio_input(data->overcurrent_pin[i], 1);
77 }
78
86ad76bb
AV		 79 usbh_data = *data;
80 platform_device_register(&at91sam9261_usbh_device);
81}
82#else
83void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
84#endif
85
86
87/* --------------------------------------------------------------------
88 * USB Device (Gadget)
89 * -------------------------------------------------------------------- */
90
e8c9dc93 91#if defined(CONFIG_USB_AT91) || defined(CONFIG_USB_AT91_MODULE)
86ad76bb
AV		 92static struct at91_udc_data udc_data;
93
94static struct resource udc_resources[] = {
95 [0] = {
96 .start = AT91SAM9261_BASE_UDP,
97 .end = AT91SAM9261_BASE_UDP + SZ_16K - 1,
98 .flags = IORESOURCE_MEM,
99 },
100 [1] = {
8fe82a55
LD		 101 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_UDP,
102 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_UDP,
86ad76bb
AV		 103 .flags = IORESOURCE_IRQ,
104 },
105};
106
107static struct platform_device at91sam9261_udc_device = {
108 .name = "at91_udc",
109 .id = -1,
110 .dev = {
111 .platform_data = &udc_data,
112 },
113 .resource = udc_resources,
114 .num_resources = ARRAY_SIZE(udc_resources),
115};
116
117void __init at91_add_device_udc(struct at91_udc_data *data)
118{
86ad76bb
AV		 119 if (!data)
120 return;
121
cc9f9aef 122 if (gpio_is_valid(data->vbus_pin)) {
86ad76bb
AV		 123 at91_set_gpio_input(data->vbus_pin, 0);
124 at91_set_deglitch(data->vbus_pin, 1);
125 }
126
da7a42d6 127 /* Pullup pin is handled internally by USB device peripheral */
86ad76bb
AV		 128
129 udc_data = *data;
130 platform_device_register(&at91sam9261_udc_device);
131}
132#else
133void __init at91_add_device_udc(struct at91_udc_data *data) {}
134#endif
135
136/* --------------------------------------------------------------------
137 * MMC / SD
138 * -------------------------------------------------------------------- */
139
140#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
c6686ff9 141static u64 mmc_dmamask = DMA_BIT_MASK(32);
86ad76bb
AV		 142static struct at91_mmc_data mmc_data;
143
144static struct resource mmc_resources[] = {
145 [0] = {
146 .start = AT91SAM9261_BASE_MCI,
147 .end = AT91SAM9261_BASE_MCI + SZ_16K - 1,
148 .flags = IORESOURCE_MEM,
149 },
150 [1] = {
8fe82a55
LD		 151 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_MCI,
152 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_MCI,
86ad76bb
AV		 153 .flags = IORESOURCE_IRQ,
154 },
155};
156
157static struct platform_device at91sam9261_mmc_device = {
158 .name = "at91_mci",
159 .id = -1,
160 .dev = {
161 .dma_mask = &mmc_dmamask,
c6686ff9 162 .coherent_dma_mask = DMA_BIT_MASK(32),
86ad76bb
AV		 163 .platform_data = &mmc_data,
164 },
165 .resource = mmc_resources,
166 .num_resources = ARRAY_SIZE(mmc_resources),
167};
168
d0760b3b 169void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
86ad76bb
AV		 170{
171 if (!data)
172 return;
173
174 /* input/irq */
cc9f9aef 175 if (gpio_is_valid(data->det_pin)) {
86ad76bb
AV		 176 at91_set_gpio_input(data->det_pin, 1);
177 at91_set_deglitch(data->det_pin, 1);
178 }
cc9f9aef 179 if (gpio_is_valid(data->wp_pin))
86ad76bb 180 at91_set_gpio_input(data->wp_pin, 1);
cc9f9aef 181 if (gpio_is_valid(data->vcc_pin))
86ad76bb
AV		 182 at91_set_gpio_output(data->vcc_pin, 0);
183
184 /* CLK */
185 at91_set_B_periph(AT91_PIN_PA2, 0);
186
187 /* CMD */
188 at91_set_B_periph(AT91_PIN_PA1, 1);
189
190 /* DAT0, maybe DAT1..DAT3 */
191 at91_set_B_periph(AT91_PIN_PA0, 1);
192 if (data->wire4) {
193 at91_set_B_periph(AT91_PIN_PA4, 1);
194 at91_set_B_periph(AT91_PIN_PA5, 1);
195 at91_set_B_periph(AT91_PIN_PA6, 1);
196 }
197
198 mmc_data = *data;
199 platform_device_register(&at91sam9261_mmc_device);
200}
201#else
d0760b3b 202void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
86ad76bb
AV		 203#endif
204
205
206/* --------------------------------------------------------------------
207 * NAND / SmartMedia
208 * -------------------------------------------------------------------- */
209
f6ed6f78 210#if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
3c3796cc 211static struct atmel_nand_data nand_data;
86ad76bb
AV		 212
213#define NAND_BASE AT91_CHIPSELECT_3
214
215static struct resource nand_resources[] = {
216 {
217 .start = NAND_BASE,
218 .end = NAND_BASE + SZ_256M - 1,
219 .flags = IORESOURCE_MEM,
220 }
221};
222
3c3796cc
HS		 223static struct platform_device atmel_nand_device = {
224 .name = "atmel_nand",
86ad76bb
AV		 225 .id = -1,
226 .dev = {
227 .platform_data = &nand_data,
228 },
229 .resource = nand_resources,
230 .num_resources = ARRAY_SIZE(nand_resources),
231};
232
3c3796cc 233void __init at91_add_device_nand(struct atmel_nand_data *data)
86ad76bb 234{
461d3b4d 235 unsigned long csa;
86ad76bb
AV		 236
237 if (!data)
238 return;
239
4342d647
JCPV		 240 csa = at91_matrix_read(AT91_MATRIX_EBICSA);
241 at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
86ad76bb 242
86ad76bb 243 /* enable pin */
cc9f9aef 244 if (gpio_is_valid(data->enable_pin))
86ad76bb
AV		 245 at91_set_gpio_output(data->enable_pin, 1);
246
247 /* ready/busy pin */
cc9f9aef 248 if (gpio_is_valid(data->rdy_pin))
86ad76bb
AV		 249 at91_set_gpio_input(data->rdy_pin, 1);
250
251 /* card detect pin */
cc9f9aef 252 if (gpio_is_valid(data->det_pin))
86ad76bb
AV		 253 at91_set_gpio_input(data->det_pin, 1);
254
255 at91_set_A_periph(AT91_PIN_PC0, 0); /* NANDOE */
256 at91_set_A_periph(AT91_PIN_PC1, 0); /* NANDWE */
257
258 nand_data = *data;
3c3796cc 259 platform_device_register(&atmel_nand_device);
86ad76bb
AV		 260}
261
262#else
3c3796cc 263void __init at91_add_device_nand(struct atmel_nand_data *data) {}
86ad76bb
AV		 264#endif
265
266
267/* --------------------------------------------------------------------
268 * TWI (i2c)
269 * -------------------------------------------------------------------- */
270
f230d3f5
AV		 271/*
272 * Prefer the GPIO code since the TWI controller isn't robust
273 * (gets overruns and underruns under load) and can only issue
274 * repeated STARTs in one scenario (the driver doesn't yet handle them).
275 */
276#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
277
278static struct i2c_gpio_platform_data pdata = {
279 .sda_pin = AT91_PIN_PA7,
280 .sda_is_open_drain = 1,
281 .scl_pin = AT91_PIN_PA8,
282 .scl_is_open_drain = 1,
283 .udelay = 2, /* ~100 kHz */
284};
285
286static struct platform_device at91sam9261_twi_device = {
287 .name = "i2c-gpio",
288 .id = -1,
289 .dev.platform_data = &pdata,
290};
291
292void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
293{
294 at91_set_GPIO_periph(AT91_PIN_PA7, 1); /* TWD (SDA) */
295 at91_set_multi_drive(AT91_PIN_PA7, 1);
296
297 at91_set_GPIO_periph(AT91_PIN_PA8, 1); /* TWCK (SCL) */
298 at91_set_multi_drive(AT91_PIN_PA8, 1);
299
300 i2c_register_board_info(0, devices, nr_devices);
301 platform_device_register(&at91sam9261_twi_device);
302}
303
304#elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
86ad76bb
AV		 305
306static struct resource twi_resources[] = {
307 [0] = {
308 .start = AT91SAM9261_BASE_TWI,
309 .end = AT91SAM9261_BASE_TWI + SZ_16K - 1,
310 .flags = IORESOURCE_MEM,
311 },
312 [1] = {
8fe82a55
LD		 313 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_TWI,
314 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_TWI,
86ad76bb
AV		 315 .flags = IORESOURCE_IRQ,
316 },
317};
318
319static struct platform_device at91sam9261_twi_device = {
320 .name = "at91_i2c",
321 .id = -1,
322 .resource = twi_resources,
323 .num_resources = ARRAY_SIZE(twi_resources),
324};
325
f230d3f5 326void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
86ad76bb
AV		 327{
328 /* pins used for TWI interface */
329 at91_set_A_periph(AT91_PIN_PA7, 0); /* TWD */
330 at91_set_multi_drive(AT91_PIN_PA7, 1);
331
332 at91_set_A_periph(AT91_PIN_PA8, 0); /* TWCK */
333 at91_set_multi_drive(AT91_PIN_PA8, 1);
334
f230d3f5 335 i2c_register_board_info(0, devices, nr_devices);
86ad76bb
AV		 336 platform_device_register(&at91sam9261_twi_device);
337}
338#else
f230d3f5 339void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
86ad76bb
AV		 340#endif
341
342
343/* --------------------------------------------------------------------
344 * SPI
345 * -------------------------------------------------------------------- */
346
347#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
c6686ff9 348static u64 spi_dmamask = DMA_BIT_MASK(32);
86ad76bb
AV		 349
350static struct resource spi0_resources[] = {
351 [0] = {
352 .start = AT91SAM9261_BASE_SPI0,
353 .end = AT91SAM9261_BASE_SPI0 + SZ_16K - 1,
354 .flags = IORESOURCE_MEM,
355 },
356 [1] = {
8fe82a55
LD		 357 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_SPI0,
358 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_SPI0,
86ad76bb
AV		 359 .flags = IORESOURCE_IRQ,
360 },
361};
362
363static struct platform_device at91sam9261_spi0_device = {
364 .name = "atmel_spi",
365 .id = 0,
366 .dev = {
367 .dma_mask = &spi_dmamask,
c6686ff9 368 .coherent_dma_mask = DMA_BIT_MASK(32),
86ad76bb
AV		 369 },
370 .resource = spi0_resources,
371 .num_resources = ARRAY_SIZE(spi0_resources),
372};
373
374static const unsigned spi0_standard_cs[4] = { AT91_PIN_PA3, AT91_PIN_PA4, AT91_PIN_PA5, AT91_PIN_PA6 };
375
376static struct resource spi1_resources[] = {
377 [0] = {
378 .start = AT91SAM9261_BASE_SPI1,
379 .end = AT91SAM9261_BASE_SPI1 + SZ_16K - 1,
380 .flags = IORESOURCE_MEM,
381 },
382 [1] = {
8fe82a55
LD		 383 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_SPI1,
384 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_SPI1,
86ad76bb
AV		 385 .flags = IORESOURCE_IRQ,
386 },
387};
388
389static struct platform_device at91sam9261_spi1_device = {
390 .name = "atmel_spi",
391 .id = 1,
392 .dev = {
393 .dma_mask = &spi_dmamask,
c6686ff9 394 .coherent_dma_mask = DMA_BIT_MASK(32),
86ad76bb
AV		 395 },
396 .resource = spi1_resources,
397 .num_resources = ARRAY_SIZE(spi1_resources),
398};
399
400static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB28, AT91_PIN_PA24, AT91_PIN_PA25, AT91_PIN_PA26 };
401
402void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
403{
404 int i;
405 unsigned long cs_pin;
406 short enable_spi0 = 0;
407 short enable_spi1 = 0;
408
409 /* Choose SPI chip-selects */
410 for (i = 0; i < nr_devices; i++) {
411 if (devices[i].controller_data)
412 cs_pin = (unsigned long) devices[i].controller_data;
413 else if (devices[i].bus_num == 0)
414 cs_pin = spi0_standard_cs[devices[i].chip_select];
415 else
416 cs_pin = spi1_standard_cs[devices[i].chip_select];
417
0c2c1f62
NF		 418 if (!gpio_is_valid(cs_pin))
419 continue;
420
86ad76bb
AV		 421 if (devices[i].bus_num == 0)
422 enable_spi0 = 1;
423 else
424 enable_spi1 = 1;
425
426 /* enable chip-select pin */
427 at91_set_gpio_output(cs_pin, 1);
428
429 /* pass chip-select pin to driver */
430 devices[i].controller_data = (void *) cs_pin;
431 }
432
433 spi_register_board_info(devices, nr_devices);
434
435 /* Configure SPI bus(es) */
436 if (enable_spi0) {
437 at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
438 at91_set_A_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
439 at91_set_A_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */
440
86ad76bb
AV		 441 platform_device_register(&at91sam9261_spi0_device);
442 }
443 if (enable_spi1) {
444 at91_set_A_periph(AT91_PIN_PB30, 0); /* SPI1_MISO */
445 at91_set_A_periph(AT91_PIN_PB31, 0); /* SPI1_MOSI */
446 at91_set_A_periph(AT91_PIN_PB29, 0); /* SPI1_SPCK */
447
86ad76bb
AV		 448 platform_device_register(&at91sam9261_spi1_device);
449 }
450}
451#else
452void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
453#endif
454
455
456/* --------------------------------------------------------------------
457 * LCD Controller
458 * -------------------------------------------------------------------- */
459
7776a94c 460#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
c6686ff9 461static u64 lcdc_dmamask = DMA_BIT_MASK(32);
7776a94c 462static struct atmel_lcdfb_info lcdc_data;
86ad76bb
AV		 463
464static struct resource lcdc_resources[] = {
465 [0] = {
466 .start = AT91SAM9261_LCDC_BASE,
467 .end = AT91SAM9261_LCDC_BASE + SZ_4K - 1,
468 .flags = IORESOURCE_MEM,
469 },
470 [1] = {
8fe82a55
LD		 471 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_LCDC,
472 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_LCDC,
86ad76bb
AV		 473 .flags = IORESOURCE_IRQ,
474 },
475#if defined(CONFIG_FB_INTSRAM)
476 [2] = {
477 .start = AT91SAM9261_SRAM_BASE,
478 .end = AT91SAM9261_SRAM_BASE + AT91SAM9261_SRAM_SIZE - 1,
479 .flags = IORESOURCE_MEM,
480 },
481#endif
482};
483
484static struct platform_device at91_lcdc_device = {
7776a94c 485 .name = "atmel_lcdfb",
86ad76bb
AV		 486 .id = 0,
487 .dev = {
488 .dma_mask = &lcdc_dmamask,
c6686ff9 489 .coherent_dma_mask = DMA_BIT_MASK(32),
86ad76bb
AV		 490 .platform_data = &lcdc_data,
491 },
492 .resource = lcdc_resources,
493 .num_resources = ARRAY_SIZE(lcdc_resources),
494};
495
7776a94c 496void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
86ad76bb
AV		 497{
498 if (!data) {
499 return;
500 }
501
f06e656f
AV		 502#if defined(CONFIG_FB_ATMEL_STN)
503 at91_set_A_periph(AT91_PIN_PB0, 0); /* LCDVSYNC */
504 at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */
505 at91_set_A_periph(AT91_PIN_PB2, 0); /* LCDDOTCK */
506 at91_set_A_periph(AT91_PIN_PB3, 0); /* LCDDEN */
507 at91_set_A_periph(AT91_PIN_PB4, 0); /* LCDCC */
508 at91_set_A_periph(AT91_PIN_PB5, 0); /* LCDD0 */
509 at91_set_A_periph(AT91_PIN_PB6, 0); /* LCDD1 */
510 at91_set_A_periph(AT91_PIN_PB7, 0); /* LCDD2 */
511 at91_set_A_periph(AT91_PIN_PB8, 0); /* LCDD3 */
512#else
86ad76bb
AV		 513 at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */
514 at91_set_A_periph(AT91_PIN_PB2, 0); /* LCDDOTCK */
515 at91_set_A_periph(AT91_PIN_PB3, 0); /* LCDDEN */
516 at91_set_A_periph(AT91_PIN_PB4, 0); /* LCDCC */
517 at91_set_A_periph(AT91_PIN_PB7, 0); /* LCDD2 */
518 at91_set_A_periph(AT91_PIN_PB8, 0); /* LCDD3 */
519 at91_set_A_periph(AT91_PIN_PB9, 0); /* LCDD4 */
520 at91_set_A_periph(AT91_PIN_PB10, 0); /* LCDD5 */
521 at91_set_A_periph(AT91_PIN_PB11, 0); /* LCDD6 */
522 at91_set_A_periph(AT91_PIN_PB12, 0); /* LCDD7 */
523 at91_set_A_periph(AT91_PIN_PB15, 0); /* LCDD10 */
524 at91_set_A_periph(AT91_PIN_PB16, 0); /* LCDD11 */
525 at91_set_A_periph(AT91_PIN_PB17, 0); /* LCDD12 */
526 at91_set_A_periph(AT91_PIN_PB18, 0); /* LCDD13 */
527 at91_set_A_periph(AT91_PIN_PB19, 0); /* LCDD14 */
528 at91_set_A_periph(AT91_PIN_PB20, 0); /* LCDD15 */
529 at91_set_B_periph(AT91_PIN_PB23, 0); /* LCDD18 */
530 at91_set_B_periph(AT91_PIN_PB24, 0); /* LCDD19 */
531 at91_set_B_periph(AT91_PIN_PB25, 0); /* LCDD20 */
532 at91_set_B_periph(AT91_PIN_PB26, 0); /* LCDD21 */
533 at91_set_B_periph(AT91_PIN_PB27, 0); /* LCDD22 */
534 at91_set_B_periph(AT91_PIN_PB28, 0); /* LCDD23 */
f06e656f 535#endif
86ad76bb 536
01d3a5e7
HS		 537 if (ARRAY_SIZE(lcdc_resources) > 2) {
538 void __iomem *fb;
539 struct resource *fb_res = &lcdc_resources[2];
28f65c11 540 size_t fb_len = resource_size(fb_res);
01d3a5e7 541
90898709 542 fb = ioremap(fb_res->start, fb_len);
01d3a5e7
HS		 543 if (fb) {
544 memset(fb, 0, fb_len);
90898709 545 iounmap(fb);
01d3a5e7
HS		 546 }
547 }
86ad76bb
AV		 548 lcdc_data = *data;
549 platform_device_register(&at91_lcdc_device);
550}
551#else
7776a94c 552void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
86ad76bb
AV		 553#endif
554
555
e5f40bfa
AV		 556/* --------------------------------------------------------------------
557 * Timer/Counter block
558 * -------------------------------------------------------------------- */
559
560#ifdef CONFIG_ATMEL_TCLIB
561
562static struct resource tcb_resources[] = {
563 [0] = {
564 .start = AT91SAM9261_BASE_TCB0,
565 .end = AT91SAM9261_BASE_TCB0 + SZ_16K - 1,
566 .flags = IORESOURCE_MEM,
567 },
568 [1] = {
8fe82a55
LD		 569 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_TC0,
570 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_TC0,
e5f40bfa
AV		 571 .flags = IORESOURCE_IRQ,
572 },
573 [2] = {
8fe82a55
LD		 574 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_TC1,
575 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_TC1,
e5f40bfa
AV		 576 .flags = IORESOURCE_IRQ,
577 },
578 [3] = {
8fe82a55
LD		 579 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_TC2,
580 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_TC2,
e5f40bfa
AV		 581 .flags = IORESOURCE_IRQ,
582 },
583};
584
585static struct platform_device at91sam9261_tcb_device = {
586 .name = "atmel_tcb",
587 .id = 0,
588 .resource = tcb_resources,
589 .num_resources = ARRAY_SIZE(tcb_resources),
590};
591
592static void __init at91_add_device_tc(void)
593{
e5f40bfa
AV		 594 platform_device_register(&at91sam9261_tcb_device);
595}
596#else
597static void __init at91_add_device_tc(void) { }
598#endif
599
600
884f5a6a
AV		 601/* --------------------------------------------------------------------
602 * RTT
603 * -------------------------------------------------------------------- */
604
605static struct resource rtt_resources[] = {
606 {
eab5fd67
JCPV		 607 .start = AT91SAM9261_BASE_RTT,
608 .end = AT91SAM9261_BASE_RTT + SZ_16 - 1,
884f5a6a 609 .flags = IORESOURCE_MEM,
b3af8b49
JCPV		 610 }, {
611 .flags = IORESOURCE_MEM,
884f5a6a
AV		 612 }
613};
614
615static struct platform_device at91sam9261_rtt_device = {
616 .name = "at91_rtt",
4fd9212c 617 .id = 0,
884f5a6a 618 .resource = rtt_resources,
884f5a6a
AV		 619};
620
205056a3
JCPV		 621#if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
622static void __init at91_add_device_rtt_rtc(void)
623{
624 at91sam9261_rtt_device.name = "rtc-at91sam9";
b3af8b49
JCPV		 625 /*
626 * The second resource is needed:
627 * GPBR will serve as the storage for RTC time offset
628 */
629 at91sam9261_rtt_device.num_resources = 2;
630 rtt_resources[1].start = AT91SAM9261_BASE_GPBR +
631 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
632 rtt_resources[1].end = rtt_resources[1].start + 3;
205056a3
JCPV		 633}
634#else
b3af8b49
JCPV		 635static void __init at91_add_device_rtt_rtc(void)
636{
637 /* Only one resource is needed: RTT not used as RTC */
638 at91sam9261_rtt_device.num_resources = 1;
639}
205056a3
JCPV		 640#endif
641
884f5a6a
AV		 642static void __init at91_add_device_rtt(void)
643{
205056a3 644 at91_add_device_rtt_rtc();
884f5a6a
AV		 645 platform_device_register(&at91sam9261_rtt_device);
646}
647
648
649/* --------------------------------------------------------------------
650 * Watchdog
651 * -------------------------------------------------------------------- */
652
2af29b78 653#if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
c1c30a29
JCPV		 654static struct resource wdt_resources[] = {
655 {
656 .start = AT91SAM9261_BASE_WDT,
657 .end = AT91SAM9261_BASE_WDT + SZ_16 - 1,
658 .flags = IORESOURCE_MEM,
659 }
660};
661
884f5a6a
AV		 662static struct platform_device at91sam9261_wdt_device = {
663 .name = "at91_wdt",
664 .id = -1,
c1c30a29
JCPV		 665 .resource = wdt_resources,
666 .num_resources = ARRAY_SIZE(wdt_resources),
884f5a6a
AV		 667};
668
669static void __init at91_add_device_watchdog(void)
670{
671 platform_device_register(&at91sam9261_wdt_device);
672}
673#else
674static void __init at91_add_device_watchdog(void) {}
675#endif
676
677
bfbc3266
AV		 678/* --------------------------------------------------------------------
679 * SSC -- Synchronous Serial Controller
680 * -------------------------------------------------------------------- */
681
682#if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
683static u64 ssc0_dmamask = DMA_BIT_MASK(32);
684
685static struct resource ssc0_resources[] = {
686 [0] = {
687 .start = AT91SAM9261_BASE_SSC0,
688 .end = AT91SAM9261_BASE_SSC0 + SZ_16K - 1,
689 .flags = IORESOURCE_MEM,
690 },
691 [1] = {
8fe82a55
LD		 692 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_SSC0,
693 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_SSC0,
bfbc3266
AV		 694 .flags = IORESOURCE_IRQ,
695 },
696};
697
698static struct platform_device at91sam9261_ssc0_device = {
699 .name = "ssc",
700 .id = 0,
701 .dev = {
702 .dma_mask = &ssc0_dmamask,
703 .coherent_dma_mask = DMA_BIT_MASK(32),
704 },
705 .resource = ssc0_resources,
706 .num_resources = ARRAY_SIZE(ssc0_resources),
707};
708
709static inline void configure_ssc0_pins(unsigned pins)
710{
711 if (pins & ATMEL_SSC_TF)
712 at91_set_A_periph(AT91_PIN_PB21, 1);
713 if (pins & ATMEL_SSC_TK)
714 at91_set_A_periph(AT91_PIN_PB22, 1);
715 if (pins & ATMEL_SSC_TD)
716 at91_set_A_periph(AT91_PIN_PB23, 1);
717 if (pins & ATMEL_SSC_RD)
718 at91_set_A_periph(AT91_PIN_PB24, 1);
719 if (pins & ATMEL_SSC_RK)
720 at91_set_A_periph(AT91_PIN_PB25, 1);
721 if (pins & ATMEL_SSC_RF)
722 at91_set_A_periph(AT91_PIN_PB26, 1);
723}
724
725static u64 ssc1_dmamask = DMA_BIT_MASK(32);
726
727static struct resource ssc1_resources[] = {
728 [0] = {
729 .start = AT91SAM9261_BASE_SSC1,
730 .end = AT91SAM9261_BASE_SSC1 + SZ_16K - 1,
731 .flags = IORESOURCE_MEM,
732 },
733 [1] = {
8fe82a55
LD		 734 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_SSC1,
735 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_SSC1,
bfbc3266
AV		 736 .flags = IORESOURCE_IRQ,
737 },
738};
739
740static struct platform_device at91sam9261_ssc1_device = {
741 .name = "ssc",
742 .id = 1,
743 .dev = {
744 .dma_mask = &ssc1_dmamask,
745 .coherent_dma_mask = DMA_BIT_MASK(32),
746 },
747 .resource = ssc1_resources,
748 .num_resources = ARRAY_SIZE(ssc1_resources),
749};
750
751static inline void configure_ssc1_pins(unsigned pins)
752{
753 if (pins & ATMEL_SSC_TF)
754 at91_set_B_periph(AT91_PIN_PA17, 1);
755 if (pins & ATMEL_SSC_TK)
756 at91_set_B_periph(AT91_PIN_PA18, 1);
757 if (pins & ATMEL_SSC_TD)
758 at91_set_B_periph(AT91_PIN_PA19, 1);
759 if (pins & ATMEL_SSC_RD)
760 at91_set_B_periph(AT91_PIN_PA20, 1);
761 if (pins & ATMEL_SSC_RK)
762 at91_set_B_periph(AT91_PIN_PA21, 1);
763 if (pins & ATMEL_SSC_RF)
764 at91_set_B_periph(AT91_PIN_PA22, 1);
765}
766
767static u64 ssc2_dmamask = DMA_BIT_MASK(32);
768
769static struct resource ssc2_resources[] = {
770 [0] = {
771 .start = AT91SAM9261_BASE_SSC2,
772 .end = AT91SAM9261_BASE_SSC2 + SZ_16K - 1,
773 .flags = IORESOURCE_MEM,
774 },
775 [1] = {
8fe82a55
LD		 776 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_SSC2,
777 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_SSC2,
bfbc3266
AV		 778 .flags = IORESOURCE_IRQ,
779 },
780};
781
782static struct platform_device at91sam9261_ssc2_device = {
783 .name = "ssc",
784 .id = 2,
785 .dev = {
786 .dma_mask = &ssc2_dmamask,
787 .coherent_dma_mask = DMA_BIT_MASK(32),
788 },
789 .resource = ssc2_resources,
790 .num_resources = ARRAY_SIZE(ssc2_resources),
791};
792
793static inline void configure_ssc2_pins(unsigned pins)
794{
795 if (pins & ATMEL_SSC_TF)
796 at91_set_B_periph(AT91_PIN_PC25, 1);
797 if (pins & ATMEL_SSC_TK)
798 at91_set_B_periph(AT91_PIN_PC26, 1);
799 if (pins & ATMEL_SSC_TD)
800 at91_set_B_periph(AT91_PIN_PC27, 1);
801 if (pins & ATMEL_SSC_RD)
802 at91_set_B_periph(AT91_PIN_PC28, 1);
803 if (pins & ATMEL_SSC_RK)
804 at91_set_B_periph(AT91_PIN_PC29, 1);
805 if (pins & ATMEL_SSC_RF)
806 at91_set_B_periph(AT91_PIN_PC30, 1);
807}
808
809/*
810 * SSC controllers are accessed through library code, instead of any
811 * kind of all-singing/all-dancing driver. For example one could be
812 * used by a particular I2S audio codec's driver, while another one
813 * on the same system might be used by a custom data capture driver.
814 */
815void __init at91_add_device_ssc(unsigned id, unsigned pins)
816{
817 struct platform_device *pdev;
818
819 /*
820 * NOTE: caller is responsible for passing information matching
821 * "pins" to whatever will be using each particular controller.
822 */
823 switch (id) {
824 case AT91SAM9261_ID_SSC0:
825 pdev = &at91sam9261_ssc0_device;
826 configure_ssc0_pins(pins);
bfbc3266
AV		 827 break;
828 case AT91SAM9261_ID_SSC1:
829 pdev = &at91sam9261_ssc1_device;
830 configure_ssc1_pins(pins);
bfbc3266
AV		 831 break;
832 case AT91SAM9261_ID_SSC2:
833 pdev = &at91sam9261_ssc2_device;
834 configure_ssc2_pins(pins);
bfbc3266
AV		 835 break;
836 default:
837 return;
838 }
839
840 platform_device_register(pdev);
841}
842
843#else
844void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
845#endif
846
847
86ad76bb
AV		 848/* --------------------------------------------------------------------
849 * UART
850 * -------------------------------------------------------------------- */
851
852#if defined(CONFIG_SERIAL_ATMEL)
853static struct resource dbgu_resources[] = {
854 [0] = {
13079a73
JCPV		 855 .start = AT91SAM9261_BASE_DBGU,
856 .end = AT91SAM9261_BASE_DBGU + SZ_512 - 1,
86ad76bb
AV		 857 .flags = IORESOURCE_MEM,
858 },
859 [1] = {
8fe82a55
LD		 860 .start = NR_IRQS_LEGACY + AT91_ID_SYS,
861 .end = NR_IRQS_LEGACY + AT91_ID_SYS,
86ad76bb
AV		 862 .flags = IORESOURCE_IRQ,
863 },
864};
865
866static struct atmel_uart_data dbgu_data = {
867 .use_dma_tx = 0,
868 .use_dma_rx = 0, /* DBGU not capable of receive DMA */
86ad76bb
AV		 869};
870
c6686ff9
AV		 871static u64 dbgu_dmamask = DMA_BIT_MASK(32);
872
86ad76bb
AV		 873static struct platform_device at91sam9261_dbgu_device = {
874 .name = "atmel_usart",
875 .id = 0,
876 .dev = {
c6686ff9
AV		 877 .dma_mask = &dbgu_dmamask,
878 .coherent_dma_mask = DMA_BIT_MASK(32),
879 .platform_data = &dbgu_data,
86ad76bb
AV		 880 },
881 .resource = dbgu_resources,
882 .num_resources = ARRAY_SIZE(dbgu_resources),
883};
884
885static inline void configure_dbgu_pins(void)
886{
887 at91_set_A_periph(AT91_PIN_PA9, 0); /* DRXD */
888 at91_set_A_periph(AT91_PIN_PA10, 1); /* DTXD */
889}
890
891static struct resource uart0_resources[] = {
892 [0] = {
893 .start = AT91SAM9261_BASE_US0,
894 .end = AT91SAM9261_BASE_US0 + SZ_16K - 1,
895 .flags = IORESOURCE_MEM,
896 },
897 [1] = {
8fe82a55
LD		 898 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_US0,
899 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_US0,
86ad76bb
AV		 900 .flags = IORESOURCE_IRQ,
901 },
902};
903
904static struct atmel_uart_data uart0_data = {
905 .use_dma_tx = 1,
906 .use_dma_rx = 1,
907};
908
c6686ff9
AV		 909static u64 uart0_dmamask = DMA_BIT_MASK(32);
910
86ad76bb
AV		 911static struct platform_device at91sam9261_uart0_device = {
912 .name = "atmel_usart",
913 .id = 1,
914 .dev = {
c6686ff9
AV		 915 .dma_mask = &uart0_dmamask,
916 .coherent_dma_mask = DMA_BIT_MASK(32),
917 .platform_data = &uart0_data,
86ad76bb
AV		 918 },
919 .resource = uart0_resources,
920 .num_resources = ARRAY_SIZE(uart0_resources),
921};
922
c8f385a6 923static inline void configure_usart0_pins(unsigned pins)
86ad76bb
AV		 924{
925 at91_set_A_periph(AT91_PIN_PC8, 1); /* TXD0 */
926 at91_set_A_periph(AT91_PIN_PC9, 0); /* RXD0 */
c8f385a6
AV		 927
928 if (pins & ATMEL_UART_RTS)
929 at91_set_A_periph(AT91_PIN_PC10, 0); /* RTS0 */
930 if (pins & ATMEL_UART_CTS)
931 at91_set_A_periph(AT91_PIN_PC11, 0); /* CTS0 */
86ad76bb
AV		 932}
933
934static struct resource uart1_resources[] = {
935 [0] = {
936 .start = AT91SAM9261_BASE_US1,
937 .end = AT91SAM9261_BASE_US1 + SZ_16K - 1,
938 .flags = IORESOURCE_MEM,
939 },
940 [1] = {
8fe82a55
LD		 941 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_US1,
942 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_US1,
86ad76bb
AV		 943 .flags = IORESOURCE_IRQ,
944 },
945};
946
947static struct atmel_uart_data uart1_data = {
948 .use_dma_tx = 1,
949 .use_dma_rx = 1,
950};
951
c6686ff9
AV		 952static u64 uart1_dmamask = DMA_BIT_MASK(32);
953
86ad76bb
AV		 954static struct platform_device at91sam9261_uart1_device = {
955 .name = "atmel_usart",
956 .id = 2,
957 .dev = {
c6686ff9
AV		 958 .dma_mask = &uart1_dmamask,
959 .coherent_dma_mask = DMA_BIT_MASK(32),
960 .platform_data = &uart1_data,
86ad76bb
AV		 961 },
962 .resource = uart1_resources,
963 .num_resources = ARRAY_SIZE(uart1_resources),
964};
965
c8f385a6 966static inline void configure_usart1_pins(unsigned pins)
86ad76bb
AV		 967{
968 at91_set_A_periph(AT91_PIN_PC12, 1); /* TXD1 */
969 at91_set_A_periph(AT91_PIN_PC13, 0); /* RXD1 */
c8f385a6
AV		 970
971 if (pins & ATMEL_UART_RTS)
972 at91_set_B_periph(AT91_PIN_PA12, 0); /* RTS1 */
973 if (pins & ATMEL_UART_CTS)
974 at91_set_B_periph(AT91_PIN_PA13, 0); /* CTS1 */
86ad76bb
AV		 975}
976
977static struct resource uart2_resources[] = {
978 [0] = {
979 .start = AT91SAM9261_BASE_US2,
980 .end = AT91SAM9261_BASE_US2 + SZ_16K - 1,
981 .flags = IORESOURCE_MEM,
982 },
983 [1] = {
8fe82a55
LD		 984 .start = NR_IRQS_LEGACY + AT91SAM9261_ID_US2,
985 .end = NR_IRQS_LEGACY + AT91SAM9261_ID_US2,
86ad76bb
AV		 986 .flags = IORESOURCE_IRQ,
987 },
988};
989
990static struct atmel_uart_data uart2_data = {
991 .use_dma_tx = 1,
992 .use_dma_rx = 1,
993};
994
c6686ff9
AV		 995static u64 uart2_dmamask = DMA_BIT_MASK(32);
996
86ad76bb
AV		 997static struct platform_device at91sam9261_uart2_device = {
998 .name = "atmel_usart",
999 .id = 3,
1000 .dev = {
c6686ff9
AV		 1001 .dma_mask = &uart2_dmamask,
1002 .coherent_dma_mask = DMA_BIT_MASK(32),
1003 .platform_data = &uart2_data,
86ad76bb
AV		 1004 },
1005 .resource = uart2_resources,
1006 .num_resources = ARRAY_SIZE(uart2_resources),
1007};
1008
c8f385a6 1009static inline void configure_usart2_pins(unsigned pins)
86ad76bb
AV		 1010{
1011 at91_set_A_periph(AT91_PIN_PC15, 0); /* RXD2 */
1012 at91_set_A_periph(AT91_PIN_PC14, 1); /* TXD2 */
c8f385a6
AV		 1013
1014 if (pins & ATMEL_UART_RTS)
1015 at91_set_B_periph(AT91_PIN_PA15, 0); /* RTS2*/
1016 if (pins & ATMEL_UART_CTS)
1017 at91_set_B_periph(AT91_PIN_PA16, 0); /* CTS2 */
86ad76bb
AV		 1018}
1019
11aadac4 1020static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
86ad76bb 1021
c8f385a6
AV		 1022void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1023{
1024 struct platform_device *pdev;
2b348e2f 1025 struct atmel_uart_data *pdata;
c8f385a6
AV		 1026
1027 switch (id) {
1028 case 0: /* DBGU */
1029 pdev = &at91sam9261_dbgu_device;
1030 configure_dbgu_pins();
c8f385a6
AV		 1031 break;
1032 case AT91SAM9261_ID_US0:
1033 pdev = &at91sam9261_uart0_device;
1034 configure_usart0_pins(pins);
c8f385a6
AV		 1035 break;
1036 case AT91SAM9261_ID_US1:
1037 pdev = &at91sam9261_uart1_device;
1038 configure_usart1_pins(pins);
c8f385a6
AV		 1039 break;
1040 case AT91SAM9261_ID_US2:
1041 pdev = &at91sam9261_uart2_device;
1042 configure_usart2_pins(pins);
c8f385a6
AV		 1043 break;
1044 default:
1045 return;
1046 }
2b348e2f
JCPV		 1047 pdata = pdev->dev.platform_data;
1048 pdata->num = portnr; /* update to mapped ID */
c8f385a6
AV		 1049
1050 if (portnr < ATMEL_MAX_UART)
1051 at91_uarts[portnr] = pdev;
1052}
1053
86ad76bb
AV		 1054void __init at91_add_device_serial(void)
1055{
1056 int i;
1057
1058 for (i = 0; i < ATMEL_MAX_UART; i++) {
1059 if (at91_uarts[i])
1060 platform_device_register(at91_uarts[i]);
1061 }
1062}
1063#else
c8f385a6 1064void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
86ad76bb
AV		 1065void __init at91_add_device_serial(void) {}
1066#endif
1067
1068
1069/* -------------------------------------------------------------------- */
1070
1071/*
1072 * These devices are always present and don't need any board-specific
1073 * setup.
1074 */
1075static int __init at91_add_standard_devices(void)
1076{
884f5a6a
AV		 1077 at91_add_device_rtt();
1078 at91_add_device_watchdog();
e5f40bfa 1079 at91_add_device_tc();
86ad76bb
AV		 1080 return 0;
1081}
1082
1083arch_initcall(at91_add_standard_devices);
Linux kernel - Deliverables
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