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[ARM] 4761/1: [AT91] Board-support for NEW_LEDs
[deliverable/linux.git] / arch / arm / mach-at91 / at91sam9261_devices.c
CommitLineData
86ad76bb 1/*
9d041268 2 * arch/arm/mach-at91/at91sam9261_devices.c
86ad76bb
AV		 3 *
4 * Copyright (C) 2005 Thibaut VARENE <varenet@parisc-linux.org>
5 * Copyright (C) 2005 David Brownell
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 */
13#include <asm/mach/arch.h>
14#include <asm/mach/map.h>
15
c6686ff9 16#include <linux/dma-mapping.h>
86ad76bb 17#include <linux/platform_device.h>
f230d3f5 18#include <linux/i2c-gpio.h>
86ad76bb 19
f230d3f5 20#include <linux/fb.h>
b8b78609
JA		 21#include <video/atmel_lcdc.h>
22
86ad76bb
AV		 23#include <asm/arch/board.h>
24#include <asm/arch/gpio.h>
25#include <asm/arch/at91sam9261.h>
26#include <asm/arch/at91sam9261_matrix.h>
27#include <asm/arch/at91sam926x_mc.h>
28
29#include "generic.h"
30
86ad76bb
AV		 31
32/* --------------------------------------------------------------------
33 * USB Host
34 * -------------------------------------------------------------------- */
35
36#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
c6686ff9 37static u64 ohci_dmamask = DMA_BIT_MASK(32);
86ad76bb
AV		 38static struct at91_usbh_data usbh_data;
39
40static struct resource usbh_resources[] = {
41 [0] = {
42 .start = AT91SAM9261_UHP_BASE,
43 .end = AT91SAM9261_UHP_BASE + SZ_1M - 1,
44 .flags = IORESOURCE_MEM,
45 },
46 [1] = {
47 .start = AT91SAM9261_ID_UHP,
48 .end = AT91SAM9261_ID_UHP,
49 .flags = IORESOURCE_IRQ,
50 },
51};
52
53static struct platform_device at91sam9261_usbh_device = {
54 .name = "at91_ohci",
55 .id = -1,
56 .dev = {
57 .dma_mask = &ohci_dmamask,
c6686ff9 58 .coherent_dma_mask = DMA_BIT_MASK(32),
86ad76bb
AV		 59 .platform_data = &usbh_data,
60 },
61 .resource = usbh_resources,
62 .num_resources = ARRAY_SIZE(usbh_resources),
63};
64
65void __init at91_add_device_usbh(struct at91_usbh_data *data)
66{
67 if (!data)
68 return;
69
70 usbh_data = *data;
71 platform_device_register(&at91sam9261_usbh_device);
72}
73#else
74void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
75#endif
76
77
78/* --------------------------------------------------------------------
79 * USB Device (Gadget)
80 * -------------------------------------------------------------------- */
81
82#ifdef CONFIG_USB_GADGET_AT91
83static struct at91_udc_data udc_data;
84
85static struct resource udc_resources[] = {
86 [0] = {
87 .start = AT91SAM9261_BASE_UDP,
88 .end = AT91SAM9261_BASE_UDP + SZ_16K - 1,
89 .flags = IORESOURCE_MEM,
90 },
91 [1] = {
92 .start = AT91SAM9261_ID_UDP,
93 .end = AT91SAM9261_ID_UDP,
94 .flags = IORESOURCE_IRQ,
95 },
96};
97
98static struct platform_device at91sam9261_udc_device = {
99 .name = "at91_udc",
100 .id = -1,
101 .dev = {
102 .platform_data = &udc_data,
103 },
104 .resource = udc_resources,
105 .num_resources = ARRAY_SIZE(udc_resources),
106};
107
108void __init at91_add_device_udc(struct at91_udc_data *data)
109{
110 unsigned long x;
111
112 if (!data)
113 return;
114
115 if (data->vbus_pin) {
116 at91_set_gpio_input(data->vbus_pin, 0);
117 at91_set_deglitch(data->vbus_pin, 1);
118 }
119
120 /* Pullup pin is handled internally */
121 x = at91_sys_read(AT91_MATRIX_USBPUCR);
122 at91_sys_write(AT91_MATRIX_USBPUCR, x | AT91_MATRIX_USBPUCR_PUON);
123
124 udc_data = *data;
125 platform_device_register(&at91sam9261_udc_device);
126}
127#else
128void __init at91_add_device_udc(struct at91_udc_data *data) {}
129#endif
130
131/* --------------------------------------------------------------------
132 * MMC / SD
133 * -------------------------------------------------------------------- */
134
135#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
c6686ff9 136static u64 mmc_dmamask = DMA_BIT_MASK(32);
86ad76bb
AV		 137static struct at91_mmc_data mmc_data;
138
139static struct resource mmc_resources[] = {
140 [0] = {
141 .start = AT91SAM9261_BASE_MCI,
142 .end = AT91SAM9261_BASE_MCI + SZ_16K - 1,
143 .flags = IORESOURCE_MEM,
144 },
145 [1] = {
146 .start = AT91SAM9261_ID_MCI,
147 .end = AT91SAM9261_ID_MCI,
148 .flags = IORESOURCE_IRQ,
149 },
150};
151
152static struct platform_device at91sam9261_mmc_device = {
153 .name = "at91_mci",
154 .id = -1,
155 .dev = {
156 .dma_mask = &mmc_dmamask,
c6686ff9 157 .coherent_dma_mask = DMA_BIT_MASK(32),
86ad76bb
AV		 158 .platform_data = &mmc_data,
159 },
160 .resource = mmc_resources,
161 .num_resources = ARRAY_SIZE(mmc_resources),
162};
163
d0760b3b 164void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
86ad76bb
AV		 165{
166 if (!data)
167 return;
168
169 /* input/irq */
170 if (data->det_pin) {
171 at91_set_gpio_input(data->det_pin, 1);
172 at91_set_deglitch(data->det_pin, 1);
173 }
174 if (data->wp_pin)
175 at91_set_gpio_input(data->wp_pin, 1);
176 if (data->vcc_pin)
177 at91_set_gpio_output(data->vcc_pin, 0);
178
179 /* CLK */
180 at91_set_B_periph(AT91_PIN_PA2, 0);
181
182 /* CMD */
183 at91_set_B_periph(AT91_PIN_PA1, 1);
184
185 /* DAT0, maybe DAT1..DAT3 */
186 at91_set_B_periph(AT91_PIN_PA0, 1);
187 if (data->wire4) {
188 at91_set_B_periph(AT91_PIN_PA4, 1);
189 at91_set_B_periph(AT91_PIN_PA5, 1);
190 at91_set_B_periph(AT91_PIN_PA6, 1);
191 }
192
193 mmc_data = *data;
194 platform_device_register(&at91sam9261_mmc_device);
195}
196#else
d0760b3b 197void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
86ad76bb
AV		 198#endif
199
200
201/* --------------------------------------------------------------------
202 * NAND / SmartMedia
203 * -------------------------------------------------------------------- */
204
205#if defined(CONFIG_MTD_NAND_AT91) || defined(CONFIG_MTD_NAND_AT91_MODULE)
206static struct at91_nand_data nand_data;
207
208#define NAND_BASE AT91_CHIPSELECT_3
209
210static struct resource nand_resources[] = {
211 {
212 .start = NAND_BASE,
213 .end = NAND_BASE + SZ_256M - 1,
214 .flags = IORESOURCE_MEM,
215 }
216};
217
218static struct platform_device at91_nand_device = {
219 .name = "at91_nand",
220 .id = -1,
221 .dev = {
222 .platform_data = &nand_data,
223 },
224 .resource = nand_resources,
225 .num_resources = ARRAY_SIZE(nand_resources),
226};
227
228void __init at91_add_device_nand(struct at91_nand_data *data)
229{
230 unsigned long csa, mode;
231
232 if (!data)
233 return;
234
235 csa = at91_sys_read(AT91_MATRIX_EBICSA);
22823558 236 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
86ad76bb
AV		 237
238 /* set the bus interface characteristics */
239 at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0)
240 | AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
241
242 at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(2) | AT91_SMC_NCS_WRPULSE_(5)
243 | AT91_SMC_NRDPULSE_(2) | AT91_SMC_NCS_RDPULSE_(5));
244
245 at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7));
246
247 if (data->bus_width_16)
248 mode = AT91_SMC_DBW_16;
249 else
250 mode = AT91_SMC_DBW_8;
251 at91_sys_write(AT91_SMC_MODE(3), mode | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(1));
252
253 /* enable pin */
254 if (data->enable_pin)
255 at91_set_gpio_output(data->enable_pin, 1);
256
257 /* ready/busy pin */
258 if (data->rdy_pin)
259 at91_set_gpio_input(data->rdy_pin, 1);
260
261 /* card detect pin */
262 if (data->det_pin)
263 at91_set_gpio_input(data->det_pin, 1);
264
265 at91_set_A_periph(AT91_PIN_PC0, 0); /* NANDOE */
266 at91_set_A_periph(AT91_PIN_PC1, 0); /* NANDWE */
267
268 nand_data = *data;
269 platform_device_register(&at91_nand_device);
270}
271
272#else
273void __init at91_add_device_nand(struct at91_nand_data *data) {}
274#endif
275
276
277/* --------------------------------------------------------------------
278 * TWI (i2c)
279 * -------------------------------------------------------------------- */
280
f230d3f5
AV		 281/*
282 * Prefer the GPIO code since the TWI controller isn't robust
283 * (gets overruns and underruns under load) and can only issue
284 * repeated STARTs in one scenario (the driver doesn't yet handle them).
285 */
286#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
287
288static struct i2c_gpio_platform_data pdata = {
289 .sda_pin = AT91_PIN_PA7,
290 .sda_is_open_drain = 1,
291 .scl_pin = AT91_PIN_PA8,
292 .scl_is_open_drain = 1,
293 .udelay = 2, /* ~100 kHz */
294};
295
296static struct platform_device at91sam9261_twi_device = {
297 .name = "i2c-gpio",
298 .id = -1,
299 .dev.platform_data = &pdata,
300};
301
302void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
303{
304 at91_set_GPIO_periph(AT91_PIN_PA7, 1); /* TWD (SDA) */
305 at91_set_multi_drive(AT91_PIN_PA7, 1);
306
307 at91_set_GPIO_periph(AT91_PIN_PA8, 1); /* TWCK (SCL) */
308 at91_set_multi_drive(AT91_PIN_PA8, 1);
309
310 i2c_register_board_info(0, devices, nr_devices);
311 platform_device_register(&at91sam9261_twi_device);
312}
313
314#elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
86ad76bb
AV		 315
316static struct resource twi_resources[] = {
317 [0] = {
318 .start = AT91SAM9261_BASE_TWI,
319 .end = AT91SAM9261_BASE_TWI + SZ_16K - 1,
320 .flags = IORESOURCE_MEM,
321 },
322 [1] = {
323 .start = AT91SAM9261_ID_TWI,
324 .end = AT91SAM9261_ID_TWI,
325 .flags = IORESOURCE_IRQ,
326 },
327};
328
329static struct platform_device at91sam9261_twi_device = {
330 .name = "at91_i2c",
331 .id = -1,
332 .resource = twi_resources,
333 .num_resources = ARRAY_SIZE(twi_resources),
334};
335
f230d3f5 336void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
86ad76bb
AV		 337{
338 /* pins used for TWI interface */
339 at91_set_A_periph(AT91_PIN_PA7, 0); /* TWD */
340 at91_set_multi_drive(AT91_PIN_PA7, 1);
341
342 at91_set_A_periph(AT91_PIN_PA8, 0); /* TWCK */
343 at91_set_multi_drive(AT91_PIN_PA8, 1);
344
f230d3f5 345 i2c_register_board_info(0, devices, nr_devices);
86ad76bb
AV		 346 platform_device_register(&at91sam9261_twi_device);
347}
348#else
f230d3f5 349void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
86ad76bb
AV		 350#endif
351
352
353/* --------------------------------------------------------------------
354 * SPI
355 * -------------------------------------------------------------------- */
356
357#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
c6686ff9 358static u64 spi_dmamask = DMA_BIT_MASK(32);
86ad76bb
AV		 359
360static struct resource spi0_resources[] = {
361 [0] = {
362 .start = AT91SAM9261_BASE_SPI0,
363 .end = AT91SAM9261_BASE_SPI0 + SZ_16K - 1,
364 .flags = IORESOURCE_MEM,
365 },
366 [1] = {
367 .start = AT91SAM9261_ID_SPI0,
368 .end = AT91SAM9261_ID_SPI0,
369 .flags = IORESOURCE_IRQ,
370 },
371};
372
373static struct platform_device at91sam9261_spi0_device = {
374 .name = "atmel_spi",
375 .id = 0,
376 .dev = {
377 .dma_mask = &spi_dmamask,
c6686ff9 378 .coherent_dma_mask = DMA_BIT_MASK(32),
86ad76bb
AV		 379 },
380 .resource = spi0_resources,
381 .num_resources = ARRAY_SIZE(spi0_resources),
382};
383
384static const unsigned spi0_standard_cs[4] = { AT91_PIN_PA3, AT91_PIN_PA4, AT91_PIN_PA5, AT91_PIN_PA6 };
385
386static struct resource spi1_resources[] = {
387 [0] = {
388 .start = AT91SAM9261_BASE_SPI1,
389 .end = AT91SAM9261_BASE_SPI1 + SZ_16K - 1,
390 .flags = IORESOURCE_MEM,
391 },
392 [1] = {
393 .start = AT91SAM9261_ID_SPI1,
394 .end = AT91SAM9261_ID_SPI1,
395 .flags = IORESOURCE_IRQ,
396 },
397};
398
399static struct platform_device at91sam9261_spi1_device = {
400 .name = "atmel_spi",
401 .id = 1,
402 .dev = {
403 .dma_mask = &spi_dmamask,
c6686ff9 404 .coherent_dma_mask = DMA_BIT_MASK(32),
86ad76bb
AV		 405 },
406 .resource = spi1_resources,
407 .num_resources = ARRAY_SIZE(spi1_resources),
408};
409
410static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB28, AT91_PIN_PA24, AT91_PIN_PA25, AT91_PIN_PA26 };
411
412void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
413{
414 int i;
415 unsigned long cs_pin;
416 short enable_spi0 = 0;
417 short enable_spi1 = 0;
418
419 /* Choose SPI chip-selects */
420 for (i = 0; i < nr_devices; i++) {
421 if (devices[i].controller_data)
422 cs_pin = (unsigned long) devices[i].controller_data;
423 else if (devices[i].bus_num == 0)
424 cs_pin = spi0_standard_cs[devices[i].chip_select];
425 else
426 cs_pin = spi1_standard_cs[devices[i].chip_select];
427
428 if (devices[i].bus_num == 0)
429 enable_spi0 = 1;
430 else
431 enable_spi1 = 1;
432
433 /* enable chip-select pin */
434 at91_set_gpio_output(cs_pin, 1);
435
436 /* pass chip-select pin to driver */
437 devices[i].controller_data = (void *) cs_pin;
438 }
439
440 spi_register_board_info(devices, nr_devices);
441
442 /* Configure SPI bus(es) */
443 if (enable_spi0) {
444 at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
445 at91_set_A_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
446 at91_set_A_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */
447
448 at91_clock_associate("spi0_clk", &at91sam9261_spi0_device.dev, "spi_clk");
449 platform_device_register(&at91sam9261_spi0_device);
450 }
451 if (enable_spi1) {
452 at91_set_A_periph(AT91_PIN_PB30, 0); /* SPI1_MISO */
453 at91_set_A_periph(AT91_PIN_PB31, 0); /* SPI1_MOSI */
454 at91_set_A_periph(AT91_PIN_PB29, 0); /* SPI1_SPCK */
455
456 at91_clock_associate("spi1_clk", &at91sam9261_spi1_device.dev, "spi_clk");
457 platform_device_register(&at91sam9261_spi1_device);
458 }
459}
460#else
461void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
462#endif
463
464
465/* --------------------------------------------------------------------
466 * LCD Controller
467 * -------------------------------------------------------------------- */
468
7776a94c 469#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
c6686ff9 470static u64 lcdc_dmamask = DMA_BIT_MASK(32);
7776a94c 471static struct atmel_lcdfb_info lcdc_data;
86ad76bb
AV		 472
473static struct resource lcdc_resources[] = {
474 [0] = {
475 .start = AT91SAM9261_LCDC_BASE,
476 .end = AT91SAM9261_LCDC_BASE + SZ_4K - 1,
477 .flags = IORESOURCE_MEM,
478 },
479 [1] = {
480 .start = AT91SAM9261_ID_LCDC,
481 .end = AT91SAM9261_ID_LCDC,
482 .flags = IORESOURCE_IRQ,
483 },
484#if defined(CONFIG_FB_INTSRAM)
485 [2] = {
486 .start = AT91SAM9261_SRAM_BASE,
487 .end = AT91SAM9261_SRAM_BASE + AT91SAM9261_SRAM_SIZE - 1,
488 .flags = IORESOURCE_MEM,
489 },
490#endif
491};
492
493static struct platform_device at91_lcdc_device = {
7776a94c 494 .name = "atmel_lcdfb",
86ad76bb
AV		 495 .id = 0,
496 .dev = {
497 .dma_mask = &lcdc_dmamask,
c6686ff9 498 .coherent_dma_mask = DMA_BIT_MASK(32),
86ad76bb
AV		 499 .platform_data = &lcdc_data,
500 },
501 .resource = lcdc_resources,
502 .num_resources = ARRAY_SIZE(lcdc_resources),
503};
504
7776a94c 505void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
86ad76bb
AV		 506{
507 if (!data) {
508 return;
509 }
510
f06e656f
AV		 511#if defined(CONFIG_FB_ATMEL_STN)
512 at91_set_A_periph(AT91_PIN_PB0, 0); /* LCDVSYNC */
513 at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */
514 at91_set_A_periph(AT91_PIN_PB2, 0); /* LCDDOTCK */
515 at91_set_A_periph(AT91_PIN_PB3, 0); /* LCDDEN */
516 at91_set_A_periph(AT91_PIN_PB4, 0); /* LCDCC */
517 at91_set_A_periph(AT91_PIN_PB5, 0); /* LCDD0 */
518 at91_set_A_periph(AT91_PIN_PB6, 0); /* LCDD1 */
519 at91_set_A_periph(AT91_PIN_PB7, 0); /* LCDD2 */
520 at91_set_A_periph(AT91_PIN_PB8, 0); /* LCDD3 */
521#else
86ad76bb
AV		 522 at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */
523 at91_set_A_periph(AT91_PIN_PB2, 0); /* LCDDOTCK */
524 at91_set_A_periph(AT91_PIN_PB3, 0); /* LCDDEN */
525 at91_set_A_periph(AT91_PIN_PB4, 0); /* LCDCC */
526 at91_set_A_periph(AT91_PIN_PB7, 0); /* LCDD2 */
527 at91_set_A_periph(AT91_PIN_PB8, 0); /* LCDD3 */
528 at91_set_A_periph(AT91_PIN_PB9, 0); /* LCDD4 */
529 at91_set_A_periph(AT91_PIN_PB10, 0); /* LCDD5 */
530 at91_set_A_periph(AT91_PIN_PB11, 0); /* LCDD6 */
531 at91_set_A_periph(AT91_PIN_PB12, 0); /* LCDD7 */
532 at91_set_A_periph(AT91_PIN_PB15, 0); /* LCDD10 */
533 at91_set_A_periph(AT91_PIN_PB16, 0); /* LCDD11 */
534 at91_set_A_periph(AT91_PIN_PB17, 0); /* LCDD12 */
535 at91_set_A_periph(AT91_PIN_PB18, 0); /* LCDD13 */
536 at91_set_A_periph(AT91_PIN_PB19, 0); /* LCDD14 */
537 at91_set_A_periph(AT91_PIN_PB20, 0); /* LCDD15 */
538 at91_set_B_periph(AT91_PIN_PB23, 0); /* LCDD18 */
539 at91_set_B_periph(AT91_PIN_PB24, 0); /* LCDD19 */
540 at91_set_B_periph(AT91_PIN_PB25, 0); /* LCDD20 */
541 at91_set_B_periph(AT91_PIN_PB26, 0); /* LCDD21 */
542 at91_set_B_periph(AT91_PIN_PB27, 0); /* LCDD22 */
543 at91_set_B_periph(AT91_PIN_PB28, 0); /* LCDD23 */
f06e656f 544#endif
86ad76bb
AV		 545
546 lcdc_data = *data;
547 platform_device_register(&at91_lcdc_device);
548}
549#else
7776a94c 550void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
86ad76bb
AV		 551#endif
552
553
884f5a6a
AV		 554/* --------------------------------------------------------------------
555 * RTT
556 * -------------------------------------------------------------------- */
557
558static struct resource rtt_resources[] = {
559 {
560 .start = AT91_BASE_SYS + AT91_RTT,
561 .end = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1,
562 .flags = IORESOURCE_MEM,
563 }
564};
565
566static struct platform_device at91sam9261_rtt_device = {
567 .name = "at91_rtt",
568 .id = -1,
569 .resource = rtt_resources,
570 .num_resources = ARRAY_SIZE(rtt_resources),
571};
572
573static void __init at91_add_device_rtt(void)
574{
575 platform_device_register(&at91sam9261_rtt_device);
576}
577
578
579/* --------------------------------------------------------------------
580 * Watchdog
581 * -------------------------------------------------------------------- */
582
583#if defined(CONFIG_AT91SAM9_WATCHDOG) || defined(CONFIG_AT91SAM9_WATCHDOG_MODULE)
584static struct platform_device at91sam9261_wdt_device = {
585 .name = "at91_wdt",
586 .id = -1,
587 .num_resources = 0,
588};
589
590static void __init at91_add_device_watchdog(void)
591{
592 platform_device_register(&at91sam9261_wdt_device);
593}
594#else
595static void __init at91_add_device_watchdog(void) {}
596#endif
597
598
bfbc3266
AV		 599/* --------------------------------------------------------------------
600 * SSC -- Synchronous Serial Controller
601 * -------------------------------------------------------------------- */
602
603#if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
604static u64 ssc0_dmamask = DMA_BIT_MASK(32);
605
606static struct resource ssc0_resources[] = {
607 [0] = {
608 .start = AT91SAM9261_BASE_SSC0,
609 .end = AT91SAM9261_BASE_SSC0 + SZ_16K - 1,
610 .flags = IORESOURCE_MEM,
611 },
612 [1] = {
613 .start = AT91SAM9261_ID_SSC0,
614 .end = AT91SAM9261_ID_SSC0,
615 .flags = IORESOURCE_IRQ,
616 },
617};
618
619static struct platform_device at91sam9261_ssc0_device = {
620 .name = "ssc",
621 .id = 0,
622 .dev = {
623 .dma_mask = &ssc0_dmamask,
624 .coherent_dma_mask = DMA_BIT_MASK(32),
625 },
626 .resource = ssc0_resources,
627 .num_resources = ARRAY_SIZE(ssc0_resources),
628};
629
630static inline void configure_ssc0_pins(unsigned pins)
631{
632 if (pins & ATMEL_SSC_TF)
633 at91_set_A_periph(AT91_PIN_PB21, 1);
634 if (pins & ATMEL_SSC_TK)
635 at91_set_A_periph(AT91_PIN_PB22, 1);
636 if (pins & ATMEL_SSC_TD)
637 at91_set_A_periph(AT91_PIN_PB23, 1);
638 if (pins & ATMEL_SSC_RD)
639 at91_set_A_periph(AT91_PIN_PB24, 1);
640 if (pins & ATMEL_SSC_RK)
641 at91_set_A_periph(AT91_PIN_PB25, 1);
642 if (pins & ATMEL_SSC_RF)
643 at91_set_A_periph(AT91_PIN_PB26, 1);
644}
645
646static u64 ssc1_dmamask = DMA_BIT_MASK(32);
647
648static struct resource ssc1_resources[] = {
649 [0] = {
650 .start = AT91SAM9261_BASE_SSC1,
651 .end = AT91SAM9261_BASE_SSC1 + SZ_16K - 1,
652 .flags = IORESOURCE_MEM,
653 },
654 [1] = {
655 .start = AT91SAM9261_ID_SSC1,
656 .end = AT91SAM9261_ID_SSC1,
657 .flags = IORESOURCE_IRQ,
658 },
659};
660
661static struct platform_device at91sam9261_ssc1_device = {
662 .name = "ssc",
663 .id = 1,
664 .dev = {
665 .dma_mask = &ssc1_dmamask,
666 .coherent_dma_mask = DMA_BIT_MASK(32),
667 },
668 .resource = ssc1_resources,
669 .num_resources = ARRAY_SIZE(ssc1_resources),
670};
671
672static inline void configure_ssc1_pins(unsigned pins)
673{
674 if (pins & ATMEL_SSC_TF)
675 at91_set_B_periph(AT91_PIN_PA17, 1);
676 if (pins & ATMEL_SSC_TK)
677 at91_set_B_periph(AT91_PIN_PA18, 1);
678 if (pins & ATMEL_SSC_TD)
679 at91_set_B_periph(AT91_PIN_PA19, 1);
680 if (pins & ATMEL_SSC_RD)
681 at91_set_B_periph(AT91_PIN_PA20, 1);
682 if (pins & ATMEL_SSC_RK)
683 at91_set_B_periph(AT91_PIN_PA21, 1);
684 if (pins & ATMEL_SSC_RF)
685 at91_set_B_periph(AT91_PIN_PA22, 1);
686}
687
688static u64 ssc2_dmamask = DMA_BIT_MASK(32);
689
690static struct resource ssc2_resources[] = {
691 [0] = {
692 .start = AT91SAM9261_BASE_SSC2,
693 .end = AT91SAM9261_BASE_SSC2 + SZ_16K - 1,
694 .flags = IORESOURCE_MEM,
695 },
696 [1] = {
697 .start = AT91SAM9261_ID_SSC2,
698 .end = AT91SAM9261_ID_SSC2,
699 .flags = IORESOURCE_IRQ,
700 },
701};
702
703static struct platform_device at91sam9261_ssc2_device = {
704 .name = "ssc",
705 .id = 2,
706 .dev = {
707 .dma_mask = &ssc2_dmamask,
708 .coherent_dma_mask = DMA_BIT_MASK(32),
709 },
710 .resource = ssc2_resources,
711 .num_resources = ARRAY_SIZE(ssc2_resources),
712};
713
714static inline void configure_ssc2_pins(unsigned pins)
715{
716 if (pins & ATMEL_SSC_TF)
717 at91_set_B_periph(AT91_PIN_PC25, 1);
718 if (pins & ATMEL_SSC_TK)
719 at91_set_B_periph(AT91_PIN_PC26, 1);
720 if (pins & ATMEL_SSC_TD)
721 at91_set_B_periph(AT91_PIN_PC27, 1);
722 if (pins & ATMEL_SSC_RD)
723 at91_set_B_periph(AT91_PIN_PC28, 1);
724 if (pins & ATMEL_SSC_RK)
725 at91_set_B_periph(AT91_PIN_PC29, 1);
726 if (pins & ATMEL_SSC_RF)
727 at91_set_B_periph(AT91_PIN_PC30, 1);
728}
729
730/*
731 * SSC controllers are accessed through library code, instead of any
732 * kind of all-singing/all-dancing driver. For example one could be
733 * used by a particular I2S audio codec's driver, while another one
734 * on the same system might be used by a custom data capture driver.
735 */
736void __init at91_add_device_ssc(unsigned id, unsigned pins)
737{
738 struct platform_device *pdev;
739
740 /*
741 * NOTE: caller is responsible for passing information matching
742 * "pins" to whatever will be using each particular controller.
743 */
744 switch (id) {
745 case AT91SAM9261_ID_SSC0:
746 pdev = &at91sam9261_ssc0_device;
747 configure_ssc0_pins(pins);
748 at91_clock_associate("ssc0_clk", &pdev->dev, "pclk");
749 break;
750 case AT91SAM9261_ID_SSC1:
751 pdev = &at91sam9261_ssc1_device;
752 configure_ssc1_pins(pins);
753 at91_clock_associate("ssc1_clk", &pdev->dev, "pclk");
754 break;
755 case AT91SAM9261_ID_SSC2:
756 pdev = &at91sam9261_ssc2_device;
757 configure_ssc2_pins(pins);
758 at91_clock_associate("ssc2_clk", &pdev->dev, "pclk");
759 break;
760 default:
761 return;
762 }
763
764 platform_device_register(pdev);
765}
766
767#else
768void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
769#endif
770
771
86ad76bb
AV		 772/* --------------------------------------------------------------------
773 * UART
774 * -------------------------------------------------------------------- */
775
776#if defined(CONFIG_SERIAL_ATMEL)
777static struct resource dbgu_resources[] = {
778 [0] = {
779 .start = AT91_VA_BASE_SYS + AT91_DBGU,
780 .end = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
781 .flags = IORESOURCE_MEM,
782 },
783 [1] = {
784 .start = AT91_ID_SYS,
785 .end = AT91_ID_SYS,
786 .flags = IORESOURCE_IRQ,
787 },
788};
789
790static struct atmel_uart_data dbgu_data = {
791 .use_dma_tx = 0,
792 .use_dma_rx = 0, /* DBGU not capable of receive DMA */
793 .regs = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
794};
795
c6686ff9
AV		 796static u64 dbgu_dmamask = DMA_BIT_MASK(32);
797
86ad76bb
AV		 798static struct platform_device at91sam9261_dbgu_device = {
799 .name = "atmel_usart",
800 .id = 0,
801 .dev = {
c6686ff9
AV		 802 .dma_mask = &dbgu_dmamask,
803 .coherent_dma_mask = DMA_BIT_MASK(32),
804 .platform_data = &dbgu_data,
86ad76bb
AV		 805 },
806 .resource = dbgu_resources,
807 .num_resources = ARRAY_SIZE(dbgu_resources),
808};
809
810static inline void configure_dbgu_pins(void)
811{
812 at91_set_A_periph(AT91_PIN_PA9, 0); /* DRXD */
813 at91_set_A_periph(AT91_PIN_PA10, 1); /* DTXD */
814}
815
816static struct resource uart0_resources[] = {
817 [0] = {
818 .start = AT91SAM9261_BASE_US0,
819 .end = AT91SAM9261_BASE_US0 + SZ_16K - 1,
820 .flags = IORESOURCE_MEM,
821 },
822 [1] = {
823 .start = AT91SAM9261_ID_US0,
824 .end = AT91SAM9261_ID_US0,
825 .flags = IORESOURCE_IRQ,
826 },
827};
828
829static struct atmel_uart_data uart0_data = {
830 .use_dma_tx = 1,
831 .use_dma_rx = 1,
832};
833
c6686ff9
AV		 834static u64 uart0_dmamask = DMA_BIT_MASK(32);
835
86ad76bb
AV		 836static struct platform_device at91sam9261_uart0_device = {
837 .name = "atmel_usart",
838 .id = 1,
839 .dev = {
c6686ff9
AV		 840 .dma_mask = &uart0_dmamask,
841 .coherent_dma_mask = DMA_BIT_MASK(32),
842 .platform_data = &uart0_data,
86ad76bb
AV		 843 },
844 .resource = uart0_resources,
845 .num_resources = ARRAY_SIZE(uart0_resources),
846};
847
c8f385a6 848static inline void configure_usart0_pins(unsigned pins)
86ad76bb
AV		 849{
850 at91_set_A_periph(AT91_PIN_PC8, 1); /* TXD0 */
851 at91_set_A_periph(AT91_PIN_PC9, 0); /* RXD0 */
c8f385a6
AV		 852
853 if (pins & ATMEL_UART_RTS)
854 at91_set_A_periph(AT91_PIN_PC10, 0); /* RTS0 */
855 if (pins & ATMEL_UART_CTS)
856 at91_set_A_periph(AT91_PIN_PC11, 0); /* CTS0 */
86ad76bb
AV		 857}
858
859static struct resource uart1_resources[] = {
860 [0] = {
861 .start = AT91SAM9261_BASE_US1,
862 .end = AT91SAM9261_BASE_US1 + SZ_16K - 1,
863 .flags = IORESOURCE_MEM,
864 },
865 [1] = {
866 .start = AT91SAM9261_ID_US1,
867 .end = AT91SAM9261_ID_US1,
868 .flags = IORESOURCE_IRQ,
869 },
870};
871
872static struct atmel_uart_data uart1_data = {
873 .use_dma_tx = 1,
874 .use_dma_rx = 1,
875};
876
c6686ff9
AV		 877static u64 uart1_dmamask = DMA_BIT_MASK(32);
878
86ad76bb
AV		 879static struct platform_device at91sam9261_uart1_device = {
880 .name = "atmel_usart",
881 .id = 2,
882 .dev = {
c6686ff9
AV		 883 .dma_mask = &uart1_dmamask,
884 .coherent_dma_mask = DMA_BIT_MASK(32),
885 .platform_data = &uart1_data,
86ad76bb
AV		 886 },
887 .resource = uart1_resources,
888 .num_resources = ARRAY_SIZE(uart1_resources),
889};
890
c8f385a6 891static inline void configure_usart1_pins(unsigned pins)
86ad76bb
AV		 892{
893 at91_set_A_periph(AT91_PIN_PC12, 1); /* TXD1 */
894 at91_set_A_periph(AT91_PIN_PC13, 0); /* RXD1 */
c8f385a6
AV		 895
896 if (pins & ATMEL_UART_RTS)
897 at91_set_B_periph(AT91_PIN_PA12, 0); /* RTS1 */
898 if (pins & ATMEL_UART_CTS)
899 at91_set_B_periph(AT91_PIN_PA13, 0); /* CTS1 */
86ad76bb
AV		 900}
901
902static struct resource uart2_resources[] = {
903 [0] = {
904 .start = AT91SAM9261_BASE_US2,
905 .end = AT91SAM9261_BASE_US2 + SZ_16K - 1,
906 .flags = IORESOURCE_MEM,
907 },
908 [1] = {
909 .start = AT91SAM9261_ID_US2,
910 .end = AT91SAM9261_ID_US2,
911 .flags = IORESOURCE_IRQ,
912 },
913};
914
915static struct atmel_uart_data uart2_data = {
916 .use_dma_tx = 1,
917 .use_dma_rx = 1,
918};
919
c6686ff9
AV		 920static u64 uart2_dmamask = DMA_BIT_MASK(32);
921
86ad76bb
AV		 922static struct platform_device at91sam9261_uart2_device = {
923 .name = "atmel_usart",
924 .id = 3,
925 .dev = {
c6686ff9
AV		 926 .dma_mask = &uart2_dmamask,
927 .coherent_dma_mask = DMA_BIT_MASK(32),
928 .platform_data = &uart2_data,
86ad76bb
AV		 929 },
930 .resource = uart2_resources,
931 .num_resources = ARRAY_SIZE(uart2_resources),
932};
933
c8f385a6 934static inline void configure_usart2_pins(unsigned pins)
86ad76bb
AV		 935{
936 at91_set_A_periph(AT91_PIN_PC15, 0); /* RXD2 */
937 at91_set_A_periph(AT91_PIN_PC14, 1); /* TXD2 */
c8f385a6
AV		 938
939 if (pins & ATMEL_UART_RTS)
940 at91_set_B_periph(AT91_PIN_PA15, 0); /* RTS2*/
941 if (pins & ATMEL_UART_CTS)
942 at91_set_B_periph(AT91_PIN_PA16, 0); /* CTS2 */
86ad76bb
AV		 943}
944
c6686ff9 945static struct platform_device *at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
86ad76bb
AV		 946struct platform_device *atmel_default_console_device; /* the serial console device */
947
c8f385a6 948void __init __deprecated at91_init_serial(struct at91_uart_config *config)
86ad76bb
AV		 949{
950 int i;
951
952 /* Fill in list of supported UARTs */
953 for (i = 0; i < config->nr_tty; i++) {
954 switch (config->tty_map[i]) {
955 case 0:
c8f385a6 956 configure_usart0_pins(ATMEL_UART_CTS | ATMEL_UART_RTS);
86ad76bb
AV		 957 at91_uarts[i] = &at91sam9261_uart0_device;
958 at91_clock_associate("usart0_clk", &at91sam9261_uart0_device.dev, "usart");
959 break;
960 case 1:
c8f385a6 961 configure_usart1_pins(0);
86ad76bb
AV		 962 at91_uarts[i] = &at91sam9261_uart1_device;
963 at91_clock_associate("usart1_clk", &at91sam9261_uart1_device.dev, "usart");
964 break;
965 case 2:
c8f385a6 966 configure_usart2_pins(0);
86ad76bb
AV		 967 at91_uarts[i] = &at91sam9261_uart2_device;
968 at91_clock_associate("usart2_clk", &at91sam9261_uart2_device.dev, "usart");
969 break;
970 case 3:
971 configure_dbgu_pins();
972 at91_uarts[i] = &at91sam9261_dbgu_device;
973 at91_clock_associate("mck", &at91sam9261_dbgu_device.dev, "usart");
974 break;
975 default:
976 continue;
977 }
978 at91_uarts[i]->id = i; /* update ID number to mapped ID */
979 }
980
981 /* Set serial console device */
982 if (config->console_tty < ATMEL_MAX_UART)
983 atmel_default_console_device = at91_uarts[config->console_tty];
984 if (!atmel_default_console_device)
985 printk(KERN_INFO "AT91: No default serial console defined.\n");
986}
987
c8f385a6
AV		 988void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
989{
990 struct platform_device *pdev;
991
992 switch (id) {
993 case 0: /* DBGU */
994 pdev = &at91sam9261_dbgu_device;
995 configure_dbgu_pins();
996 at91_clock_associate("mck", &pdev->dev, "usart");
997 break;
998 case AT91SAM9261_ID_US0:
999 pdev = &at91sam9261_uart0_device;
1000 configure_usart0_pins(pins);
1001 at91_clock_associate("usart0_clk", &pdev->dev, "usart");
1002 break;
1003 case AT91SAM9261_ID_US1:
1004 pdev = &at91sam9261_uart1_device;
1005 configure_usart1_pins(pins);
1006 at91_clock_associate("usart1_clk", &pdev->dev, "usart");
1007 break;
1008 case AT91SAM9261_ID_US2:
1009 pdev = &at91sam9261_uart2_device;
1010 configure_usart2_pins(pins);
1011 at91_clock_associate("usart2_clk", &pdev->dev, "usart");
1012 break;
1013 default:
1014 return;
1015 }
1016 pdev->id = portnr; /* update to mapped ID */
1017
1018 if (portnr < ATMEL_MAX_UART)
1019 at91_uarts[portnr] = pdev;
1020}
1021
1022void __init at91_set_serial_console(unsigned portnr)
1023{
1024 if (portnr < ATMEL_MAX_UART)
1025 atmel_default_console_device = at91_uarts[portnr];
1026 if (!atmel_default_console_device)
1027 printk(KERN_INFO "AT91: No default serial console defined.\n");
1028}
1029
86ad76bb
AV		 1030void __init at91_add_device_serial(void)
1031{
1032 int i;
1033
1034 for (i = 0; i < ATMEL_MAX_UART; i++) {
1035 if (at91_uarts[i])
1036 platform_device_register(at91_uarts[i]);
1037 }
1038}
1039#else
c8f385a6
AV		 1040void __init __deprecated at91_init_serial(struct at91_uart_config *config) {}
1041void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1042void __init at91_set_serial_console(unsigned portnr) {}
86ad76bb
AV		 1043void __init at91_add_device_serial(void) {}
1044#endif
1045
1046
1047/* -------------------------------------------------------------------- */
1048
1049/*
1050 * These devices are always present and don't need any board-specific
1051 * setup.
1052 */
1053static int __init at91_add_standard_devices(void)
1054{
884f5a6a
AV		 1055 at91_add_device_rtt();
1056 at91_add_device_watchdog();
86ad76bb
AV		 1057 return 0;
1058}
1059
1060arch_initcall(at91_add_standard_devices);
Linux kernel - Deliverables
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