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86ad76bb | 1 | /* |
9d041268 | 2 | * arch/arm/mach-at91/at91sam9261_devices.c |
86ad76bb AV |
3 | * |
4 | * Copyright (C) 2005 Thibaut VARENE <varenet@parisc-linux.org> | |
5 | * Copyright (C) 2005 David Brownell | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | */ | |
13 | #include <asm/mach/arch.h> | |
14 | #include <asm/mach/map.h> | |
15 | ||
c6686ff9 | 16 | #include <linux/dma-mapping.h> |
86ad76bb | 17 | #include <linux/platform_device.h> |
f230d3f5 | 18 | #include <linux/i2c-gpio.h> |
86ad76bb | 19 | |
f230d3f5 | 20 | #include <linux/fb.h> |
b8b78609 JA |
21 | #include <video/atmel_lcdc.h> |
22 | ||
86ad76bb AV |
23 | #include <asm/arch/board.h> |
24 | #include <asm/arch/gpio.h> | |
25 | #include <asm/arch/at91sam9261.h> | |
26 | #include <asm/arch/at91sam9261_matrix.h> | |
b78eabde | 27 | #include <asm/arch/at91sam9_smc.h> |
86ad76bb AV |
28 | |
29 | #include "generic.h" | |
30 | ||
86ad76bb AV |
31 | |
32 | /* -------------------------------------------------------------------- | |
33 | * USB Host | |
34 | * -------------------------------------------------------------------- */ | |
35 | ||
36 | #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) | |
c6686ff9 | 37 | static u64 ohci_dmamask = DMA_BIT_MASK(32); |
86ad76bb AV |
38 | static struct at91_usbh_data usbh_data; |
39 | ||
40 | static struct resource usbh_resources[] = { | |
41 | [0] = { | |
42 | .start = AT91SAM9261_UHP_BASE, | |
43 | .end = AT91SAM9261_UHP_BASE + SZ_1M - 1, | |
44 | .flags = IORESOURCE_MEM, | |
45 | }, | |
46 | [1] = { | |
47 | .start = AT91SAM9261_ID_UHP, | |
48 | .end = AT91SAM9261_ID_UHP, | |
49 | .flags = IORESOURCE_IRQ, | |
50 | }, | |
51 | }; | |
52 | ||
53 | static struct platform_device at91sam9261_usbh_device = { | |
54 | .name = "at91_ohci", | |
55 | .id = -1, | |
56 | .dev = { | |
57 | .dma_mask = &ohci_dmamask, | |
c6686ff9 | 58 | .coherent_dma_mask = DMA_BIT_MASK(32), |
86ad76bb AV |
59 | .platform_data = &usbh_data, |
60 | }, | |
61 | .resource = usbh_resources, | |
62 | .num_resources = ARRAY_SIZE(usbh_resources), | |
63 | }; | |
64 | ||
65 | void __init at91_add_device_usbh(struct at91_usbh_data *data) | |
66 | { | |
67 | if (!data) | |
68 | return; | |
69 | ||
70 | usbh_data = *data; | |
71 | platform_device_register(&at91sam9261_usbh_device); | |
72 | } | |
73 | #else | |
74 | void __init at91_add_device_usbh(struct at91_usbh_data *data) {} | |
75 | #endif | |
76 | ||
77 | ||
78 | /* -------------------------------------------------------------------- | |
79 | * USB Device (Gadget) | |
80 | * -------------------------------------------------------------------- */ | |
81 | ||
82 | #ifdef CONFIG_USB_GADGET_AT91 | |
83 | static struct at91_udc_data udc_data; | |
84 | ||
85 | static struct resource udc_resources[] = { | |
86 | [0] = { | |
87 | .start = AT91SAM9261_BASE_UDP, | |
88 | .end = AT91SAM9261_BASE_UDP + SZ_16K - 1, | |
89 | .flags = IORESOURCE_MEM, | |
90 | }, | |
91 | [1] = { | |
92 | .start = AT91SAM9261_ID_UDP, | |
93 | .end = AT91SAM9261_ID_UDP, | |
94 | .flags = IORESOURCE_IRQ, | |
95 | }, | |
96 | }; | |
97 | ||
98 | static struct platform_device at91sam9261_udc_device = { | |
99 | .name = "at91_udc", | |
100 | .id = -1, | |
101 | .dev = { | |
102 | .platform_data = &udc_data, | |
103 | }, | |
104 | .resource = udc_resources, | |
105 | .num_resources = ARRAY_SIZE(udc_resources), | |
106 | }; | |
107 | ||
108 | void __init at91_add_device_udc(struct at91_udc_data *data) | |
109 | { | |
86ad76bb AV |
110 | if (!data) |
111 | return; | |
112 | ||
113 | if (data->vbus_pin) { | |
114 | at91_set_gpio_input(data->vbus_pin, 0); | |
115 | at91_set_deglitch(data->vbus_pin, 1); | |
116 | } | |
117 | ||
da7a42d6 | 118 | /* Pullup pin is handled internally by USB device peripheral */ |
86ad76bb AV |
119 | |
120 | udc_data = *data; | |
121 | platform_device_register(&at91sam9261_udc_device); | |
122 | } | |
123 | #else | |
124 | void __init at91_add_device_udc(struct at91_udc_data *data) {} | |
125 | #endif | |
126 | ||
127 | /* -------------------------------------------------------------------- | |
128 | * MMC / SD | |
129 | * -------------------------------------------------------------------- */ | |
130 | ||
131 | #if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE) | |
c6686ff9 | 132 | static u64 mmc_dmamask = DMA_BIT_MASK(32); |
86ad76bb AV |
133 | static struct at91_mmc_data mmc_data; |
134 | ||
135 | static struct resource mmc_resources[] = { | |
136 | [0] = { | |
137 | .start = AT91SAM9261_BASE_MCI, | |
138 | .end = AT91SAM9261_BASE_MCI + SZ_16K - 1, | |
139 | .flags = IORESOURCE_MEM, | |
140 | }, | |
141 | [1] = { | |
142 | .start = AT91SAM9261_ID_MCI, | |
143 | .end = AT91SAM9261_ID_MCI, | |
144 | .flags = IORESOURCE_IRQ, | |
145 | }, | |
146 | }; | |
147 | ||
148 | static struct platform_device at91sam9261_mmc_device = { | |
149 | .name = "at91_mci", | |
150 | .id = -1, | |
151 | .dev = { | |
152 | .dma_mask = &mmc_dmamask, | |
c6686ff9 | 153 | .coherent_dma_mask = DMA_BIT_MASK(32), |
86ad76bb AV |
154 | .platform_data = &mmc_data, |
155 | }, | |
156 | .resource = mmc_resources, | |
157 | .num_resources = ARRAY_SIZE(mmc_resources), | |
158 | }; | |
159 | ||
d0760b3b | 160 | void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) |
86ad76bb AV |
161 | { |
162 | if (!data) | |
163 | return; | |
164 | ||
165 | /* input/irq */ | |
166 | if (data->det_pin) { | |
167 | at91_set_gpio_input(data->det_pin, 1); | |
168 | at91_set_deglitch(data->det_pin, 1); | |
169 | } | |
170 | if (data->wp_pin) | |
171 | at91_set_gpio_input(data->wp_pin, 1); | |
172 | if (data->vcc_pin) | |
173 | at91_set_gpio_output(data->vcc_pin, 0); | |
174 | ||
175 | /* CLK */ | |
176 | at91_set_B_periph(AT91_PIN_PA2, 0); | |
177 | ||
178 | /* CMD */ | |
179 | at91_set_B_periph(AT91_PIN_PA1, 1); | |
180 | ||
181 | /* DAT0, maybe DAT1..DAT3 */ | |
182 | at91_set_B_periph(AT91_PIN_PA0, 1); | |
183 | if (data->wire4) { | |
184 | at91_set_B_periph(AT91_PIN_PA4, 1); | |
185 | at91_set_B_periph(AT91_PIN_PA5, 1); | |
186 | at91_set_B_periph(AT91_PIN_PA6, 1); | |
187 | } | |
188 | ||
189 | mmc_data = *data; | |
190 | platform_device_register(&at91sam9261_mmc_device); | |
191 | } | |
192 | #else | |
d0760b3b | 193 | void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {} |
86ad76bb AV |
194 | #endif |
195 | ||
196 | ||
197 | /* -------------------------------------------------------------------- | |
198 | * NAND / SmartMedia | |
199 | * -------------------------------------------------------------------- */ | |
200 | ||
201 | #if defined(CONFIG_MTD_NAND_AT91) || defined(CONFIG_MTD_NAND_AT91_MODULE) | |
202 | static struct at91_nand_data nand_data; | |
203 | ||
204 | #define NAND_BASE AT91_CHIPSELECT_3 | |
205 | ||
206 | static struct resource nand_resources[] = { | |
207 | { | |
208 | .start = NAND_BASE, | |
209 | .end = NAND_BASE + SZ_256M - 1, | |
210 | .flags = IORESOURCE_MEM, | |
211 | } | |
212 | }; | |
213 | ||
214 | static struct platform_device at91_nand_device = { | |
215 | .name = "at91_nand", | |
216 | .id = -1, | |
217 | .dev = { | |
218 | .platform_data = &nand_data, | |
219 | }, | |
220 | .resource = nand_resources, | |
221 | .num_resources = ARRAY_SIZE(nand_resources), | |
222 | }; | |
223 | ||
224 | void __init at91_add_device_nand(struct at91_nand_data *data) | |
225 | { | |
226 | unsigned long csa, mode; | |
227 | ||
228 | if (!data) | |
229 | return; | |
230 | ||
231 | csa = at91_sys_read(AT91_MATRIX_EBICSA); | |
22823558 | 232 | at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); |
86ad76bb AV |
233 | |
234 | /* set the bus interface characteristics */ | |
235 | at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) | |
236 | | AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0)); | |
237 | ||
238 | at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(2) | AT91_SMC_NCS_WRPULSE_(5) | |
239 | | AT91_SMC_NRDPULSE_(2) | AT91_SMC_NCS_RDPULSE_(5)); | |
240 | ||
241 | at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7)); | |
242 | ||
243 | if (data->bus_width_16) | |
244 | mode = AT91_SMC_DBW_16; | |
245 | else | |
246 | mode = AT91_SMC_DBW_8; | |
247 | at91_sys_write(AT91_SMC_MODE(3), mode | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(1)); | |
248 | ||
249 | /* enable pin */ | |
250 | if (data->enable_pin) | |
251 | at91_set_gpio_output(data->enable_pin, 1); | |
252 | ||
253 | /* ready/busy pin */ | |
254 | if (data->rdy_pin) | |
255 | at91_set_gpio_input(data->rdy_pin, 1); | |
256 | ||
257 | /* card detect pin */ | |
258 | if (data->det_pin) | |
259 | at91_set_gpio_input(data->det_pin, 1); | |
260 | ||
261 | at91_set_A_periph(AT91_PIN_PC0, 0); /* NANDOE */ | |
262 | at91_set_A_periph(AT91_PIN_PC1, 0); /* NANDWE */ | |
263 | ||
264 | nand_data = *data; | |
265 | platform_device_register(&at91_nand_device); | |
266 | } | |
267 | ||
268 | #else | |
269 | void __init at91_add_device_nand(struct at91_nand_data *data) {} | |
270 | #endif | |
271 | ||
272 | ||
273 | /* -------------------------------------------------------------------- | |
274 | * TWI (i2c) | |
275 | * -------------------------------------------------------------------- */ | |
276 | ||
f230d3f5 AV |
277 | /* |
278 | * Prefer the GPIO code since the TWI controller isn't robust | |
279 | * (gets overruns and underruns under load) and can only issue | |
280 | * repeated STARTs in one scenario (the driver doesn't yet handle them). | |
281 | */ | |
282 | #if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE) | |
283 | ||
284 | static struct i2c_gpio_platform_data pdata = { | |
285 | .sda_pin = AT91_PIN_PA7, | |
286 | .sda_is_open_drain = 1, | |
287 | .scl_pin = AT91_PIN_PA8, | |
288 | .scl_is_open_drain = 1, | |
289 | .udelay = 2, /* ~100 kHz */ | |
290 | }; | |
291 | ||
292 | static struct platform_device at91sam9261_twi_device = { | |
293 | .name = "i2c-gpio", | |
294 | .id = -1, | |
295 | .dev.platform_data = &pdata, | |
296 | }; | |
297 | ||
298 | void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) | |
299 | { | |
300 | at91_set_GPIO_periph(AT91_PIN_PA7, 1); /* TWD (SDA) */ | |
301 | at91_set_multi_drive(AT91_PIN_PA7, 1); | |
302 | ||
303 | at91_set_GPIO_periph(AT91_PIN_PA8, 1); /* TWCK (SCL) */ | |
304 | at91_set_multi_drive(AT91_PIN_PA8, 1); | |
305 | ||
306 | i2c_register_board_info(0, devices, nr_devices); | |
307 | platform_device_register(&at91sam9261_twi_device); | |
308 | } | |
309 | ||
310 | #elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE) | |
86ad76bb AV |
311 | |
312 | static struct resource twi_resources[] = { | |
313 | [0] = { | |
314 | .start = AT91SAM9261_BASE_TWI, | |
315 | .end = AT91SAM9261_BASE_TWI + SZ_16K - 1, | |
316 | .flags = IORESOURCE_MEM, | |
317 | }, | |
318 | [1] = { | |
319 | .start = AT91SAM9261_ID_TWI, | |
320 | .end = AT91SAM9261_ID_TWI, | |
321 | .flags = IORESOURCE_IRQ, | |
322 | }, | |
323 | }; | |
324 | ||
325 | static struct platform_device at91sam9261_twi_device = { | |
326 | .name = "at91_i2c", | |
327 | .id = -1, | |
328 | .resource = twi_resources, | |
329 | .num_resources = ARRAY_SIZE(twi_resources), | |
330 | }; | |
331 | ||
f230d3f5 | 332 | void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) |
86ad76bb AV |
333 | { |
334 | /* pins used for TWI interface */ | |
335 | at91_set_A_periph(AT91_PIN_PA7, 0); /* TWD */ | |
336 | at91_set_multi_drive(AT91_PIN_PA7, 1); | |
337 | ||
338 | at91_set_A_periph(AT91_PIN_PA8, 0); /* TWCK */ | |
339 | at91_set_multi_drive(AT91_PIN_PA8, 1); | |
340 | ||
f230d3f5 | 341 | i2c_register_board_info(0, devices, nr_devices); |
86ad76bb AV |
342 | platform_device_register(&at91sam9261_twi_device); |
343 | } | |
344 | #else | |
f230d3f5 | 345 | void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {} |
86ad76bb AV |
346 | #endif |
347 | ||
348 | ||
349 | /* -------------------------------------------------------------------- | |
350 | * SPI | |
351 | * -------------------------------------------------------------------- */ | |
352 | ||
353 | #if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE) | |
c6686ff9 | 354 | static u64 spi_dmamask = DMA_BIT_MASK(32); |
86ad76bb AV |
355 | |
356 | static struct resource spi0_resources[] = { | |
357 | [0] = { | |
358 | .start = AT91SAM9261_BASE_SPI0, | |
359 | .end = AT91SAM9261_BASE_SPI0 + SZ_16K - 1, | |
360 | .flags = IORESOURCE_MEM, | |
361 | }, | |
362 | [1] = { | |
363 | .start = AT91SAM9261_ID_SPI0, | |
364 | .end = AT91SAM9261_ID_SPI0, | |
365 | .flags = IORESOURCE_IRQ, | |
366 | }, | |
367 | }; | |
368 | ||
369 | static struct platform_device at91sam9261_spi0_device = { | |
370 | .name = "atmel_spi", | |
371 | .id = 0, | |
372 | .dev = { | |
373 | .dma_mask = &spi_dmamask, | |
c6686ff9 | 374 | .coherent_dma_mask = DMA_BIT_MASK(32), |
86ad76bb AV |
375 | }, |
376 | .resource = spi0_resources, | |
377 | .num_resources = ARRAY_SIZE(spi0_resources), | |
378 | }; | |
379 | ||
380 | static const unsigned spi0_standard_cs[4] = { AT91_PIN_PA3, AT91_PIN_PA4, AT91_PIN_PA5, AT91_PIN_PA6 }; | |
381 | ||
382 | static struct resource spi1_resources[] = { | |
383 | [0] = { | |
384 | .start = AT91SAM9261_BASE_SPI1, | |
385 | .end = AT91SAM9261_BASE_SPI1 + SZ_16K - 1, | |
386 | .flags = IORESOURCE_MEM, | |
387 | }, | |
388 | [1] = { | |
389 | .start = AT91SAM9261_ID_SPI1, | |
390 | .end = AT91SAM9261_ID_SPI1, | |
391 | .flags = IORESOURCE_IRQ, | |
392 | }, | |
393 | }; | |
394 | ||
395 | static struct platform_device at91sam9261_spi1_device = { | |
396 | .name = "atmel_spi", | |
397 | .id = 1, | |
398 | .dev = { | |
399 | .dma_mask = &spi_dmamask, | |
c6686ff9 | 400 | .coherent_dma_mask = DMA_BIT_MASK(32), |
86ad76bb AV |
401 | }, |
402 | .resource = spi1_resources, | |
403 | .num_resources = ARRAY_SIZE(spi1_resources), | |
404 | }; | |
405 | ||
406 | static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB28, AT91_PIN_PA24, AT91_PIN_PA25, AT91_PIN_PA26 }; | |
407 | ||
408 | void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) | |
409 | { | |
410 | int i; | |
411 | unsigned long cs_pin; | |
412 | short enable_spi0 = 0; | |
413 | short enable_spi1 = 0; | |
414 | ||
415 | /* Choose SPI chip-selects */ | |
416 | for (i = 0; i < nr_devices; i++) { | |
417 | if (devices[i].controller_data) | |
418 | cs_pin = (unsigned long) devices[i].controller_data; | |
419 | else if (devices[i].bus_num == 0) | |
420 | cs_pin = spi0_standard_cs[devices[i].chip_select]; | |
421 | else | |
422 | cs_pin = spi1_standard_cs[devices[i].chip_select]; | |
423 | ||
424 | if (devices[i].bus_num == 0) | |
425 | enable_spi0 = 1; | |
426 | else | |
427 | enable_spi1 = 1; | |
428 | ||
429 | /* enable chip-select pin */ | |
430 | at91_set_gpio_output(cs_pin, 1); | |
431 | ||
432 | /* pass chip-select pin to driver */ | |
433 | devices[i].controller_data = (void *) cs_pin; | |
434 | } | |
435 | ||
436 | spi_register_board_info(devices, nr_devices); | |
437 | ||
438 | /* Configure SPI bus(es) */ | |
439 | if (enable_spi0) { | |
440 | at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */ | |
441 | at91_set_A_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */ | |
442 | at91_set_A_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */ | |
443 | ||
444 | at91_clock_associate("spi0_clk", &at91sam9261_spi0_device.dev, "spi_clk"); | |
445 | platform_device_register(&at91sam9261_spi0_device); | |
446 | } | |
447 | if (enable_spi1) { | |
448 | at91_set_A_periph(AT91_PIN_PB30, 0); /* SPI1_MISO */ | |
449 | at91_set_A_periph(AT91_PIN_PB31, 0); /* SPI1_MOSI */ | |
450 | at91_set_A_periph(AT91_PIN_PB29, 0); /* SPI1_SPCK */ | |
451 | ||
452 | at91_clock_associate("spi1_clk", &at91sam9261_spi1_device.dev, "spi_clk"); | |
453 | platform_device_register(&at91sam9261_spi1_device); | |
454 | } | |
455 | } | |
456 | #else | |
457 | void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {} | |
458 | #endif | |
459 | ||
460 | ||
461 | /* -------------------------------------------------------------------- | |
462 | * LCD Controller | |
463 | * -------------------------------------------------------------------- */ | |
464 | ||
7776a94c | 465 | #if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE) |
c6686ff9 | 466 | static u64 lcdc_dmamask = DMA_BIT_MASK(32); |
7776a94c | 467 | static struct atmel_lcdfb_info lcdc_data; |
86ad76bb AV |
468 | |
469 | static struct resource lcdc_resources[] = { | |
470 | [0] = { | |
471 | .start = AT91SAM9261_LCDC_BASE, | |
472 | .end = AT91SAM9261_LCDC_BASE + SZ_4K - 1, | |
473 | .flags = IORESOURCE_MEM, | |
474 | }, | |
475 | [1] = { | |
476 | .start = AT91SAM9261_ID_LCDC, | |
477 | .end = AT91SAM9261_ID_LCDC, | |
478 | .flags = IORESOURCE_IRQ, | |
479 | }, | |
480 | #if defined(CONFIG_FB_INTSRAM) | |
481 | [2] = { | |
482 | .start = AT91SAM9261_SRAM_BASE, | |
483 | .end = AT91SAM9261_SRAM_BASE + AT91SAM9261_SRAM_SIZE - 1, | |
484 | .flags = IORESOURCE_MEM, | |
485 | }, | |
486 | #endif | |
487 | }; | |
488 | ||
489 | static struct platform_device at91_lcdc_device = { | |
7776a94c | 490 | .name = "atmel_lcdfb", |
86ad76bb AV |
491 | .id = 0, |
492 | .dev = { | |
493 | .dma_mask = &lcdc_dmamask, | |
c6686ff9 | 494 | .coherent_dma_mask = DMA_BIT_MASK(32), |
86ad76bb AV |
495 | .platform_data = &lcdc_data, |
496 | }, | |
497 | .resource = lcdc_resources, | |
498 | .num_resources = ARRAY_SIZE(lcdc_resources), | |
499 | }; | |
500 | ||
7776a94c | 501 | void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) |
86ad76bb AV |
502 | { |
503 | if (!data) { | |
504 | return; | |
505 | } | |
506 | ||
f06e656f AV |
507 | #if defined(CONFIG_FB_ATMEL_STN) |
508 | at91_set_A_periph(AT91_PIN_PB0, 0); /* LCDVSYNC */ | |
509 | at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */ | |
510 | at91_set_A_periph(AT91_PIN_PB2, 0); /* LCDDOTCK */ | |
511 | at91_set_A_periph(AT91_PIN_PB3, 0); /* LCDDEN */ | |
512 | at91_set_A_periph(AT91_PIN_PB4, 0); /* LCDCC */ | |
513 | at91_set_A_periph(AT91_PIN_PB5, 0); /* LCDD0 */ | |
514 | at91_set_A_periph(AT91_PIN_PB6, 0); /* LCDD1 */ | |
515 | at91_set_A_periph(AT91_PIN_PB7, 0); /* LCDD2 */ | |
516 | at91_set_A_periph(AT91_PIN_PB8, 0); /* LCDD3 */ | |
517 | #else | |
86ad76bb AV |
518 | at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */ |
519 | at91_set_A_periph(AT91_PIN_PB2, 0); /* LCDDOTCK */ | |
520 | at91_set_A_periph(AT91_PIN_PB3, 0); /* LCDDEN */ | |
521 | at91_set_A_periph(AT91_PIN_PB4, 0); /* LCDCC */ | |
522 | at91_set_A_periph(AT91_PIN_PB7, 0); /* LCDD2 */ | |
523 | at91_set_A_periph(AT91_PIN_PB8, 0); /* LCDD3 */ | |
524 | at91_set_A_periph(AT91_PIN_PB9, 0); /* LCDD4 */ | |
525 | at91_set_A_periph(AT91_PIN_PB10, 0); /* LCDD5 */ | |
526 | at91_set_A_periph(AT91_PIN_PB11, 0); /* LCDD6 */ | |
527 | at91_set_A_periph(AT91_PIN_PB12, 0); /* LCDD7 */ | |
528 | at91_set_A_periph(AT91_PIN_PB15, 0); /* LCDD10 */ | |
529 | at91_set_A_periph(AT91_PIN_PB16, 0); /* LCDD11 */ | |
530 | at91_set_A_periph(AT91_PIN_PB17, 0); /* LCDD12 */ | |
531 | at91_set_A_periph(AT91_PIN_PB18, 0); /* LCDD13 */ | |
532 | at91_set_A_periph(AT91_PIN_PB19, 0); /* LCDD14 */ | |
533 | at91_set_A_periph(AT91_PIN_PB20, 0); /* LCDD15 */ | |
534 | at91_set_B_periph(AT91_PIN_PB23, 0); /* LCDD18 */ | |
535 | at91_set_B_periph(AT91_PIN_PB24, 0); /* LCDD19 */ | |
536 | at91_set_B_periph(AT91_PIN_PB25, 0); /* LCDD20 */ | |
537 | at91_set_B_periph(AT91_PIN_PB26, 0); /* LCDD21 */ | |
538 | at91_set_B_periph(AT91_PIN_PB27, 0); /* LCDD22 */ | |
539 | at91_set_B_periph(AT91_PIN_PB28, 0); /* LCDD23 */ | |
f06e656f | 540 | #endif |
86ad76bb | 541 | |
01d3a5e7 HS |
542 | if (ARRAY_SIZE(lcdc_resources) > 2) { |
543 | void __iomem *fb; | |
544 | struct resource *fb_res = &lcdc_resources[2]; | |
545 | size_t fb_len = fb_res->end - fb_res->start + 1; | |
546 | ||
547 | fb = ioremap_writecombine(fb_res->start, fb_len); | |
548 | if (fb) { | |
549 | memset(fb, 0, fb_len); | |
550 | iounmap(fb, fb_len); | |
551 | } | |
552 | } | |
86ad76bb AV |
553 | lcdc_data = *data; |
554 | platform_device_register(&at91_lcdc_device); | |
555 | } | |
556 | #else | |
7776a94c | 557 | void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {} |
86ad76bb AV |
558 | #endif |
559 | ||
560 | ||
e5f40bfa AV |
561 | /* -------------------------------------------------------------------- |
562 | * Timer/Counter block | |
563 | * -------------------------------------------------------------------- */ | |
564 | ||
565 | #ifdef CONFIG_ATMEL_TCLIB | |
566 | ||
567 | static struct resource tcb_resources[] = { | |
568 | [0] = { | |
569 | .start = AT91SAM9261_BASE_TCB0, | |
570 | .end = AT91SAM9261_BASE_TCB0 + SZ_16K - 1, | |
571 | .flags = IORESOURCE_MEM, | |
572 | }, | |
573 | [1] = { | |
574 | .start = AT91SAM9261_ID_TC0, | |
575 | .end = AT91SAM9261_ID_TC0, | |
576 | .flags = IORESOURCE_IRQ, | |
577 | }, | |
578 | [2] = { | |
579 | .start = AT91SAM9261_ID_TC1, | |
580 | .end = AT91SAM9261_ID_TC1, | |
581 | .flags = IORESOURCE_IRQ, | |
582 | }, | |
583 | [3] = { | |
584 | .start = AT91SAM9261_ID_TC2, | |
585 | .end = AT91SAM9261_ID_TC2, | |
586 | .flags = IORESOURCE_IRQ, | |
587 | }, | |
588 | }; | |
589 | ||
590 | static struct platform_device at91sam9261_tcb_device = { | |
591 | .name = "atmel_tcb", | |
592 | .id = 0, | |
593 | .resource = tcb_resources, | |
594 | .num_resources = ARRAY_SIZE(tcb_resources), | |
595 | }; | |
596 | ||
597 | static void __init at91_add_device_tc(void) | |
598 | { | |
599 | /* this chip has a separate clock and irq for each TC channel */ | |
600 | at91_clock_associate("tc0_clk", &at91sam9261_tcb_device.dev, "t0_clk"); | |
601 | at91_clock_associate("tc1_clk", &at91sam9261_tcb_device.dev, "t1_clk"); | |
602 | at91_clock_associate("tc2_clk", &at91sam9261_tcb_device.dev, "t2_clk"); | |
603 | platform_device_register(&at91sam9261_tcb_device); | |
604 | } | |
605 | #else | |
606 | static void __init at91_add_device_tc(void) { } | |
607 | #endif | |
608 | ||
609 | ||
884f5a6a AV |
610 | /* -------------------------------------------------------------------- |
611 | * RTT | |
612 | * -------------------------------------------------------------------- */ | |
613 | ||
614 | static struct resource rtt_resources[] = { | |
615 | { | |
616 | .start = AT91_BASE_SYS + AT91_RTT, | |
617 | .end = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1, | |
618 | .flags = IORESOURCE_MEM, | |
619 | } | |
620 | }; | |
621 | ||
622 | static struct platform_device at91sam9261_rtt_device = { | |
623 | .name = "at91_rtt", | |
4fd9212c | 624 | .id = 0, |
884f5a6a AV |
625 | .resource = rtt_resources, |
626 | .num_resources = ARRAY_SIZE(rtt_resources), | |
627 | }; | |
628 | ||
629 | static void __init at91_add_device_rtt(void) | |
630 | { | |
631 | platform_device_register(&at91sam9261_rtt_device); | |
632 | } | |
633 | ||
634 | ||
635 | /* -------------------------------------------------------------------- | |
636 | * Watchdog | |
637 | * -------------------------------------------------------------------- */ | |
638 | ||
639 | #if defined(CONFIG_AT91SAM9_WATCHDOG) || defined(CONFIG_AT91SAM9_WATCHDOG_MODULE) | |
640 | static struct platform_device at91sam9261_wdt_device = { | |
641 | .name = "at91_wdt", | |
642 | .id = -1, | |
643 | .num_resources = 0, | |
644 | }; | |
645 | ||
646 | static void __init at91_add_device_watchdog(void) | |
647 | { | |
648 | platform_device_register(&at91sam9261_wdt_device); | |
649 | } | |
650 | #else | |
651 | static void __init at91_add_device_watchdog(void) {} | |
652 | #endif | |
653 | ||
654 | ||
bfbc3266 AV |
655 | /* -------------------------------------------------------------------- |
656 | * SSC -- Synchronous Serial Controller | |
657 | * -------------------------------------------------------------------- */ | |
658 | ||
659 | #if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE) | |
660 | static u64 ssc0_dmamask = DMA_BIT_MASK(32); | |
661 | ||
662 | static struct resource ssc0_resources[] = { | |
663 | [0] = { | |
664 | .start = AT91SAM9261_BASE_SSC0, | |
665 | .end = AT91SAM9261_BASE_SSC0 + SZ_16K - 1, | |
666 | .flags = IORESOURCE_MEM, | |
667 | }, | |
668 | [1] = { | |
669 | .start = AT91SAM9261_ID_SSC0, | |
670 | .end = AT91SAM9261_ID_SSC0, | |
671 | .flags = IORESOURCE_IRQ, | |
672 | }, | |
673 | }; | |
674 | ||
675 | static struct platform_device at91sam9261_ssc0_device = { | |
676 | .name = "ssc", | |
677 | .id = 0, | |
678 | .dev = { | |
679 | .dma_mask = &ssc0_dmamask, | |
680 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
681 | }, | |
682 | .resource = ssc0_resources, | |
683 | .num_resources = ARRAY_SIZE(ssc0_resources), | |
684 | }; | |
685 | ||
686 | static inline void configure_ssc0_pins(unsigned pins) | |
687 | { | |
688 | if (pins & ATMEL_SSC_TF) | |
689 | at91_set_A_periph(AT91_PIN_PB21, 1); | |
690 | if (pins & ATMEL_SSC_TK) | |
691 | at91_set_A_periph(AT91_PIN_PB22, 1); | |
692 | if (pins & ATMEL_SSC_TD) | |
693 | at91_set_A_periph(AT91_PIN_PB23, 1); | |
694 | if (pins & ATMEL_SSC_RD) | |
695 | at91_set_A_periph(AT91_PIN_PB24, 1); | |
696 | if (pins & ATMEL_SSC_RK) | |
697 | at91_set_A_periph(AT91_PIN_PB25, 1); | |
698 | if (pins & ATMEL_SSC_RF) | |
699 | at91_set_A_periph(AT91_PIN_PB26, 1); | |
700 | } | |
701 | ||
702 | static u64 ssc1_dmamask = DMA_BIT_MASK(32); | |
703 | ||
704 | static struct resource ssc1_resources[] = { | |
705 | [0] = { | |
706 | .start = AT91SAM9261_BASE_SSC1, | |
707 | .end = AT91SAM9261_BASE_SSC1 + SZ_16K - 1, | |
708 | .flags = IORESOURCE_MEM, | |
709 | }, | |
710 | [1] = { | |
711 | .start = AT91SAM9261_ID_SSC1, | |
712 | .end = AT91SAM9261_ID_SSC1, | |
713 | .flags = IORESOURCE_IRQ, | |
714 | }, | |
715 | }; | |
716 | ||
717 | static struct platform_device at91sam9261_ssc1_device = { | |
718 | .name = "ssc", | |
719 | .id = 1, | |
720 | .dev = { | |
721 | .dma_mask = &ssc1_dmamask, | |
722 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
723 | }, | |
724 | .resource = ssc1_resources, | |
725 | .num_resources = ARRAY_SIZE(ssc1_resources), | |
726 | }; | |
727 | ||
728 | static inline void configure_ssc1_pins(unsigned pins) | |
729 | { | |
730 | if (pins & ATMEL_SSC_TF) | |
731 | at91_set_B_periph(AT91_PIN_PA17, 1); | |
732 | if (pins & ATMEL_SSC_TK) | |
733 | at91_set_B_periph(AT91_PIN_PA18, 1); | |
734 | if (pins & ATMEL_SSC_TD) | |
735 | at91_set_B_periph(AT91_PIN_PA19, 1); | |
736 | if (pins & ATMEL_SSC_RD) | |
737 | at91_set_B_periph(AT91_PIN_PA20, 1); | |
738 | if (pins & ATMEL_SSC_RK) | |
739 | at91_set_B_periph(AT91_PIN_PA21, 1); | |
740 | if (pins & ATMEL_SSC_RF) | |
741 | at91_set_B_periph(AT91_PIN_PA22, 1); | |
742 | } | |
743 | ||
744 | static u64 ssc2_dmamask = DMA_BIT_MASK(32); | |
745 | ||
746 | static struct resource ssc2_resources[] = { | |
747 | [0] = { | |
748 | .start = AT91SAM9261_BASE_SSC2, | |
749 | .end = AT91SAM9261_BASE_SSC2 + SZ_16K - 1, | |
750 | .flags = IORESOURCE_MEM, | |
751 | }, | |
752 | [1] = { | |
753 | .start = AT91SAM9261_ID_SSC2, | |
754 | .end = AT91SAM9261_ID_SSC2, | |
755 | .flags = IORESOURCE_IRQ, | |
756 | }, | |
757 | }; | |
758 | ||
759 | static struct platform_device at91sam9261_ssc2_device = { | |
760 | .name = "ssc", | |
761 | .id = 2, | |
762 | .dev = { | |
763 | .dma_mask = &ssc2_dmamask, | |
764 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
765 | }, | |
766 | .resource = ssc2_resources, | |
767 | .num_resources = ARRAY_SIZE(ssc2_resources), | |
768 | }; | |
769 | ||
770 | static inline void configure_ssc2_pins(unsigned pins) | |
771 | { | |
772 | if (pins & ATMEL_SSC_TF) | |
773 | at91_set_B_periph(AT91_PIN_PC25, 1); | |
774 | if (pins & ATMEL_SSC_TK) | |
775 | at91_set_B_periph(AT91_PIN_PC26, 1); | |
776 | if (pins & ATMEL_SSC_TD) | |
777 | at91_set_B_periph(AT91_PIN_PC27, 1); | |
778 | if (pins & ATMEL_SSC_RD) | |
779 | at91_set_B_periph(AT91_PIN_PC28, 1); | |
780 | if (pins & ATMEL_SSC_RK) | |
781 | at91_set_B_periph(AT91_PIN_PC29, 1); | |
782 | if (pins & ATMEL_SSC_RF) | |
783 | at91_set_B_periph(AT91_PIN_PC30, 1); | |
784 | } | |
785 | ||
786 | /* | |
787 | * SSC controllers are accessed through library code, instead of any | |
788 | * kind of all-singing/all-dancing driver. For example one could be | |
789 | * used by a particular I2S audio codec's driver, while another one | |
790 | * on the same system might be used by a custom data capture driver. | |
791 | */ | |
792 | void __init at91_add_device_ssc(unsigned id, unsigned pins) | |
793 | { | |
794 | struct platform_device *pdev; | |
795 | ||
796 | /* | |
797 | * NOTE: caller is responsible for passing information matching | |
798 | * "pins" to whatever will be using each particular controller. | |
799 | */ | |
800 | switch (id) { | |
801 | case AT91SAM9261_ID_SSC0: | |
802 | pdev = &at91sam9261_ssc0_device; | |
803 | configure_ssc0_pins(pins); | |
804 | at91_clock_associate("ssc0_clk", &pdev->dev, "pclk"); | |
805 | break; | |
806 | case AT91SAM9261_ID_SSC1: | |
807 | pdev = &at91sam9261_ssc1_device; | |
808 | configure_ssc1_pins(pins); | |
809 | at91_clock_associate("ssc1_clk", &pdev->dev, "pclk"); | |
810 | break; | |
811 | case AT91SAM9261_ID_SSC2: | |
812 | pdev = &at91sam9261_ssc2_device; | |
813 | configure_ssc2_pins(pins); | |
814 | at91_clock_associate("ssc2_clk", &pdev->dev, "pclk"); | |
815 | break; | |
816 | default: | |
817 | return; | |
818 | } | |
819 | ||
820 | platform_device_register(pdev); | |
821 | } | |
822 | ||
823 | #else | |
824 | void __init at91_add_device_ssc(unsigned id, unsigned pins) {} | |
825 | #endif | |
826 | ||
827 | ||
86ad76bb AV |
828 | /* -------------------------------------------------------------------- |
829 | * UART | |
830 | * -------------------------------------------------------------------- */ | |
831 | ||
832 | #if defined(CONFIG_SERIAL_ATMEL) | |
833 | static struct resource dbgu_resources[] = { | |
834 | [0] = { | |
835 | .start = AT91_VA_BASE_SYS + AT91_DBGU, | |
836 | .end = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1, | |
837 | .flags = IORESOURCE_MEM, | |
838 | }, | |
839 | [1] = { | |
840 | .start = AT91_ID_SYS, | |
841 | .end = AT91_ID_SYS, | |
842 | .flags = IORESOURCE_IRQ, | |
843 | }, | |
844 | }; | |
845 | ||
846 | static struct atmel_uart_data dbgu_data = { | |
847 | .use_dma_tx = 0, | |
848 | .use_dma_rx = 0, /* DBGU not capable of receive DMA */ | |
849 | .regs = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU), | |
850 | }; | |
851 | ||
c6686ff9 AV |
852 | static u64 dbgu_dmamask = DMA_BIT_MASK(32); |
853 | ||
86ad76bb AV |
854 | static struct platform_device at91sam9261_dbgu_device = { |
855 | .name = "atmel_usart", | |
856 | .id = 0, | |
857 | .dev = { | |
c6686ff9 AV |
858 | .dma_mask = &dbgu_dmamask, |
859 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
860 | .platform_data = &dbgu_data, | |
86ad76bb AV |
861 | }, |
862 | .resource = dbgu_resources, | |
863 | .num_resources = ARRAY_SIZE(dbgu_resources), | |
864 | }; | |
865 | ||
866 | static inline void configure_dbgu_pins(void) | |
867 | { | |
868 | at91_set_A_periph(AT91_PIN_PA9, 0); /* DRXD */ | |
869 | at91_set_A_periph(AT91_PIN_PA10, 1); /* DTXD */ | |
870 | } | |
871 | ||
872 | static struct resource uart0_resources[] = { | |
873 | [0] = { | |
874 | .start = AT91SAM9261_BASE_US0, | |
875 | .end = AT91SAM9261_BASE_US0 + SZ_16K - 1, | |
876 | .flags = IORESOURCE_MEM, | |
877 | }, | |
878 | [1] = { | |
879 | .start = AT91SAM9261_ID_US0, | |
880 | .end = AT91SAM9261_ID_US0, | |
881 | .flags = IORESOURCE_IRQ, | |
882 | }, | |
883 | }; | |
884 | ||
885 | static struct atmel_uart_data uart0_data = { | |
886 | .use_dma_tx = 1, | |
887 | .use_dma_rx = 1, | |
888 | }; | |
889 | ||
c6686ff9 AV |
890 | static u64 uart0_dmamask = DMA_BIT_MASK(32); |
891 | ||
86ad76bb AV |
892 | static struct platform_device at91sam9261_uart0_device = { |
893 | .name = "atmel_usart", | |
894 | .id = 1, | |
895 | .dev = { | |
c6686ff9 AV |
896 | .dma_mask = &uart0_dmamask, |
897 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
898 | .platform_data = &uart0_data, | |
86ad76bb AV |
899 | }, |
900 | .resource = uart0_resources, | |
901 | .num_resources = ARRAY_SIZE(uart0_resources), | |
902 | }; | |
903 | ||
c8f385a6 | 904 | static inline void configure_usart0_pins(unsigned pins) |
86ad76bb AV |
905 | { |
906 | at91_set_A_periph(AT91_PIN_PC8, 1); /* TXD0 */ | |
907 | at91_set_A_periph(AT91_PIN_PC9, 0); /* RXD0 */ | |
c8f385a6 AV |
908 | |
909 | if (pins & ATMEL_UART_RTS) | |
910 | at91_set_A_periph(AT91_PIN_PC10, 0); /* RTS0 */ | |
911 | if (pins & ATMEL_UART_CTS) | |
912 | at91_set_A_periph(AT91_PIN_PC11, 0); /* CTS0 */ | |
86ad76bb AV |
913 | } |
914 | ||
915 | static struct resource uart1_resources[] = { | |
916 | [0] = { | |
917 | .start = AT91SAM9261_BASE_US1, | |
918 | .end = AT91SAM9261_BASE_US1 + SZ_16K - 1, | |
919 | .flags = IORESOURCE_MEM, | |
920 | }, | |
921 | [1] = { | |
922 | .start = AT91SAM9261_ID_US1, | |
923 | .end = AT91SAM9261_ID_US1, | |
924 | .flags = IORESOURCE_IRQ, | |
925 | }, | |
926 | }; | |
927 | ||
928 | static struct atmel_uart_data uart1_data = { | |
929 | .use_dma_tx = 1, | |
930 | .use_dma_rx = 1, | |
931 | }; | |
932 | ||
c6686ff9 AV |
933 | static u64 uart1_dmamask = DMA_BIT_MASK(32); |
934 | ||
86ad76bb AV |
935 | static struct platform_device at91sam9261_uart1_device = { |
936 | .name = "atmel_usart", | |
937 | .id = 2, | |
938 | .dev = { | |
c6686ff9 AV |
939 | .dma_mask = &uart1_dmamask, |
940 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
941 | .platform_data = &uart1_data, | |
86ad76bb AV |
942 | }, |
943 | .resource = uart1_resources, | |
944 | .num_resources = ARRAY_SIZE(uart1_resources), | |
945 | }; | |
946 | ||
c8f385a6 | 947 | static inline void configure_usart1_pins(unsigned pins) |
86ad76bb AV |
948 | { |
949 | at91_set_A_periph(AT91_PIN_PC12, 1); /* TXD1 */ | |
950 | at91_set_A_periph(AT91_PIN_PC13, 0); /* RXD1 */ | |
c8f385a6 AV |
951 | |
952 | if (pins & ATMEL_UART_RTS) | |
953 | at91_set_B_periph(AT91_PIN_PA12, 0); /* RTS1 */ | |
954 | if (pins & ATMEL_UART_CTS) | |
955 | at91_set_B_periph(AT91_PIN_PA13, 0); /* CTS1 */ | |
86ad76bb AV |
956 | } |
957 | ||
958 | static struct resource uart2_resources[] = { | |
959 | [0] = { | |
960 | .start = AT91SAM9261_BASE_US2, | |
961 | .end = AT91SAM9261_BASE_US2 + SZ_16K - 1, | |
962 | .flags = IORESOURCE_MEM, | |
963 | }, | |
964 | [1] = { | |
965 | .start = AT91SAM9261_ID_US2, | |
966 | .end = AT91SAM9261_ID_US2, | |
967 | .flags = IORESOURCE_IRQ, | |
968 | }, | |
969 | }; | |
970 | ||
971 | static struct atmel_uart_data uart2_data = { | |
972 | .use_dma_tx = 1, | |
973 | .use_dma_rx = 1, | |
974 | }; | |
975 | ||
c6686ff9 AV |
976 | static u64 uart2_dmamask = DMA_BIT_MASK(32); |
977 | ||
86ad76bb AV |
978 | static struct platform_device at91sam9261_uart2_device = { |
979 | .name = "atmel_usart", | |
980 | .id = 3, | |
981 | .dev = { | |
c6686ff9 AV |
982 | .dma_mask = &uart2_dmamask, |
983 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
984 | .platform_data = &uart2_data, | |
86ad76bb AV |
985 | }, |
986 | .resource = uart2_resources, | |
987 | .num_resources = ARRAY_SIZE(uart2_resources), | |
988 | }; | |
989 | ||
c8f385a6 | 990 | static inline void configure_usart2_pins(unsigned pins) |
86ad76bb AV |
991 | { |
992 | at91_set_A_periph(AT91_PIN_PC15, 0); /* RXD2 */ | |
993 | at91_set_A_periph(AT91_PIN_PC14, 1); /* TXD2 */ | |
c8f385a6 AV |
994 | |
995 | if (pins & ATMEL_UART_RTS) | |
996 | at91_set_B_periph(AT91_PIN_PA15, 0); /* RTS2*/ | |
997 | if (pins & ATMEL_UART_CTS) | |
998 | at91_set_B_periph(AT91_PIN_PA16, 0); /* CTS2 */ | |
86ad76bb AV |
999 | } |
1000 | ||
11aadac4 | 1001 | static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */ |
86ad76bb AV |
1002 | struct platform_device *atmel_default_console_device; /* the serial console device */ |
1003 | ||
c8f385a6 AV |
1004 | void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) |
1005 | { | |
1006 | struct platform_device *pdev; | |
1007 | ||
1008 | switch (id) { | |
1009 | case 0: /* DBGU */ | |
1010 | pdev = &at91sam9261_dbgu_device; | |
1011 | configure_dbgu_pins(); | |
1012 | at91_clock_associate("mck", &pdev->dev, "usart"); | |
1013 | break; | |
1014 | case AT91SAM9261_ID_US0: | |
1015 | pdev = &at91sam9261_uart0_device; | |
1016 | configure_usart0_pins(pins); | |
1017 | at91_clock_associate("usart0_clk", &pdev->dev, "usart"); | |
1018 | break; | |
1019 | case AT91SAM9261_ID_US1: | |
1020 | pdev = &at91sam9261_uart1_device; | |
1021 | configure_usart1_pins(pins); | |
1022 | at91_clock_associate("usart1_clk", &pdev->dev, "usart"); | |
1023 | break; | |
1024 | case AT91SAM9261_ID_US2: | |
1025 | pdev = &at91sam9261_uart2_device; | |
1026 | configure_usart2_pins(pins); | |
1027 | at91_clock_associate("usart2_clk", &pdev->dev, "usart"); | |
1028 | break; | |
1029 | default: | |
1030 | return; | |
1031 | } | |
1032 | pdev->id = portnr; /* update to mapped ID */ | |
1033 | ||
1034 | if (portnr < ATMEL_MAX_UART) | |
1035 | at91_uarts[portnr] = pdev; | |
1036 | } | |
1037 | ||
1038 | void __init at91_set_serial_console(unsigned portnr) | |
1039 | { | |
1040 | if (portnr < ATMEL_MAX_UART) | |
1041 | atmel_default_console_device = at91_uarts[portnr]; | |
c8f385a6 AV |
1042 | } |
1043 | ||
86ad76bb AV |
1044 | void __init at91_add_device_serial(void) |
1045 | { | |
1046 | int i; | |
1047 | ||
1048 | for (i = 0; i < ATMEL_MAX_UART; i++) { | |
1049 | if (at91_uarts[i]) | |
1050 | platform_device_register(at91_uarts[i]); | |
1051 | } | |
11aadac4 AV |
1052 | |
1053 | if (!atmel_default_console_device) | |
1054 | printk(KERN_INFO "AT91: No default serial console defined.\n"); | |
86ad76bb AV |
1055 | } |
1056 | #else | |
c8f385a6 AV |
1057 | void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {} |
1058 | void __init at91_set_serial_console(unsigned portnr) {} | |
86ad76bb AV |
1059 | void __init at91_add_device_serial(void) {} |
1060 | #endif | |
1061 | ||
1062 | ||
1063 | /* -------------------------------------------------------------------- */ | |
1064 | ||
1065 | /* | |
1066 | * These devices are always present and don't need any board-specific | |
1067 | * setup. | |
1068 | */ | |
1069 | static int __init at91_add_standard_devices(void) | |
1070 | { | |
884f5a6a AV |
1071 | at91_add_device_rtt(); |
1072 | at91_add_device_watchdog(); | |
e5f40bfa | 1073 | at91_add_device_tc(); |
86ad76bb AV |
1074 | return 0; |
1075 | } | |
1076 | ||
1077 | arch_initcall(at91_add_standard_devices); |