[deliverable/linux.git] / arch / arm / mach-at91 / at91sam9263.c

/*
 * arch/arm/mach-at91/at91sam9263.c
 *
 *  Copyright (C) 2007 Atmel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 */

#include <linux/module.h>

#include <asm/proc-fns.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/system_misc.h>
#include <mach/at91sam9263.h>
#include <mach/at91_aic.h>
#include <mach/at91_pmc.h>
#include <mach/at91_rstc.h>

#include "soc.h"
#include "generic.h"
#include "clock.h"
#include "sam9_smc.h"

/* --------------------------------------------------------------------
 *  Clocks
 * -------------------------------------------------------------------- */

/*
 * The peripheral clocks.
 */
static struct clk pioA_clk = {
	.name		= "pioA_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_PIOA,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk pioB_clk = {
	.name		= "pioB_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_PIOB,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk pioCDE_clk = {
	.name		= "pioCDE_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_PIOCDE,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart0_clk = {
	.name		= "usart0_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_US0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart1_clk = {
	.name		= "usart1_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_US1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart2_clk = {
	.name		= "usart2_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_US2,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk mmc0_clk = {
	.name		= "mci0_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_MCI0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk mmc1_clk = {
	.name		= "mci1_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_MCI1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk can_clk = {
	.name		= "can_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_CAN,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk twi_clk = {
	.name		= "twi_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_TWI,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk spi0_clk = {
	.name		= "spi0_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_SPI0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk spi1_clk = {
	.name		= "spi1_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_SPI1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk ssc0_clk = {
	.name		= "ssc0_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_SSC0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk ssc1_clk = {
	.name		= "ssc1_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_SSC1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk ac97_clk = {
	.name		= "ac97_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_AC97C,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk tcb_clk = {
	.name		= "tcb_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_TCB,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk pwm_clk = {
	.name		= "pwm_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_PWMC,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk macb_clk = {
	.name		= "pclk",
	.pmc_mask	= 1 << AT91SAM9263_ID_EMAC,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk dma_clk = {
	.name		= "dma_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_DMA,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk twodge_clk = {
	.name		= "2dge_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_2DGE,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk udc_clk = {
	.name		= "udc_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_UDP,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk isi_clk = {
	.name		= "isi_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_ISI,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk lcdc_clk = {
	.name		= "lcdc_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_LCDC,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk ohci_clk = {
	.name		= "ohci_clk",
	.pmc_mask	= 1 << AT91SAM9263_ID_UHP,
	.type		= CLK_TYPE_PERIPHERAL,
};

static struct clk *periph_clocks[] __initdata = {
	&pioA_clk,
	&pioB_clk,
	&pioCDE_clk,
	&usart0_clk,
	&usart1_clk,
	&usart2_clk,
	&mmc0_clk,
	&mmc1_clk,
	&can_clk,
	&twi_clk,
	&spi0_clk,
	&spi1_clk,
	&ssc0_clk,
	&ssc1_clk,
	&ac97_clk,
	&tcb_clk,
	&pwm_clk,
	&macb_clk,
	&twodge_clk,
	&udc_clk,
	&isi_clk,
	&lcdc_clk,
	&dma_clk,
	&ohci_clk,
	// irq0 .. irq1
};

static struct clk_lookup periph_clocks_lookups[] = {
	/* One additional fake clock for macb_hclk */
	CLKDEV_CON_ID("hclk", &macb_clk),
	CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
	CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
	CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.0", &mmc0_clk),
	CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.1", &mmc1_clk),
	CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
	CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
	CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk),
	CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9260.0", &twi_clk),
	/* fake hclk clock */
	CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
	CLKDEV_CON_ID("pioA", &pioA_clk),
	CLKDEV_CON_ID("pioB", &pioB_clk),
	CLKDEV_CON_ID("pioC", &pioCDE_clk),
	CLKDEV_CON_ID("pioD", &pioCDE_clk),
	CLKDEV_CON_ID("pioE", &pioCDE_clk),
	/* more usart lookup table for DT entries */
	CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck),
	CLKDEV_CON_DEV_ID("usart", "fff8c000.serial", &usart0_clk),
	CLKDEV_CON_DEV_ID("usart", "fff90000.serial", &usart1_clk),
	CLKDEV_CON_DEV_ID("usart", "fff94000.serial", &usart2_clk),
	/* more tc lookup table for DT entries */
	CLKDEV_CON_DEV_ID("t0_clk", "fff7c000.timer", &tcb_clk),
	CLKDEV_CON_DEV_ID("hclk", "a00000.ohci", &ohci_clk),
	CLKDEV_CON_DEV_ID("spi_clk", "fffa4000.spi", &spi0_clk),
	CLKDEV_CON_DEV_ID("spi_clk", "fffa8000.spi", &spi1_clk),
	CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi_clk),
};

static struct clk_lookup usart_clocks_lookups[] = {
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
};

/*
 * The four programmable clocks.
 * You must configure pin multiplexing to bring these signals out.
 */
static struct clk pck0 = {
	.name		= "pck0",
	.pmc_mask	= AT91_PMC_PCK0,
	.type		= CLK_TYPE_PROGRAMMABLE,
	.id		= 0,
};
static struct clk pck1 = {
	.name		= "pck1",
	.pmc_mask	= AT91_PMC_PCK1,
	.type		= CLK_TYPE_PROGRAMMABLE,
	.id		= 1,
};
static struct clk pck2 = {
	.name		= "pck2",
	.pmc_mask	= AT91_PMC_PCK2,
	.type		= CLK_TYPE_PROGRAMMABLE,
	.id		= 2,
};
static struct clk pck3 = {
	.name		= "pck3",
	.pmc_mask	= AT91_PMC_PCK3,
	.type		= CLK_TYPE_PROGRAMMABLE,
	.id		= 3,
};

static void __init at91sam9263_register_clocks(void)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
		clk_register(periph_clocks[i]);

	clkdev_add_table(periph_clocks_lookups,
			 ARRAY_SIZE(periph_clocks_lookups));
	clkdev_add_table(usart_clocks_lookups,
			 ARRAY_SIZE(usart_clocks_lookups));

	clk_register(&pck0);
	clk_register(&pck1);
	clk_register(&pck2);
	clk_register(&pck3);
}

/* --------------------------------------------------------------------
 *  GPIO
 * -------------------------------------------------------------------- */

static struct at91_gpio_bank at91sam9263_gpio[] __initdata = {
	{
		.id		= AT91SAM9263_ID_PIOA,
		.regbase	= AT91SAM9263_BASE_PIOA,
	}, {
		.id		= AT91SAM9263_ID_PIOB,
		.regbase	= AT91SAM9263_BASE_PIOB,
	}, {
		.id		= AT91SAM9263_ID_PIOCDE,
		.regbase	= AT91SAM9263_BASE_PIOC,
	}, {
		.id		= AT91SAM9263_ID_PIOCDE,
		.regbase	= AT91SAM9263_BASE_PIOD,
	}, {
		.id		= AT91SAM9263_ID_PIOCDE,
		.regbase	= AT91SAM9263_BASE_PIOE,
	}
};

/* --------------------------------------------------------------------
 *  AT91SAM9263 processor initialization
 * -------------------------------------------------------------------- */

static void __init at91sam9263_map_io(void)
{
	at91_init_sram(0, AT91SAM9263_SRAM0_BASE, AT91SAM9263_SRAM0_SIZE);
	at91_init_sram(1, AT91SAM9263_SRAM1_BASE, AT91SAM9263_SRAM1_SIZE);
}

static void __init at91sam9263_ioremap_registers(void)
{
	at91_ioremap_shdwc(AT91SAM9263_BASE_SHDWC);
	at91_ioremap_rstc(AT91SAM9263_BASE_RSTC);
	at91_ioremap_ramc(0, AT91SAM9263_BASE_SDRAMC0, 512);
	at91_ioremap_ramc(1, AT91SAM9263_BASE_SDRAMC1, 512);
	at91sam926x_ioremap_pit(AT91SAM9263_BASE_PIT);
	at91sam9_ioremap_smc(0, AT91SAM9263_BASE_SMC0);
	at91sam9_ioremap_smc(1, AT91SAM9263_BASE_SMC1);
	at91_ioremap_matrix(AT91SAM9263_BASE_MATRIX);
}

static void __init at91sam9263_initialize(void)
{
	arm_pm_idle = at91sam9_idle;
	arm_pm_restart = at91sam9_alt_restart;
	at91_extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1);

	/* Register GPIO subsystem */
	at91_gpio_init(at91sam9263_gpio, 5);
}

/* --------------------------------------------------------------------
 *  Interrupt initialization
 * -------------------------------------------------------------------- */

/*
 * The default interrupt priority levels (0 = lowest, 7 = highest).
 */
static unsigned int at91sam9263_default_irq_priority[NR_AIC_IRQS] __initdata = {
	7,	/* Advanced Interrupt Controller (FIQ) */
	7,	/* System Peripherals */
	1,	/* Parallel IO Controller A */
	1,	/* Parallel IO Controller B */
	1,	/* Parallel IO Controller C, D and E */
	0,
	0,
	5,	/* USART 0 */
	5,	/* USART 1 */
	5,	/* USART 2 */
	0,	/* Multimedia Card Interface 0 */
	0,	/* Multimedia Card Interface 1 */
	3,	/* CAN */
	6,	/* Two-Wire Interface */
	5,	/* Serial Peripheral Interface 0 */
	5,	/* Serial Peripheral Interface 1 */
	4,	/* Serial Synchronous Controller 0 */
	4,	/* Serial Synchronous Controller 1 */
	5,	/* AC97 Controller */
	0,	/* Timer Counter 0, 1 and 2 */
	0,	/* Pulse Width Modulation Controller */
	3,	/* Ethernet */
	0,
	0,	/* 2D Graphic Engine */
	2,	/* USB Device Port */
	0,	/* Image Sensor Interface */
	3,	/* LDC Controller */
	0,	/* DMA Controller */
	0,
	2,	/* USB Host port */
	0,	/* Advanced Interrupt Controller (IRQ0) */
	0,	/* Advanced Interrupt Controller (IRQ1) */
};

struct at91_init_soc __initdata at91sam9263_soc = {
	.map_io = at91sam9263_map_io,
	.default_irq_priority = at91sam9263_default_irq_priority,
	.ioremap_registers = at91sam9263_ioremap_registers,
	.register_clocks = at91sam9263_register_clocks,
	.init = at91sam9263_initialize,
};
Commit	Line	Data
b2c65616 AV	1	/*
	2	* arch/arm/mach-at91/at91sam9263.c
	3	*
	4	* Copyright (C) 2007 Atmel Corporation.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	*/
	12
	13	#include <linux/module.h>
	14
c9dfafba	15	#include <asm/proc-fns.h>
80b02c17	16	#include <asm/irq.h>
b2c65616 AV	17	#include <asm/mach/arch.h>
b2c65616 AV	18	#include <asm/mach/map.h>
9f97da78	19	#include <asm/system_misc.h>
a09e64fb	20	#include <mach/at91sam9263.h>
8fe82a55	21	#include <mach/at91_aic.h>
a09e64fb RK	22	#include <mach/at91_pmc.h>
a09e64fb RK	23	#include <mach/at91_rstc.h>
b2c65616	24
21d08b9d	25	#include "soc.h"
b2c65616 AV	26	#include "generic.h"
b2c65616 AV	27	#include "clock.h"
faee0cc3	28	#include "sam9_smc.h"
b2c65616	29
b2c65616 AV	30	/* --------------------------------------------------------------------
	31	* Clocks
	32	* -------------------------------------------------------------------- */
	33
	34	/*
	35	* The peripheral clocks.
	36	*/
	37	static struct clk pioA_clk = {
	38	.name = "pioA_clk",
	39	.pmc_mask = 1 << AT91SAM9263_ID_PIOA,
	40	.type = CLK_TYPE_PERIPHERAL,
	41	};
	42	static struct clk pioB_clk = {
	43	.name = "pioB_clk",
	44	.pmc_mask = 1 << AT91SAM9263_ID_PIOB,
	45	.type = CLK_TYPE_PERIPHERAL,
	46	};
	47	static struct clk pioCDE_clk = {
	48	.name = "pioCDE_clk",
	49	.pmc_mask = 1 << AT91SAM9263_ID_PIOCDE,
	50	.type = CLK_TYPE_PERIPHERAL,
	51	};
	52	static struct clk usart0_clk = {
	53	.name = "usart0_clk",
	54	.pmc_mask = 1 << AT91SAM9263_ID_US0,
	55	.type = CLK_TYPE_PERIPHERAL,
	56	};
	57	static struct clk usart1_clk = {
	58	.name = "usart1_clk",
	59	.pmc_mask = 1 << AT91SAM9263_ID_US1,
	60	.type = CLK_TYPE_PERIPHERAL,
	61	};
	62	static struct clk usart2_clk = {
	63	.name = "usart2_clk",
	64	.pmc_mask = 1 << AT91SAM9263_ID_US2,
	65	.type = CLK_TYPE_PERIPHERAL,
	66	};
	67	static struct clk mmc0_clk = {
	68	.name = "mci0_clk",
	69	.pmc_mask = 1 << AT91SAM9263_ID_MCI0,
	70	.type = CLK_TYPE_PERIPHERAL,
	71	};
	72	static struct clk mmc1_clk = {
	73	.name = "mci1_clk",
	74	.pmc_mask = 1 << AT91SAM9263_ID_MCI1,
	75	.type = CLK_TYPE_PERIPHERAL,
	76	};
e8788bab AV	77	static struct clk can_clk = {
	78	.name = "can_clk",
	79	.pmc_mask = 1 << AT91SAM9263_ID_CAN,
	80	.type = CLK_TYPE_PERIPHERAL,
	81	};
b2c65616 AV	82	static struct clk twi_clk = {
	83	.name = "twi_clk",
	84	.pmc_mask = 1 << AT91SAM9263_ID_TWI,
	85	.type = CLK_TYPE_PERIPHERAL,
	86	};
	87	static struct clk spi0_clk = {
	88	.name = "spi0_clk",
	89	.pmc_mask = 1 << AT91SAM9263_ID_SPI0,
	90	.type = CLK_TYPE_PERIPHERAL,
	91	};
	92	static struct clk spi1_clk = {
	93	.name = "spi1_clk",
	94	.pmc_mask = 1 << AT91SAM9263_ID_SPI1,
	95	.type = CLK_TYPE_PERIPHERAL,
	96	};
e8788bab AV	97	static struct clk ssc0_clk = {
	98	.name = "ssc0_clk",
	99	.pmc_mask = 1 << AT91SAM9263_ID_SSC0,
	100	.type = CLK_TYPE_PERIPHERAL,
	101	};
	102	static struct clk ssc1_clk = {
	103	.name = "ssc1_clk",
	104	.pmc_mask = 1 << AT91SAM9263_ID_SSC1,
	105	.type = CLK_TYPE_PERIPHERAL,
	106	};
	107	static struct clk ac97_clk = {
	108	.name = "ac97_clk",
	109	.pmc_mask = 1 << AT91SAM9263_ID_AC97C,
	110	.type = CLK_TYPE_PERIPHERAL,
	111	};
b2c65616 AV	112	static struct clk tcb_clk = {
	113	.name = "tcb_clk",
	114	.pmc_mask = 1 << AT91SAM9263_ID_TCB,
	115	.type = CLK_TYPE_PERIPHERAL,
	116	};
bb1ad68b AV	117	static struct clk pwm_clk = {
bb1ad68b AV	118	.name = "pwm_clk",
e8788bab AV	119	.pmc_mask = 1 << AT91SAM9263_ID_PWMC,
	120	.type = CLK_TYPE_PERIPHERAL,
	121	};
69b2e99c	122	static struct clk macb_clk = {
865d605e	123	.name = "pclk",
b2c65616 AV	124	.pmc_mask = 1 << AT91SAM9263_ID_EMAC,
	125	.type = CLK_TYPE_PERIPHERAL,
	126	};
e8788bab AV	127	static struct clk dma_clk = {
	128	.name = "dma_clk",
	129	.pmc_mask = 1 << AT91SAM9263_ID_DMA,
	130	.type = CLK_TYPE_PERIPHERAL,
	131	};
	132	static struct clk twodge_clk = {
	133	.name = "2dge_clk",
	134	.pmc_mask = 1 << AT91SAM9263_ID_2DGE,
	135	.type = CLK_TYPE_PERIPHERAL,
	136	};
b2c65616 AV	137	static struct clk udc_clk = {
	138	.name = "udc_clk",
	139	.pmc_mask = 1 << AT91SAM9263_ID_UDP,
	140	.type = CLK_TYPE_PERIPHERAL,
	141	};
	142	static struct clk isi_clk = {
	143	.name = "isi_clk",
	144	.pmc_mask = 1 << AT91SAM9263_ID_ISI,
	145	.type = CLK_TYPE_PERIPHERAL,
	146	};
	147	static struct clk lcdc_clk = {
	148	.name = "lcdc_clk",
7f6e2d99	149	.pmc_mask = 1 << AT91SAM9263_ID_LCDC,
b2c65616 AV	150	.type = CLK_TYPE_PERIPHERAL,
	151	};
	152	static struct clk ohci_clk = {
	153	.name = "ohci_clk",
	154	.pmc_mask = 1 << AT91SAM9263_ID_UHP,
	155	.type = CLK_TYPE_PERIPHERAL,
	156	};
	157
	158	static struct clk *periph_clocks[] __initdata = {
	159	&pioA_clk,
	160	&pioB_clk,
	161	&pioCDE_clk,
	162	&usart0_clk,
	163	&usart1_clk,
	164	&usart2_clk,
	165	&mmc0_clk,
	166	&mmc1_clk,
e8788bab	167	&can_clk,
b2c65616 AV	168	&twi_clk,
	169	&spi0_clk,
	170	&spi1_clk,
e8788bab AV	171	&ssc0_clk,
	172	&ssc1_clk,
	173	&ac97_clk,
b2c65616	174	&tcb_clk,
bb1ad68b	175	&pwm_clk,
69b2e99c	176	&macb_clk,
e8788bab	177	&twodge_clk,
b2c65616 AV	178	&udc_clk,
	179	&isi_clk,
	180	&lcdc_clk,
e8788bab	181	&dma_clk,
b2c65616 AV	182	&ohci_clk,
	183	// irq0 .. irq1
	184	};
	185
bd602995	186	static struct clk_lookup periph_clocks_lookups[] = {
865d605e JI	187	/* One additional fake clock for macb_hclk */
865d605e JI	188	CLKDEV_CON_ID("hclk", &macb_clk),
bd602995 JCPV	189	CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
bd602995 JCPV	190	CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
4cf3326a LD	191	CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.0", &mmc0_clk),
4cf3326a LD	192	CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.1", &mmc1_clk),
bd602995 JCPV	193	CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
	194	CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
	195	CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk),
302090a6	196	CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9260.0", &twi_clk),
0af4316b JCPV	197	/* fake hclk clock */
0af4316b JCPV	198	CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
619d4a4b JCPV	199	CLKDEV_CON_ID("pioA", &pioA_clk),
	200	CLKDEV_CON_ID("pioB", &pioB_clk),
	201	CLKDEV_CON_ID("pioC", &pioCDE_clk),
	202	CLKDEV_CON_ID("pioD", &pioCDE_clk),
	203	CLKDEV_CON_ID("pioE", &pioCDE_clk),
4abb3677 JCPV	204	/* more usart lookup table for DT entries */
	205	CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck),
	206	CLKDEV_CON_DEV_ID("usart", "fff8c000.serial", &usart0_clk),
	207	CLKDEV_CON_DEV_ID("usart", "fff90000.serial", &usart1_clk),
	208	CLKDEV_CON_DEV_ID("usart", "fff94000.serial", &usart2_clk),
	209	/* more tc lookup table for DT entries */
	210	CLKDEV_CON_DEV_ID("t0_clk", "fff7c000.timer", &tcb_clk),
	211	CLKDEV_CON_DEV_ID("hclk", "a00000.ohci", &ohci_clk),
	212	CLKDEV_CON_DEV_ID("spi_clk", "fffa4000.spi", &spi0_clk),
	213	CLKDEV_CON_DEV_ID("spi_clk", "fffa8000.spi", &spi1_clk),
f7d19b90	214	CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi_clk),
bd602995 JCPV	215	};
	216
	217	static struct clk_lookup usart_clocks_lookups[] = {
	218	CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
	219	CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
	220	CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
	221	CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
	222	};
	223
b2c65616 AV	224	/*
	225	* The four programmable clocks.
	226	* You must configure pin multiplexing to bring these signals out.
	227	*/
	228	static struct clk pck0 = {
	229	.name = "pck0",
	230	.pmc_mask = AT91_PMC_PCK0,
	231	.type = CLK_TYPE_PROGRAMMABLE,
	232	.id = 0,
	233	};
	234	static struct clk pck1 = {
	235	.name = "pck1",
	236	.pmc_mask = AT91_PMC_PCK1,
	237	.type = CLK_TYPE_PROGRAMMABLE,
	238	.id = 1,
	239	};
	240	static struct clk pck2 = {
	241	.name = "pck2",
	242	.pmc_mask = AT91_PMC_PCK2,
	243	.type = CLK_TYPE_PROGRAMMABLE,
	244	.id = 2,
	245	};
	246	static struct clk pck3 = {
	247	.name = "pck3",
	248	.pmc_mask = AT91_PMC_PCK3,
	249	.type = CLK_TYPE_PROGRAMMABLE,
	250	.id = 3,
	251	};
	252
	253	static void __init at91sam9263_register_clocks(void)
	254	{
	255	int i;
	256
	257	for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
	258	clk_register(periph_clocks[i]);
	259
bd602995 JCPV	260	clkdev_add_table(periph_clocks_lookups,
	261	ARRAY_SIZE(periph_clocks_lookups));
	262	clkdev_add_table(usart_clocks_lookups,
	263	ARRAY_SIZE(usart_clocks_lookups));
	264
b2c65616 AV	265	clk_register(&pck0);
	266	clk_register(&pck1);
	267	clk_register(&pck2);
	268	clk_register(&pck3);
	269	}
	270
	271	/* --------------------------------------------------------------------
	272	* GPIO
	273	* -------------------------------------------------------------------- */
	274
1a2d9156	275	static struct at91_gpio_bank at91sam9263_gpio[] __initdata = {
b2c65616 AV	276	{
b2c65616 AV	277	.id = AT91SAM9263_ID_PIOA,
80e91cb8	278	.regbase = AT91SAM9263_BASE_PIOA,
b2c65616 AV	279	}, {
b2c65616 AV	280	.id = AT91SAM9263_ID_PIOB,
80e91cb8	281	.regbase = AT91SAM9263_BASE_PIOB,
b2c65616 AV	282	}, {
b2c65616 AV	283	.id = AT91SAM9263_ID_PIOCDE,
80e91cb8	284	.regbase = AT91SAM9263_BASE_PIOC,
b2c65616 AV	285	}, {
b2c65616 AV	286	.id = AT91SAM9263_ID_PIOCDE,
80e91cb8	287	.regbase = AT91SAM9263_BASE_PIOD,
b2c65616 AV	288	}, {
b2c65616 AV	289	.id = AT91SAM9263_ID_PIOCDE,
80e91cb8	290	.regbase = AT91SAM9263_BASE_PIOE,
b2c65616 AV	291	}
	292	};
	293
b2c65616 AV	294	/* --------------------------------------------------------------------
	295	* AT91SAM9263 processor initialization
	296	* -------------------------------------------------------------------- */
	297
21d08b9d	298	static void __init at91sam9263_map_io(void)
b2c65616	299	{
f0051d82 JCPV	300	at91_init_sram(0, AT91SAM9263_SRAM0_BASE, AT91SAM9263_SRAM0_SIZE);
f0051d82 JCPV	301	at91_init_sram(1, AT91SAM9263_SRAM1_BASE, AT91SAM9263_SRAM1_SIZE);
1b021a3b	302	}
b2c65616	303
cfa5a1fe JCPV	304	static void __init at91sam9263_ioremap_registers(void)
cfa5a1fe JCPV	305	{
f22deee5	306	at91_ioremap_shdwc(AT91SAM9263_BASE_SHDWC);
e9f68b5c	307	at91_ioremap_rstc(AT91SAM9263_BASE_RSTC);
f363c407 JCPV	308	at91_ioremap_ramc(0, AT91SAM9263_BASE_SDRAMC0, 512);
f363c407 JCPV	309	at91_ioremap_ramc(1, AT91SAM9263_BASE_SDRAMC1, 512);
4ab0c599	310	at91sam926x_ioremap_pit(AT91SAM9263_BASE_PIT);
faee0cc3 JCPV	311	at91sam9_ioremap_smc(0, AT91SAM9263_BASE_SMC0);
faee0cc3 JCPV	312	at91sam9_ioremap_smc(1, AT91SAM9263_BASE_SMC1);
4342d647	313	at91_ioremap_matrix(AT91SAM9263_BASE_MATRIX);
cfa5a1fe JCPV	314	}
cfa5a1fe JCPV	315
46539374	316	static void __init at91sam9263_initialize(void)
1b021a3b	317	{
0d781716	318	arm_pm_idle = at91sam9_idle;
1b2073e7	319	arm_pm_restart = at91sam9_alt_restart;
b2c65616 AV	320	at91_extern_irq = (1 << AT91SAM9263_ID_IRQ0) \| (1 << AT91SAM9263_ID_IRQ1);
b2c65616 AV	321
b2c65616 AV	322	/* Register GPIO subsystem */
	323	at91_gpio_init(at91sam9263_gpio, 5);
	324	}
	325
	326	/* --------------------------------------------------------------------
	327	* Interrupt initialization
	328	* -------------------------------------------------------------------- */
	329
	330	/*
	331	* The default interrupt priority levels (0 = lowest, 7 = highest).
	332	*/
	333	static unsigned int at91sam9263_default_irq_priority[NR_AIC_IRQS] __initdata = {
	334	7, /* Advanced Interrupt Controller (FIQ) */
	335	7, /* System Peripherals */
7cbed2b5 AV	336	1, /* Parallel IO Controller A */
	337	1, /* Parallel IO Controller B */
	338	1, /* Parallel IO Controller C, D and E */
b2c65616 AV	339	0,
b2c65616 AV	340	0,
7cbed2b5 AV	341	5, /* USART 0 */
	342	5, /* USART 1 */
	343	5, /* USART 2 */
b2c65616 AV	344	0, /* Multimedia Card Interface 0 */
b2c65616 AV	345	0, /* Multimedia Card Interface 1 */
7cbed2b5 AV	346	3, /* CAN */
	347	6, /* Two-Wire Interface */
	348	5, /* Serial Peripheral Interface 0 */
	349	5, /* Serial Peripheral Interface 1 */
	350	4, /* Serial Synchronous Controller 0 */
	351	4, /* Serial Synchronous Controller 1 */
	352	5, /* AC97 Controller */
b2c65616 AV	353	0, /* Timer Counter 0, 1 and 2 */
	354	0, /* Pulse Width Modulation Controller */
	355	3, /* Ethernet */
	356	0,
	357	0, /* 2D Graphic Engine */
7cbed2b5	358	2, /* USB Device Port */
b2c65616 AV	359	0, /* Image Sensor Interface */
	360	3, /* LDC Controller */
	361	0, /* DMA Controller */
	362	0,
7cbed2b5	363	2, /* USB Host port */
b2c65616 AV	364	0, /* Advanced Interrupt Controller (IRQ0) */
	365	0, /* Advanced Interrupt Controller (IRQ1) */
	366	};
	367
8c3583b6	368	struct at91_init_soc __initdata at91sam9263_soc = {
21d08b9d	369	.map_io = at91sam9263_map_io,
92100c12	370	.default_irq_priority = at91sam9263_default_irq_priority,
cfa5a1fe	371	.ioremap_registers = at91sam9263_ioremap_registers,
51ddec76	372	.register_clocks = at91sam9263_register_clocks,
21d08b9d JCPV	373	.init = at91sam9263_initialize,
21d08b9d JCPV	374	};