projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ARM: make mach/io.h include optional
[deliverable/linux.git] / arch / arm / mach-at91 / at91sam9263_devices.c
CommitLineData
b2c65616
AV		 1/*
2 * arch/arm/mach-at91/at91sam9263_devices.c
3 *
4 * Copyright (C) 2007 Atmel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 */
12#include <asm/mach/arch.h>
13#include <asm/mach/map.h>
14
c6686ff9 15#include <linux/dma-mapping.h>
2f8163ba 16#include <linux/gpio.h>
b2c65616 17#include <linux/platform_device.h>
f230d3f5 18#include <linux/i2c-gpio.h>
b2c65616 19
f230d3f5 20#include <linux/fb.h>
b8b78609
JA		 21#include <video/atmel_lcdc.h>
22
a09e64fb 23#include <mach/board.h>
a09e64fb
RK		 24#include <mach/at91sam9263.h>
25#include <mach/at91sam9263_matrix.h>
4342d647 26#include <mach/at91_matrix.h>
a09e64fb 27#include <mach/at91sam9_smc.h>
b2c65616
AV		 28
29#include "generic.h"
30
b2c65616
AV		 31
32/* --------------------------------------------------------------------
33 * USB Host
34 * -------------------------------------------------------------------- */
35
36#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
c6686ff9 37static u64 ohci_dmamask = DMA_BIT_MASK(32);
b2c65616
AV		 38static struct at91_usbh_data usbh_data;
39
40static struct resource usbh_resources[] = {
41 [0] = {
42 .start = AT91SAM9263_UHP_BASE,
43 .end = AT91SAM9263_UHP_BASE + SZ_1M - 1,
44 .flags = IORESOURCE_MEM,
45 },
46 [1] = {
47 .start = AT91SAM9263_ID_UHP,
48 .end = AT91SAM9263_ID_UHP,
49 .flags = IORESOURCE_IRQ,
50 },
51};
52
53static struct platform_device at91_usbh_device = {
54 .name = "at91_ohci",
55 .id = -1,
56 .dev = {
57 .dma_mask = &ohci_dmamask,
c6686ff9 58 .coherent_dma_mask = DMA_BIT_MASK(32),
b2c65616
AV		 59 .platform_data = &usbh_data,
60 },
61 .resource = usbh_resources,
62 .num_resources = ARRAY_SIZE(usbh_resources),
63};
64
65void __init at91_add_device_usbh(struct at91_usbh_data *data)
66{
67 int i;
68
69 if (!data)
70 return;
71
72 /* Enable VBus control for UHP ports */
73 for (i = 0; i < data->ports; i++) {
cc9f9aef 74 if (gpio_is_valid(data->vbus_pin[i]))
b2c65616
AV		 75 at91_set_gpio_output(data->vbus_pin[i], 0);
76 }
77
1fcaea7e
TP		 78 /* Enable overcurrent notification */
79 for (i = 0; i < data->ports; i++) {
80 if (data->overcurrent_pin[i])
81 at91_set_gpio_input(data->overcurrent_pin[i], 1);
82 }
83
b2c65616
AV		 84 usbh_data = *data;
85 platform_device_register(&at91_usbh_device);
86}
87#else
88void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
89#endif
90
91
92/* --------------------------------------------------------------------
93 * USB Device (Gadget)
94 * -------------------------------------------------------------------- */
95
0e934e22 96#ifdef CONFIG_USB_AT91
b2c65616
AV		 97static struct at91_udc_data udc_data;
98
99static struct resource udc_resources[] = {
100 [0] = {
101 .start = AT91SAM9263_BASE_UDP,
102 .end = AT91SAM9263_BASE_UDP + SZ_16K - 1,
103 .flags = IORESOURCE_MEM,
104 },
105 [1] = {
106 .start = AT91SAM9263_ID_UDP,
107 .end = AT91SAM9263_ID_UDP,
108 .flags = IORESOURCE_IRQ,
109 },
110};
111
112static struct platform_device at91_udc_device = {
113 .name = "at91_udc",
114 .id = -1,
115 .dev = {
116 .platform_data = &udc_data,
117 },
118 .resource = udc_resources,
119 .num_resources = ARRAY_SIZE(udc_resources),
120};
121
122void __init at91_add_device_udc(struct at91_udc_data *data)
123{
124 if (!data)
125 return;
126
cc9f9aef 127 if (gpio_is_valid(data->vbus_pin)) {
b2c65616
AV		 128 at91_set_gpio_input(data->vbus_pin, 0);
129 at91_set_deglitch(data->vbus_pin, 1);
130 }
131
132 /* Pullup pin is handled internally by USB device peripheral */
133
134 udc_data = *data;
135 platform_device_register(&at91_udc_device);
136}
137#else
138void __init at91_add_device_udc(struct at91_udc_data *data) {}
139#endif
140
141
142/* --------------------------------------------------------------------
143 * Ethernet
144 * -------------------------------------------------------------------- */
145
146#if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
c6686ff9 147static u64 eth_dmamask = DMA_BIT_MASK(32);
84e0cdb0 148static struct macb_platform_data eth_data;
b2c65616
AV		 149
150static struct resource eth_resources[] = {
151 [0] = {
152 .start = AT91SAM9263_BASE_EMAC,
153 .end = AT91SAM9263_BASE_EMAC + SZ_16K - 1,
154 .flags = IORESOURCE_MEM,
155 },
156 [1] = {
157 .start = AT91SAM9263_ID_EMAC,
158 .end = AT91SAM9263_ID_EMAC,
159 .flags = IORESOURCE_IRQ,
160 },
161};
162
163static struct platform_device at91sam9263_eth_device = {
164 .name = "macb",
165 .id = -1,
166 .dev = {
167 .dma_mask = &eth_dmamask,
c6686ff9 168 .coherent_dma_mask = DMA_BIT_MASK(32),
b2c65616
AV		 169 .platform_data = &eth_data,
170 },
171 .resource = eth_resources,
172 .num_resources = ARRAY_SIZE(eth_resources),
173};
174
84e0cdb0 175void __init at91_add_device_eth(struct macb_platform_data *data)
b2c65616
AV		 176{
177 if (!data)
178 return;
179
cc9f9aef 180 if (gpio_is_valid(data->phy_irq_pin)) {
b2c65616
AV		 181 at91_set_gpio_input(data->phy_irq_pin, 0);
182 at91_set_deglitch(data->phy_irq_pin, 1);
183 }
184
185 /* Pins used for MII and RMII */
186 at91_set_A_periph(AT91_PIN_PE21, 0); /* ETXCK_EREFCK */
187 at91_set_B_periph(AT91_PIN_PC25, 0); /* ERXDV */
188 at91_set_A_periph(AT91_PIN_PE25, 0); /* ERX0 */
189 at91_set_A_periph(AT91_PIN_PE26, 0); /* ERX1 */
190 at91_set_A_periph(AT91_PIN_PE27, 0); /* ERXER */
191 at91_set_A_periph(AT91_PIN_PE28, 0); /* ETXEN */
192 at91_set_A_periph(AT91_PIN_PE23, 0); /* ETX0 */
193 at91_set_A_periph(AT91_PIN_PE24, 0); /* ETX1 */
194 at91_set_A_periph(AT91_PIN_PE30, 0); /* EMDIO */
195 at91_set_A_periph(AT91_PIN_PE29, 0); /* EMDC */
196
197 if (!data->is_rmii) {
198 at91_set_A_periph(AT91_PIN_PE22, 0); /* ECRS */
199 at91_set_B_periph(AT91_PIN_PC26, 0); /* ECOL */
200 at91_set_B_periph(AT91_PIN_PC22, 0); /* ERX2 */
201 at91_set_B_periph(AT91_PIN_PC23, 0); /* ERX3 */
202 at91_set_B_periph(AT91_PIN_PC27, 0); /* ERXCK */
203 at91_set_B_periph(AT91_PIN_PC20, 0); /* ETX2 */
204 at91_set_B_periph(AT91_PIN_PC21, 0); /* ETX3 */
205 at91_set_B_periph(AT91_PIN_PC24, 0); /* ETXER */
206 }
207
208 eth_data = *data;
209 platform_device_register(&at91sam9263_eth_device);
210}
211#else
84e0cdb0 212void __init at91_add_device_eth(struct macb_platform_data *data) {}
b2c65616
AV		 213#endif
214
215
216/* --------------------------------------------------------------------
217 * MMC / SD
218 * -------------------------------------------------------------------- */
219
220#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
c6686ff9 221static u64 mmc_dmamask = DMA_BIT_MASK(32);
b2c65616
AV		 222static struct at91_mmc_data mmc0_data, mmc1_data;
223
224static struct resource mmc0_resources[] = {
225 [0] = {
226 .start = AT91SAM9263_BASE_MCI0,
227 .end = AT91SAM9263_BASE_MCI0 + SZ_16K - 1,
228 .flags = IORESOURCE_MEM,
229 },
230 [1] = {
231 .start = AT91SAM9263_ID_MCI0,
232 .end = AT91SAM9263_ID_MCI0,
233 .flags = IORESOURCE_IRQ,
234 },
235};
236
237static struct platform_device at91sam9263_mmc0_device = {
238 .name = "at91_mci",
239 .id = 0,
240 .dev = {
241 .dma_mask = &mmc_dmamask,
c6686ff9 242 .coherent_dma_mask = DMA_BIT_MASK(32),
b2c65616
AV		 243 .platform_data = &mmc0_data,
244 },
245 .resource = mmc0_resources,
246 .num_resources = ARRAY_SIZE(mmc0_resources),
247};
248
249static struct resource mmc1_resources[] = {
250 [0] = {
251 .start = AT91SAM9263_BASE_MCI1,
252 .end = AT91SAM9263_BASE_MCI1 + SZ_16K - 1,
253 .flags = IORESOURCE_MEM,
254 },
255 [1] = {
256 .start = AT91SAM9263_ID_MCI1,
257 .end = AT91SAM9263_ID_MCI1,
258 .flags = IORESOURCE_IRQ,
259 },
260};
261
262static struct platform_device at91sam9263_mmc1_device = {
263 .name = "at91_mci",
264 .id = 1,
265 .dev = {
266 .dma_mask = &mmc_dmamask,
c6686ff9 267 .coherent_dma_mask = DMA_BIT_MASK(32),
b2c65616
AV		 268 .platform_data = &mmc1_data,
269 },
270 .resource = mmc1_resources,
271 .num_resources = ARRAY_SIZE(mmc1_resources),
272};
273
274void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
275{
276 if (!data)
277 return;
278
279 /* input/irq */
cc9f9aef 280 if (gpio_is_valid(data->det_pin)) {
b2c65616
AV		 281 at91_set_gpio_input(data->det_pin, 1);
282 at91_set_deglitch(data->det_pin, 1);
283 }
cc9f9aef 284 if (gpio_is_valid(data->wp_pin))
b2c65616 285 at91_set_gpio_input(data->wp_pin, 1);
cc9f9aef 286 if (gpio_is_valid(data->vcc_pin))
b2c65616
AV		 287 at91_set_gpio_output(data->vcc_pin, 0);
288
289 if (mmc_id == 0) { /* MCI0 */
290 /* CLK */
291 at91_set_A_periph(AT91_PIN_PA12, 0);
292
293 if (data->slot_b) {
294 /* CMD */
295 at91_set_A_periph(AT91_PIN_PA16, 1);
296
297 /* DAT0, maybe DAT1..DAT3 */
298 at91_set_A_periph(AT91_PIN_PA17, 1);
299 if (data->wire4) {
300 at91_set_A_periph(AT91_PIN_PA18, 1);
301 at91_set_A_periph(AT91_PIN_PA19, 1);
302 at91_set_A_periph(AT91_PIN_PA20, 1);
303 }
304 } else {
305 /* CMD */
306 at91_set_A_periph(AT91_PIN_PA1, 1);
307
308 /* DAT0, maybe DAT1..DAT3 */
309 at91_set_A_periph(AT91_PIN_PA0, 1);
310 if (data->wire4) {
311 at91_set_A_periph(AT91_PIN_PA3, 1);
312 at91_set_A_periph(AT91_PIN_PA4, 1);
313 at91_set_A_periph(AT91_PIN_PA5, 1);
314 }
315 }
316
317 mmc0_data = *data;
b2c65616
AV		 318 platform_device_register(&at91sam9263_mmc0_device);
319 } else { /* MCI1 */
320 /* CLK */
321 at91_set_A_periph(AT91_PIN_PA6, 0);
322
323 if (data->slot_b) {
324 /* CMD */
325 at91_set_A_periph(AT91_PIN_PA21, 1);
326
327 /* DAT0, maybe DAT1..DAT3 */
328 at91_set_A_periph(AT91_PIN_PA22, 1);
329 if (data->wire4) {
330 at91_set_A_periph(AT91_PIN_PA23, 1);
331 at91_set_A_periph(AT91_PIN_PA24, 1);
332 at91_set_A_periph(AT91_PIN_PA25, 1);
333 }
334 } else {
335 /* CMD */
336 at91_set_A_periph(AT91_PIN_PA7, 1);
337
338 /* DAT0, maybe DAT1..DAT3 */
339 at91_set_A_periph(AT91_PIN_PA8, 1);
340 if (data->wire4) {
341 at91_set_A_periph(AT91_PIN_PA9, 1);
342 at91_set_A_periph(AT91_PIN_PA10, 1);
343 at91_set_A_periph(AT91_PIN_PA11, 1);
344 }
345 }
346
347 mmc1_data = *data;
b2c65616
AV		 348 platform_device_register(&at91sam9263_mmc1_device);
349 }
350}
351#else
352void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
353#endif
354
e565f206
SG		 355/* --------------------------------------------------------------------
356 * Compact Flash (PCMCIA or IDE)
357 * -------------------------------------------------------------------- */
358
359#if defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE) || \
360 defined(CONFIG_BLK_DEV_IDE_AT91) || defined(CONFIG_BLK_DEV_IDE_AT91_MODULE)
361
362static struct at91_cf_data cf0_data;
363
364static struct resource cf0_resources[] = {
365 [0] = {
366 .start = AT91_CHIPSELECT_4,
367 .end = AT91_CHIPSELECT_4 + SZ_256M - 1,
368 .flags = IORESOURCE_MEM | IORESOURCE_MEM_8AND16BIT,
369 }
370};
371
372static struct platform_device cf0_device = {
373 .id = 0,
374 .dev = {
375 .platform_data = &cf0_data,
376 },
377 .resource = cf0_resources,
378 .num_resources = ARRAY_SIZE(cf0_resources),
379};
380
381static struct at91_cf_data cf1_data;
382
383static struct resource cf1_resources[] = {
384 [0] = {
385 .start = AT91_CHIPSELECT_5,
386 .end = AT91_CHIPSELECT_5 + SZ_256M - 1,
387 .flags = IORESOURCE_MEM | IORESOURCE_MEM_8AND16BIT,
388 }
389};
390
391static struct platform_device cf1_device = {
392 .id = 1,
393 .dev = {
394 .platform_data = &cf1_data,
395 },
396 .resource = cf1_resources,
397 .num_resources = ARRAY_SIZE(cf1_resources),
398};
399
400void __init at91_add_device_cf(struct at91_cf_data *data)
401{
402 unsigned long ebi0_csa;
403 struct platform_device *pdev;
404
405 if (!data)
406 return;
407
408 /*
409 * assign CS4 or CS5 to SMC with Compact Flash logic support,
410 * we assume SMC timings are configured by board code,
411 * except True IDE where timings are controlled by driver
412 */
4342d647 413 ebi0_csa = at91_matrix_read(AT91_MATRIX_EBI0CSA);
e565f206
SG		 414 switch (data->chipselect) {
415 case 4:
416 at91_set_A_periph(AT91_PIN_PD6, 0); /* EBI0_NCS4/CFCS0 */
417 ebi0_csa |= AT91_MATRIX_EBI0_CS4A_SMC_CF1;
418 cf0_data = *data;
419 pdev = &cf0_device;
420 break;
421 case 5:
422 at91_set_A_periph(AT91_PIN_PD7, 0); /* EBI0_NCS5/CFCS1 */
423 ebi0_csa |= AT91_MATRIX_EBI0_CS5A_SMC_CF2;
424 cf1_data = *data;
425 pdev = &cf1_device;
426 break;
427 default:
428 printk(KERN_ERR "AT91 CF: bad chip-select requested (%u)\n",
429 data->chipselect);
430 return;
431 }
4342d647 432 at91_matrix_write(AT91_MATRIX_EBI0CSA, ebi0_csa);
e565f206 433
cc9f9aef 434 if (gpio_is_valid(data->det_pin)) {
e565f206
SG		 435 at91_set_gpio_input(data->det_pin, 1);
436 at91_set_deglitch(data->det_pin, 1);
437 }
438
cc9f9aef 439 if (gpio_is_valid(data->irq_pin)) {
e565f206
SG		 440 at91_set_gpio_input(data->irq_pin, 1);
441 at91_set_deglitch(data->irq_pin, 1);
442 }
443
cc9f9aef 444 if (gpio_is_valid(data->vcc_pin))
e565f206
SG		 445 /* initially off */
446 at91_set_gpio_output(data->vcc_pin, 0);
447
448 /* enable EBI controlled pins */
449 at91_set_A_periph(AT91_PIN_PD5, 1); /* NWAIT */
450 at91_set_A_periph(AT91_PIN_PD8, 0); /* CFCE1 */
451 at91_set_A_periph(AT91_PIN_PD9, 0); /* CFCE2 */
452 at91_set_A_periph(AT91_PIN_PD14, 0); /* CFNRW */
453
454 pdev->name = (data->flags & AT91_CF_TRUE_IDE) ? "at91_ide" : "at91_cf";
455 platform_device_register(pdev);
456}
457#else
458void __init at91_add_device_cf(struct at91_cf_data *data) {}
459#endif
b2c65616
AV		 460
461/* --------------------------------------------------------------------
462 * NAND / SmartMedia
463 * -------------------------------------------------------------------- */
464
f6ed6f78 465#if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
3c3796cc 466static struct atmel_nand_data nand_data;
b2c65616
AV		 467
468#define NAND_BASE AT91_CHIPSELECT_3
469
470static struct resource nand_resources[] = {
d7a2415f 471 [0] = {
b2c65616
AV		 472 .start = NAND_BASE,
473 .end = NAND_BASE + SZ_256M - 1,
474 .flags = IORESOURCE_MEM,
d7a2415f
AV		 475 },
476 [1] = {
d28edd1b
JCPV		 477 .start = AT91SAM9263_BASE_ECC0,
478 .end = AT91SAM9263_BASE_ECC0 + SZ_512 - 1,
d7a2415f 479 .flags = IORESOURCE_MEM,
b2c65616
AV		 480 }
481};
482
483static struct platform_device at91sam9263_nand_device = {
3c3796cc 484 .name = "atmel_nand",
b2c65616
AV		 485 .id = -1,
486 .dev = {
487 .platform_data = &nand_data,
488 },
489 .resource = nand_resources,
490 .num_resources = ARRAY_SIZE(nand_resources),
491};
492
3c3796cc 493void __init at91_add_device_nand(struct atmel_nand_data *data)
b2c65616 494{
461d3b4d 495 unsigned long csa;
b2c65616
AV		 496
497 if (!data)
498 return;
499
4342d647
JCPV		 500 csa = at91_matrix_read(AT91_MATRIX_EBI0CSA);
501 at91_matrix_write(AT91_MATRIX_EBI0CSA, csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
b2c65616 502
b2c65616 503 /* enable pin */
cc9f9aef 504 if (gpio_is_valid(data->enable_pin))
b2c65616
AV		 505 at91_set_gpio_output(data->enable_pin, 1);
506
507 /* ready/busy pin */
cc9f9aef 508 if (gpio_is_valid(data->rdy_pin))
b2c65616
AV		 509 at91_set_gpio_input(data->rdy_pin, 1);
510
511 /* card detect pin */
cc9f9aef 512 if (gpio_is_valid(data->det_pin))
b2c65616
AV		 513 at91_set_gpio_input(data->det_pin, 1);
514
515 nand_data = *data;
516 platform_device_register(&at91sam9263_nand_device);
517}
518#else
3c3796cc 519void __init at91_add_device_nand(struct atmel_nand_data *data) {}
b2c65616
AV		 520#endif
521
522
523/* --------------------------------------------------------------------
524 * TWI (i2c)
525 * -------------------------------------------------------------------- */
526
f230d3f5
AV		 527/*
528 * Prefer the GPIO code since the TWI controller isn't robust
529 * (gets overruns and underruns under load) and can only issue
530 * repeated STARTs in one scenario (the driver doesn't yet handle them).
531 */
532#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
533
534static struct i2c_gpio_platform_data pdata = {
535 .sda_pin = AT91_PIN_PB4,
536 .sda_is_open_drain = 1,
537 .scl_pin = AT91_PIN_PB5,
538 .scl_is_open_drain = 1,
539 .udelay = 2, /* ~100 kHz */
540};
541
542static struct platform_device at91sam9263_twi_device = {
543 .name = "i2c-gpio",
544 .id = -1,
545 .dev.platform_data = &pdata,
546};
547
548void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
549{
550 at91_set_GPIO_periph(AT91_PIN_PB4, 1); /* TWD (SDA) */
551 at91_set_multi_drive(AT91_PIN_PB4, 1);
552
553 at91_set_GPIO_periph(AT91_PIN_PB5, 1); /* TWCK (SCL) */
554 at91_set_multi_drive(AT91_PIN_PB5, 1);
555
556 i2c_register_board_info(0, devices, nr_devices);
557 platform_device_register(&at91sam9263_twi_device);
558}
559
560#elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
b2c65616
AV		 561
562static struct resource twi_resources[] = {
563 [0] = {
564 .start = AT91SAM9263_BASE_TWI,
565 .end = AT91SAM9263_BASE_TWI + SZ_16K - 1,
566 .flags = IORESOURCE_MEM,
567 },
568 [1] = {
569 .start = AT91SAM9263_ID_TWI,
570 .end = AT91SAM9263_ID_TWI,
571 .flags = IORESOURCE_IRQ,
572 },
573};
574
575static struct platform_device at91sam9263_twi_device = {
576 .name = "at91_i2c",
577 .id = -1,
578 .resource = twi_resources,
579 .num_resources = ARRAY_SIZE(twi_resources),
580};
581
f230d3f5 582void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
b2c65616
AV		 583{
584 /* pins used for TWI interface */
585 at91_set_A_periph(AT91_PIN_PB4, 0); /* TWD */
586 at91_set_multi_drive(AT91_PIN_PB4, 1);
587
588 at91_set_A_periph(AT91_PIN_PB5, 0); /* TWCK */
589 at91_set_multi_drive(AT91_PIN_PB5, 1);
590
f230d3f5 591 i2c_register_board_info(0, devices, nr_devices);
b2c65616
AV		 592 platform_device_register(&at91sam9263_twi_device);
593}
594#else
f230d3f5 595void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
b2c65616
AV		 596#endif
597
598
599/* --------------------------------------------------------------------
600 * SPI
601 * -------------------------------------------------------------------- */
602
603#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
c6686ff9 604static u64 spi_dmamask = DMA_BIT_MASK(32);
b2c65616
AV		 605
606static struct resource spi0_resources[] = {
607 [0] = {
608 .start = AT91SAM9263_BASE_SPI0,
609 .end = AT91SAM9263_BASE_SPI0 + SZ_16K - 1,
610 .flags = IORESOURCE_MEM,
611 },
612 [1] = {
613 .start = AT91SAM9263_ID_SPI0,
614 .end = AT91SAM9263_ID_SPI0,
615 .flags = IORESOURCE_IRQ,
616 },
617};
618
619static struct platform_device at91sam9263_spi0_device = {
620 .name = "atmel_spi",
621 .id = 0,
622 .dev = {
623 .dma_mask = &spi_dmamask,
c6686ff9 624 .coherent_dma_mask = DMA_BIT_MASK(32),
b2c65616
AV		 625 },
626 .resource = spi0_resources,
627 .num_resources = ARRAY_SIZE(spi0_resources),
628};
629
630static const unsigned spi0_standard_cs[4] = { AT91_PIN_PA5, AT91_PIN_PA3, AT91_PIN_PA4, AT91_PIN_PB11 };
631
632static struct resource spi1_resources[] = {
633 [0] = {
634 .start = AT91SAM9263_BASE_SPI1,
635 .end = AT91SAM9263_BASE_SPI1 + SZ_16K - 1,
636 .flags = IORESOURCE_MEM,
637 },
638 [1] = {
639 .start = AT91SAM9263_ID_SPI1,
640 .end = AT91SAM9263_ID_SPI1,
641 .flags = IORESOURCE_IRQ,
642 },
643};
644
645static struct platform_device at91sam9263_spi1_device = {
646 .name = "atmel_spi",
647 .id = 1,
648 .dev = {
649 .dma_mask = &spi_dmamask,
c6686ff9 650 .coherent_dma_mask = DMA_BIT_MASK(32),
b2c65616
AV		 651 },
652 .resource = spi1_resources,
653 .num_resources = ARRAY_SIZE(spi1_resources),
654};
655
656static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB15, AT91_PIN_PB16, AT91_PIN_PB17, AT91_PIN_PB18 };
657
658void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
659{
660 int i;
661 unsigned long cs_pin;
662 short enable_spi0 = 0;
663 short enable_spi1 = 0;
664
665 /* Choose SPI chip-selects */
666 for (i = 0; i < nr_devices; i++) {
667 if (devices[i].controller_data)
668 cs_pin = (unsigned long) devices[i].controller_data;
669 else if (devices[i].bus_num == 0)
670 cs_pin = spi0_standard_cs[devices[i].chip_select];
671 else
672 cs_pin = spi1_standard_cs[devices[i].chip_select];
673
674 if (devices[i].bus_num == 0)
675 enable_spi0 = 1;
676 else
677 enable_spi1 = 1;
678
679 /* enable chip-select pin */
680 at91_set_gpio_output(cs_pin, 1);
681
682 /* pass chip-select pin to driver */
683 devices[i].controller_data = (void *) cs_pin;
684 }
685
686 spi_register_board_info(devices, nr_devices);
687
688 /* Configure SPI bus(es) */
689 if (enable_spi0) {
690 at91_set_B_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
691 at91_set_B_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
7f6e2d99 692 at91_set_B_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */
b2c65616 693
b2c65616
AV		 694 platform_device_register(&at91sam9263_spi0_device);
695 }
696 if (enable_spi1) {
697 at91_set_A_periph(AT91_PIN_PB12, 0); /* SPI1_MISO */
698 at91_set_A_periph(AT91_PIN_PB13, 0); /* SPI1_MOSI */
699 at91_set_A_periph(AT91_PIN_PB14, 0); /* SPI1_SPCK */
700
b2c65616
AV		 701 platform_device_register(&at91sam9263_spi1_device);
702 }
703}
704#else
705void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
706#endif
707
708
7776a94c
AV		 709/* --------------------------------------------------------------------
710 * AC97
711 * -------------------------------------------------------------------- */
712
d656f07a 713#if defined(CONFIG_SND_ATMEL_AC97C) || defined(CONFIG_SND_ATMEL_AC97C_MODULE)
c6686ff9 714static u64 ac97_dmamask = DMA_BIT_MASK(32);
d656f07a 715static struct ac97c_platform_data ac97_data;
7776a94c
AV		 716
717static struct resource ac97_resources[] = {
718 [0] = {
719 .start = AT91SAM9263_BASE_AC97C,
720 .end = AT91SAM9263_BASE_AC97C + SZ_16K - 1,
721 .flags = IORESOURCE_MEM,
722 },
723 [1] = {
724 .start = AT91SAM9263_ID_AC97C,
725 .end = AT91SAM9263_ID_AC97C,
726 .flags = IORESOURCE_IRQ,
727 },
728};
729
730static struct platform_device at91sam9263_ac97_device = {
d656f07a 731 .name = "atmel_ac97c",
732 .id = 0,
7776a94c
AV		 733 .dev = {
734 .dma_mask = &ac97_dmamask,
c6686ff9 735 .coherent_dma_mask = DMA_BIT_MASK(32),
7776a94c
AV		 736 .platform_data = &ac97_data,
737 },
738 .resource = ac97_resources,
739 .num_resources = ARRAY_SIZE(ac97_resources),
740};
741
d656f07a 742void __init at91_add_device_ac97(struct ac97c_platform_data *data)
7776a94c
AV		 743{
744 if (!data)
745 return;
746
747 at91_set_A_periph(AT91_PIN_PB0, 0); /* AC97FS */
748 at91_set_A_periph(AT91_PIN_PB1, 0); /* AC97CK */
749 at91_set_A_periph(AT91_PIN_PB2, 0); /* AC97TX */
750 at91_set_A_periph(AT91_PIN_PB3, 0); /* AC97RX */
751
752 /* reset */
cc9f9aef 753 if (gpio_is_valid(data->reset_pin))
7776a94c
AV		 754 at91_set_gpio_output(data->reset_pin, 0);
755
d656f07a 756 ac97_data = *data;
7776a94c
AV		 757 platform_device_register(&at91sam9263_ac97_device);
758}
759#else
d656f07a 760void __init at91_add_device_ac97(struct ac97c_platform_data *data) {}
7776a94c
AV		 761#endif
762
58a587dc
MKB		 763/* --------------------------------------------------------------------
764 * CAN Controller
765 * -------------------------------------------------------------------- */
766
767#if defined(CONFIG_CAN_AT91) || defined(CONFIG_CAN_AT91_MODULE)
768static struct resource can_resources[] = {
769 [0] = {
770 .start = AT91SAM9263_BASE_CAN,
771 .end = AT91SAM9263_BASE_CAN + SZ_16K - 1,
772 .flags = IORESOURCE_MEM,
773 },
774 [1] = {
775 .start = AT91SAM9263_ID_CAN,
776 .end = AT91SAM9263_ID_CAN,
777 .flags = IORESOURCE_IRQ,
778 },
779};
780
781static struct platform_device at91sam9263_can_device = {
782 .name = "at91_can",
783 .id = -1,
784 .resource = can_resources,
785 .num_resources = ARRAY_SIZE(can_resources),
786};
787
788void __init at91_add_device_can(struct at91_can_data *data)
789{
790 at91_set_A_periph(AT91_PIN_PA13, 0); /* CANTX */
791 at91_set_A_periph(AT91_PIN_PA14, 0); /* CANRX */
792 at91sam9263_can_device.dev.platform_data = data;
793
794 platform_device_register(&at91sam9263_can_device);
795}
796#else
797void __init at91_add_device_can(struct at91_can_data *data) {}
798#endif
7776a94c
AV		 799
800/* --------------------------------------------------------------------
801 * LCD Controller
802 * -------------------------------------------------------------------- */
803
804#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
c6686ff9 805static u64 lcdc_dmamask = DMA_BIT_MASK(32);
7776a94c
AV		 806static struct atmel_lcdfb_info lcdc_data;
807
808static struct resource lcdc_resources[] = {
809 [0] = {
810 .start = AT91SAM9263_LCDC_BASE,
811 .end = AT91SAM9263_LCDC_BASE + SZ_4K - 1,
812 .flags = IORESOURCE_MEM,
813 },
814 [1] = {
815 .start = AT91SAM9263_ID_LCDC,
816 .end = AT91SAM9263_ID_LCDC,
817 .flags = IORESOURCE_IRQ,
818 },
819};
820
821static struct platform_device at91_lcdc_device = {
822 .name = "atmel_lcdfb",
823 .id = 0,
824 .dev = {
825 .dma_mask = &lcdc_dmamask,
c6686ff9 826 .coherent_dma_mask = DMA_BIT_MASK(32),
7776a94c
AV		 827 .platform_data = &lcdc_data,
828 },
829 .resource = lcdc_resources,
830 .num_resources = ARRAY_SIZE(lcdc_resources),
831};
832
833void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
834{
835 if (!data)
836 return;
837
838 at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */
839 at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */
840 at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDDEN */
841 at91_set_B_periph(AT91_PIN_PB9, 0); /* LCDCC */
842 at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDD2 */
843 at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDD3 */
844 at91_set_A_periph(AT91_PIN_PC8, 0); /* LCDD4 */
845 at91_set_A_periph(AT91_PIN_PC9, 0); /* LCDD5 */
846 at91_set_A_periph(AT91_PIN_PC10, 0); /* LCDD6 */
847 at91_set_A_periph(AT91_PIN_PC11, 0); /* LCDD7 */
848 at91_set_A_periph(AT91_PIN_PC14, 0); /* LCDD10 */
849 at91_set_A_periph(AT91_PIN_PC15, 0); /* LCDD11 */
850 at91_set_A_periph(AT91_PIN_PC16, 0); /* LCDD12 */
851 at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD13 */
852 at91_set_A_periph(AT91_PIN_PC18, 0); /* LCDD14 */
853 at91_set_A_periph(AT91_PIN_PC19, 0); /* LCDD15 */
854 at91_set_A_periph(AT91_PIN_PC22, 0); /* LCDD18 */
855 at91_set_A_periph(AT91_PIN_PC23, 0); /* LCDD19 */
856 at91_set_A_periph(AT91_PIN_PC24, 0); /* LCDD20 */
857 at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD21 */
858 at91_set_A_periph(AT91_PIN_PC26, 0); /* LCDD22 */
859 at91_set_A_periph(AT91_PIN_PC27, 0); /* LCDD23 */
860
861 lcdc_data = *data;
862 platform_device_register(&at91_lcdc_device);
863}
864#else
865void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
866#endif
867
868
e2920802
AV		 869/* --------------------------------------------------------------------
870 * Image Sensor Interface
871 * -------------------------------------------------------------------- */
872
873#if defined(CONFIG_VIDEO_AT91_ISI) || defined(CONFIG_VIDEO_AT91_ISI_MODULE)
874
875struct resource isi_resources[] = {
876 [0] = {
877 .start = AT91SAM9263_BASE_ISI,
878 .end = AT91SAM9263_BASE_ISI + SZ_16K - 1,
879 .flags = IORESOURCE_MEM,
880 },
881 [1] = {
882 .start = AT91SAM9263_ID_ISI,
883 .end = AT91SAM9263_ID_ISI,
884 .flags = IORESOURCE_IRQ,
885 },
886};
887
888static struct platform_device at91sam9263_isi_device = {
889 .name = "at91_isi",
890 .id = -1,
891 .resource = isi_resources,
892 .num_resources = ARRAY_SIZE(isi_resources),
893};
894
45bb9e6f
JW		 895void __init at91_add_device_isi(struct isi_platform_data *data,
896 bool use_pck_as_mck)
e2920802
AV		 897{
898 at91_set_A_periph(AT91_PIN_PE0, 0); /* ISI_D0 */
899 at91_set_A_periph(AT91_PIN_PE1, 0); /* ISI_D1 */
900 at91_set_A_periph(AT91_PIN_PE2, 0); /* ISI_D2 */
901 at91_set_A_periph(AT91_PIN_PE3, 0); /* ISI_D3 */
902 at91_set_A_periph(AT91_PIN_PE4, 0); /* ISI_D4 */
903 at91_set_A_periph(AT91_PIN_PE5, 0); /* ISI_D5 */
904 at91_set_A_periph(AT91_PIN_PE6, 0); /* ISI_D6 */
905 at91_set_A_periph(AT91_PIN_PE7, 0); /* ISI_D7 */
906 at91_set_A_periph(AT91_PIN_PE8, 0); /* ISI_PCK */
907 at91_set_A_periph(AT91_PIN_PE9, 0); /* ISI_HSYNC */
908 at91_set_A_periph(AT91_PIN_PE10, 0); /* ISI_VSYNC */
e2920802
AV		 909 at91_set_B_periph(AT91_PIN_PE12, 0); /* ISI_PD8 */
910 at91_set_B_periph(AT91_PIN_PE13, 0); /* ISI_PD9 */
911 at91_set_B_periph(AT91_PIN_PE14, 0); /* ISI_PD10 */
912 at91_set_B_periph(AT91_PIN_PE15, 0); /* ISI_PD11 */
45bb9e6f
JW		 913
914 if (use_pck_as_mck) {
915 at91_set_B_periph(AT91_PIN_PE11, 0); /* ISI_MCK (PCK3) */
916
917 /* TODO: register the PCK for ISI_MCK and set its parent */
918 }
e2920802
AV		 919}
920#else
45bb9e6f
JW		 921void __init at91_add_device_isi(struct isi_platform_data *data,
922 bool use_pck_as_mck) {}
e2920802
AV		 923#endif
924
925
e5f40bfa
AV		 926/* --------------------------------------------------------------------
927 * Timer/Counter block
928 * -------------------------------------------------------------------- */
929
930#ifdef CONFIG_ATMEL_TCLIB
931
932static struct resource tcb_resources[] = {
933 [0] = {
934 .start = AT91SAM9263_BASE_TCB0,
935 .end = AT91SAM9263_BASE_TCB0 + SZ_16K - 1,
936 .flags = IORESOURCE_MEM,
937 },
938 [1] = {
939 .start = AT91SAM9263_ID_TCB,
940 .end = AT91SAM9263_ID_TCB,
941 .flags = IORESOURCE_IRQ,
942 },
943};
944
945static struct platform_device at91sam9263_tcb_device = {
946 .name = "atmel_tcb",
947 .id = 0,
948 .resource = tcb_resources,
949 .num_resources = ARRAY_SIZE(tcb_resources),
950};
951
952static void __init at91_add_device_tc(void)
953{
e5f40bfa
AV		 954 platform_device_register(&at91sam9263_tcb_device);
955}
956#else
957static void __init at91_add_device_tc(void) { }
958#endif
959
960
884f5a6a
AV		 961/* --------------------------------------------------------------------
962 * RTT
963 * -------------------------------------------------------------------- */
964
965static struct resource rtt0_resources[] = {
966 {
eab5fd67
JCPV		 967 .start = AT91SAM9263_BASE_RTT0,
968 .end = AT91SAM9263_BASE_RTT0 + SZ_16 - 1,
884f5a6a 969 .flags = IORESOURCE_MEM,
b3af8b49
JCPV		 970 }, {
971 .flags = IORESOURCE_MEM,
884f5a6a
AV		 972 }
973};
974
975static struct platform_device at91sam9263_rtt0_device = {
976 .name = "at91_rtt",
977 .id = 0,
978 .resource = rtt0_resources,
884f5a6a
AV		 979};
980
981static struct resource rtt1_resources[] = {
982 {
eab5fd67
JCPV		 983 .start = AT91SAM9263_BASE_RTT1,
984 .end = AT91SAM9263_BASE_RTT1 + SZ_16 - 1,
884f5a6a 985 .flags = IORESOURCE_MEM,
b3af8b49
JCPV		 986 }, {
987 .flags = IORESOURCE_MEM,
884f5a6a
AV		 988 }
989};
990
991static struct platform_device at91sam9263_rtt1_device = {
992 .name = "at91_rtt",
993 .id = 1,
994 .resource = rtt1_resources,
884f5a6a
AV		 995};
996
205056a3
JCPV		 997#if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9)
998static void __init at91_add_device_rtt_rtc(void)
999{
1000 struct platform_device *pdev;
b3af8b49 1001 struct resource *r;
205056a3
JCPV		 1002
1003 switch (CONFIG_RTC_DRV_AT91SAM9_RTT) {
1004 case 0:
b3af8b49
JCPV		 1005 /*
1006 * The second resource is needed only for the chosen RTT:
1007 * GPBR will serve as the storage for RTC time offset
1008 */
1009 at91sam9263_rtt0_device.num_resources = 2;
1010 at91sam9263_rtt1_device.num_resources = 1;
205056a3 1011 pdev = &at91sam9263_rtt0_device;
b3af8b49 1012 r = rtt0_resources;
205056a3
JCPV		 1013 break;
1014 case 1:
b3af8b49
JCPV		 1015 at91sam9263_rtt0_device.num_resources = 1;
1016 at91sam9263_rtt1_device.num_resources = 2;
205056a3 1017 pdev = &at91sam9263_rtt1_device;
b3af8b49 1018 r = rtt1_resources;
205056a3
JCPV		 1019 break;
1020 default:
b3af8b49
JCPV		 1021 pr_err("at91sam9263: only supports 2 RTT (%d)\n",
1022 CONFIG_RTC_DRV_AT91SAM9_RTT);
205056a3
JCPV		 1023 return;
1024 }
1025
1026 pdev->name = "rtc-at91sam9";
b3af8b49
JCPV		 1027 r[1].start = AT91SAM9263_BASE_GPBR + 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR;
1028 r[1].end = r[1].start + 3;
205056a3
JCPV		 1029}
1030#else
b3af8b49
JCPV		 1031static void __init at91_add_device_rtt_rtc(void)
1032{
1033 /* Only one resource is needed: RTT not used as RTC */
1034 at91sam9263_rtt0_device.num_resources = 1;
1035 at91sam9263_rtt1_device.num_resources = 1;
1036}
205056a3
JCPV		 1037#endif
1038
884f5a6a
AV		 1039static void __init at91_add_device_rtt(void)
1040{
205056a3 1041 at91_add_device_rtt_rtc();
884f5a6a
AV		 1042 platform_device_register(&at91sam9263_rtt0_device);
1043 platform_device_register(&at91sam9263_rtt1_device);
1044}
1045
1046
1047/* --------------------------------------------------------------------
1048 * Watchdog
1049 * -------------------------------------------------------------------- */
1050
2af29b78 1051#if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
c1c30a29
JCPV		 1052static struct resource wdt_resources[] = {
1053 {
1054 .start = AT91SAM9263_BASE_WDT,
1055 .end = AT91SAM9263_BASE_WDT + SZ_16 - 1,
1056 .flags = IORESOURCE_MEM,
1057 }
1058};
1059
884f5a6a
AV		 1060static struct platform_device at91sam9263_wdt_device = {
1061 .name = "at91_wdt",
1062 .id = -1,
c1c30a29
JCPV		 1063 .resource = wdt_resources,
1064 .num_resources = ARRAY_SIZE(wdt_resources),
884f5a6a
AV		 1065};
1066
1067static void __init at91_add_device_watchdog(void)
1068{
1069 platform_device_register(&at91sam9263_wdt_device);
1070}
1071#else
1072static void __init at91_add_device_watchdog(void) {}
1073#endif
1074
1075
bb1ad68b
AV		 1076/* --------------------------------------------------------------------
1077 * PWM
1078 * --------------------------------------------------------------------*/
1079
1080#if defined(CONFIG_ATMEL_PWM)
1081static u32 pwm_mask;
1082
1083static struct resource pwm_resources[] = {
1084 [0] = {
1085 .start = AT91SAM9263_BASE_PWMC,
1086 .end = AT91SAM9263_BASE_PWMC + SZ_16K - 1,
1087 .flags = IORESOURCE_MEM,
1088 },
1089 [1] = {
1090 .start = AT91SAM9263_ID_PWMC,
1091 .end = AT91SAM9263_ID_PWMC,
1092 .flags = IORESOURCE_IRQ,
1093 },
1094};
1095
1096static struct platform_device at91sam9263_pwm0_device = {
1097 .name = "atmel_pwm",
1098 .id = -1,
1099 .dev = {
1100 .platform_data = &pwm_mask,
1101 },
1102 .resource = pwm_resources,
1103 .num_resources = ARRAY_SIZE(pwm_resources),
1104};
1105
1106void __init at91_add_device_pwm(u32 mask)
1107{
1108 if (mask & (1 << AT91_PWM0))
1109 at91_set_B_periph(AT91_PIN_PB7, 1); /* enable PWM0 */
1110
1111 if (mask & (1 << AT91_PWM1))
1112 at91_set_B_periph(AT91_PIN_PB8, 1); /* enable PWM1 */
1113
1114 if (mask & (1 << AT91_PWM2))
1115 at91_set_B_periph(AT91_PIN_PC29, 1); /* enable PWM2 */
1116
1117 if (mask & (1 << AT91_PWM3))
1118 at91_set_B_periph(AT91_PIN_PB29, 1); /* enable PWM3 */
1119
1120 pwm_mask = mask;
1121
1122 platform_device_register(&at91sam9263_pwm0_device);
1123}
1124#else
1125void __init at91_add_device_pwm(u32 mask) {}
1126#endif
1127
1128
bfbc3266
AV		 1129/* --------------------------------------------------------------------
1130 * SSC -- Synchronous Serial Controller
1131 * -------------------------------------------------------------------- */
1132
1133#if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
1134static u64 ssc0_dmamask = DMA_BIT_MASK(32);
1135
1136static struct resource ssc0_resources[] = {
1137 [0] = {
1138 .start = AT91SAM9263_BASE_SSC0,
1139 .end = AT91SAM9263_BASE_SSC0 + SZ_16K - 1,
1140 .flags = IORESOURCE_MEM,
1141 },
1142 [1] = {
1143 .start = AT91SAM9263_ID_SSC0,
1144 .end = AT91SAM9263_ID_SSC0,
1145 .flags = IORESOURCE_IRQ,
1146 },
1147};
1148
1149static struct platform_device at91sam9263_ssc0_device = {
1150 .name = "ssc",
1151 .id = 0,
1152 .dev = {
1153 .dma_mask = &ssc0_dmamask,
1154 .coherent_dma_mask = DMA_BIT_MASK(32),
1155 },
1156 .resource = ssc0_resources,
1157 .num_resources = ARRAY_SIZE(ssc0_resources),
1158};
1159
1160static inline void configure_ssc0_pins(unsigned pins)
1161{
1162 if (pins & ATMEL_SSC_TF)
1163 at91_set_B_periph(AT91_PIN_PB0, 1);
1164 if (pins & ATMEL_SSC_TK)
1165 at91_set_B_periph(AT91_PIN_PB1, 1);
1166 if (pins & ATMEL_SSC_TD)
1167 at91_set_B_periph(AT91_PIN_PB2, 1);
1168 if (pins & ATMEL_SSC_RD)
1169 at91_set_B_periph(AT91_PIN_PB3, 1);
1170 if (pins & ATMEL_SSC_RK)
1171 at91_set_B_periph(AT91_PIN_PB4, 1);
1172 if (pins & ATMEL_SSC_RF)
1173 at91_set_B_periph(AT91_PIN_PB5, 1);
1174}
1175
1176static u64 ssc1_dmamask = DMA_BIT_MASK(32);
1177
1178static struct resource ssc1_resources[] = {
1179 [0] = {
1180 .start = AT91SAM9263_BASE_SSC1,
1181 .end = AT91SAM9263_BASE_SSC1 + SZ_16K - 1,
1182 .flags = IORESOURCE_MEM,
1183 },
1184 [1] = {
1185 .start = AT91SAM9263_ID_SSC1,
1186 .end = AT91SAM9263_ID_SSC1,
1187 .flags = IORESOURCE_IRQ,
1188 },
1189};
1190
1191static struct platform_device at91sam9263_ssc1_device = {
1192 .name = "ssc",
1193 .id = 1,
1194 .dev = {
1195 .dma_mask = &ssc1_dmamask,
1196 .coherent_dma_mask = DMA_BIT_MASK(32),
1197 },
1198 .resource = ssc1_resources,
1199 .num_resources = ARRAY_SIZE(ssc1_resources),
1200};
1201
1202static inline void configure_ssc1_pins(unsigned pins)
1203{
1204 if (pins & ATMEL_SSC_TF)
1205 at91_set_A_periph(AT91_PIN_PB6, 1);
1206 if (pins & ATMEL_SSC_TK)
1207 at91_set_A_periph(AT91_PIN_PB7, 1);
1208 if (pins & ATMEL_SSC_TD)
1209 at91_set_A_periph(AT91_PIN_PB8, 1);
1210 if (pins & ATMEL_SSC_RD)
1211 at91_set_A_periph(AT91_PIN_PB9, 1);
1212 if (pins & ATMEL_SSC_RK)
1213 at91_set_A_periph(AT91_PIN_PB10, 1);
1214 if (pins & ATMEL_SSC_RF)
1215 at91_set_A_periph(AT91_PIN_PB11, 1);
1216}
1217
1218/*
bfbc3266
AV		 1219 * SSC controllers are accessed through library code, instead of any
1220 * kind of all-singing/all-dancing driver. For example one could be
1221 * used by a particular I2S audio codec's driver, while another one
1222 * on the same system might be used by a custom data capture driver.
1223 */
1224void __init at91_add_device_ssc(unsigned id, unsigned pins)
1225{
1226 struct platform_device *pdev;
1227
1228 /*
1229 * NOTE: caller is responsible for passing information matching
1230 * "pins" to whatever will be using each particular controller.
1231 */
1232 switch (id) {
1233 case AT91SAM9263_ID_SSC0:
1234 pdev = &at91sam9263_ssc0_device;
1235 configure_ssc0_pins(pins);
bfbc3266
AV		 1236 break;
1237 case AT91SAM9263_ID_SSC1:
1238 pdev = &at91sam9263_ssc1_device;
1239 configure_ssc1_pins(pins);
bfbc3266
AV		 1240 break;
1241 default:
1242 return;
1243 }
1244
1245 platform_device_register(pdev);
1246}
1247
1248#else
1249void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
1250#endif
1251
1252
b2c65616
AV		 1253/* --------------------------------------------------------------------
1254 * UART
1255 * -------------------------------------------------------------------- */
1256
1257#if defined(CONFIG_SERIAL_ATMEL)
1258
1259static struct resource dbgu_resources[] = {
1260 [0] = {
13079a73
JCPV		 1261 .start = AT91SAM9263_BASE_DBGU,
1262 .end = AT91SAM9263_BASE_DBGU + SZ_512 - 1,
b2c65616
AV		 1263 .flags = IORESOURCE_MEM,
1264 },
1265 [1] = {
1266 .start = AT91_ID_SYS,
1267 .end = AT91_ID_SYS,
1268 .flags = IORESOURCE_IRQ,
1269 },
1270};
1271
1272static struct atmel_uart_data dbgu_data = {
1273 .use_dma_tx = 0,
1274 .use_dma_rx = 0, /* DBGU not capable of receive DMA */
b2c65616
AV		 1275};
1276
c6686ff9
AV		 1277static u64 dbgu_dmamask = DMA_BIT_MASK(32);
1278
b2c65616
AV		 1279static struct platform_device at91sam9263_dbgu_device = {
1280 .name = "atmel_usart",
1281 .id = 0,
1282 .dev = {
c6686ff9
AV		 1283 .dma_mask = &dbgu_dmamask,
1284 .coherent_dma_mask = DMA_BIT_MASK(32),
1285 .platform_data = &dbgu_data,
b2c65616
AV		 1286 },
1287 .resource = dbgu_resources,
1288 .num_resources = ARRAY_SIZE(dbgu_resources),
1289};
1290
1291static inline void configure_dbgu_pins(void)
1292{
1293 at91_set_A_periph(AT91_PIN_PC30, 0); /* DRXD */
1294 at91_set_A_periph(AT91_PIN_PC31, 1); /* DTXD */
1295}
1296
1297static struct resource uart0_resources[] = {
1298 [0] = {
1299 .start = AT91SAM9263_BASE_US0,
1300 .end = AT91SAM9263_BASE_US0 + SZ_16K - 1,
1301 .flags = IORESOURCE_MEM,
1302 },
1303 [1] = {
1304 .start = AT91SAM9263_ID_US0,
1305 .end = AT91SAM9263_ID_US0,
1306 .flags = IORESOURCE_IRQ,
1307 },
1308};
1309
1310static struct atmel_uart_data uart0_data = {
1311 .use_dma_tx = 1,
1312 .use_dma_rx = 1,
1313};
1314
c6686ff9
AV		 1315static u64 uart0_dmamask = DMA_BIT_MASK(32);
1316
b2c65616
AV		 1317static struct platform_device at91sam9263_uart0_device = {
1318 .name = "atmel_usart",
1319 .id = 1,
1320 .dev = {
c6686ff9
AV		 1321 .dma_mask = &uart0_dmamask,
1322 .coherent_dma_mask = DMA_BIT_MASK(32),
1323 .platform_data = &uart0_data,
b2c65616
AV		 1324 },
1325 .resource = uart0_resources,
1326 .num_resources = ARRAY_SIZE(uart0_resources),
1327};
1328
c8f385a6 1329static inline void configure_usart0_pins(unsigned pins)
b2c65616
AV		 1330{
1331 at91_set_A_periph(AT91_PIN_PA26, 1); /* TXD0 */
1332 at91_set_A_periph(AT91_PIN_PA27, 0); /* RXD0 */
c8f385a6
AV		 1333
1334 if (pins & ATMEL_UART_RTS)
1335 at91_set_A_periph(AT91_PIN_PA28, 0); /* RTS0 */
1336 if (pins & ATMEL_UART_CTS)
1337 at91_set_A_periph(AT91_PIN_PA29, 0); /* CTS0 */
b2c65616
AV		 1338}
1339
1340static struct resource uart1_resources[] = {
1341 [0] = {
1342 .start = AT91SAM9263_BASE_US1,
1343 .end = AT91SAM9263_BASE_US1 + SZ_16K - 1,
1344 .flags = IORESOURCE_MEM,
1345 },
1346 [1] = {
1347 .start = AT91SAM9263_ID_US1,
1348 .end = AT91SAM9263_ID_US1,
1349 .flags = IORESOURCE_IRQ,
1350 },
1351};
1352
1353static struct atmel_uart_data uart1_data = {
1354 .use_dma_tx = 1,
1355 .use_dma_rx = 1,
1356};
1357
c6686ff9
AV		 1358static u64 uart1_dmamask = DMA_BIT_MASK(32);
1359
b2c65616
AV		 1360static struct platform_device at91sam9263_uart1_device = {
1361 .name = "atmel_usart",
1362 .id = 2,
1363 .dev = {
c6686ff9
AV		 1364 .dma_mask = &uart1_dmamask,
1365 .coherent_dma_mask = DMA_BIT_MASK(32),
1366 .platform_data = &uart1_data,
b2c65616
AV		 1367 },
1368 .resource = uart1_resources,
1369 .num_resources = ARRAY_SIZE(uart1_resources),
1370};
1371
c8f385a6 1372static inline void configure_usart1_pins(unsigned pins)
b2c65616
AV		 1373{
1374 at91_set_A_periph(AT91_PIN_PD0, 1); /* TXD1 */
1375 at91_set_A_periph(AT91_PIN_PD1, 0); /* RXD1 */
c8f385a6
AV		 1376
1377 if (pins & ATMEL_UART_RTS)
1378 at91_set_B_periph(AT91_PIN_PD7, 0); /* RTS1 */
1379 if (pins & ATMEL_UART_CTS)
1380 at91_set_B_periph(AT91_PIN_PD8, 0); /* CTS1 */
b2c65616
AV		 1381}
1382
1383static struct resource uart2_resources[] = {
1384 [0] = {
1385 .start = AT91SAM9263_BASE_US2,
1386 .end = AT91SAM9263_BASE_US2 + SZ_16K - 1,
1387 .flags = IORESOURCE_MEM,
1388 },
1389 [1] = {
1390 .start = AT91SAM9263_ID_US2,
1391 .end = AT91SAM9263_ID_US2,
1392 .flags = IORESOURCE_IRQ,
1393 },
1394};
1395
1396static struct atmel_uart_data uart2_data = {
1397 .use_dma_tx = 1,
1398 .use_dma_rx = 1,
1399};
1400
c6686ff9
AV		 1401static u64 uart2_dmamask = DMA_BIT_MASK(32);
1402
b2c65616
AV		 1403static struct platform_device at91sam9263_uart2_device = {
1404 .name = "atmel_usart",
1405 .id = 3,
1406 .dev = {
c6686ff9
AV		 1407 .dma_mask = &uart2_dmamask,
1408 .coherent_dma_mask = DMA_BIT_MASK(32),
1409 .platform_data = &uart2_data,
b2c65616
AV		 1410 },
1411 .resource = uart2_resources,
1412 .num_resources = ARRAY_SIZE(uart2_resources),
1413};
1414
c8f385a6 1415static inline void configure_usart2_pins(unsigned pins)
b2c65616
AV		 1416{
1417 at91_set_A_periph(AT91_PIN_PD2, 1); /* TXD2 */
1418 at91_set_A_periph(AT91_PIN_PD3, 0); /* RXD2 */
c8f385a6
AV		 1419
1420 if (pins & ATMEL_UART_RTS)
1421 at91_set_B_periph(AT91_PIN_PD5, 0); /* RTS2 */
1422 if (pins & ATMEL_UART_CTS)
1423 at91_set_B_periph(AT91_PIN_PD6, 0); /* CTS2 */
b2c65616
AV		 1424}
1425
11aadac4 1426static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
b2c65616 1427
c8f385a6
AV		 1428void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1429{
1430 struct platform_device *pdev;
2b348e2f 1431 struct atmel_uart_data *pdata;
c8f385a6
AV		 1432
1433 switch (id) {
1434 case 0: /* DBGU */
1435 pdev = &at91sam9263_dbgu_device;
1436 configure_dbgu_pins();
c8f385a6
AV		 1437 break;
1438 case AT91SAM9263_ID_US0:
1439 pdev = &at91sam9263_uart0_device;
1440 configure_usart0_pins(pins);
c8f385a6
AV		 1441 break;
1442 case AT91SAM9263_ID_US1:
1443 pdev = &at91sam9263_uart1_device;
1444 configure_usart1_pins(pins);
c8f385a6
AV		 1445 break;
1446 case AT91SAM9263_ID_US2:
1447 pdev = &at91sam9263_uart2_device;
1448 configure_usart2_pins(pins);
c8f385a6
AV		 1449 break;
1450 default:
1451 return;
1452 }
2b348e2f
JCPV		 1453 pdata = pdev->dev.platform_data;
1454 pdata->num = portnr; /* update to mapped ID */
c8f385a6
AV		 1455
1456 if (portnr < ATMEL_MAX_UART)
1457 at91_uarts[portnr] = pdev;
1458}
1459
1460void __init at91_set_serial_console(unsigned portnr)
1461{
bd602995 1462 if (portnr < ATMEL_MAX_UART) {
c8f385a6 1463 atmel_default_console_device = at91_uarts[portnr];
5c1f9668 1464 at91sam9263_set_console_clock(at91_uarts[portnr]->id);
bd602995 1465 }
c8f385a6
AV		 1466}
1467
b2c65616
AV		 1468void __init at91_add_device_serial(void)
1469{
1470 int i;
1471
1472 for (i = 0; i < ATMEL_MAX_UART; i++) {
1473 if (at91_uarts[i])
1474 platform_device_register(at91_uarts[i]);
1475 }
11aadac4
AV		 1476
1477 if (!atmel_default_console_device)
1478 printk(KERN_INFO "AT91: No default serial console defined.\n");
b2c65616
AV		 1479}
1480#else
c8f385a6
AV		 1481void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1482void __init at91_set_serial_console(unsigned portnr) {}
b2c65616
AV		 1483void __init at91_add_device_serial(void) {}
1484#endif
1485
1486
1487/* -------------------------------------------------------------------- */
1488/*
1489 * These devices are always present and don't need any board-specific
1490 * setup.
1491 */
1492static int __init at91_add_standard_devices(void)
1493{
884f5a6a
AV		 1494 at91_add_device_rtt();
1495 at91_add_device_watchdog();
e5f40bfa 1496 at91_add_device_tc();
b2c65616
AV		 1497 return 0;
1498}
1499
1500arch_initcall(at91_add_standard_devices);
Linux kernel - Deliverables
This page took 1.264158 seconds and 5 git commands to generate.