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Merge branch 'drm-next' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied...
[deliverable/linux.git] / arch / arm / mach-at91 / at91sam9263_devices.c
CommitLineData
b2c65616
AV		 1/*
2 * arch/arm/mach-at91/at91sam9263_devices.c
3 *
4 * Copyright (C) 2007 Atmel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 */
12#include <asm/mach/arch.h>
13#include <asm/mach/map.h>
14
c6686ff9 15#include <linux/dma-mapping.h>
b2c65616 16#include <linux/platform_device.h>
f230d3f5 17#include <linux/i2c-gpio.h>
b2c65616 18
f230d3f5 19#include <linux/fb.h>
b8b78609
JA		 20#include <video/atmel_lcdc.h>
21
a09e64fb
RK		 22#include <mach/board.h>
23#include <mach/gpio.h>
24#include <mach/at91sam9263.h>
25#include <mach/at91sam9263_matrix.h>
26#include <mach/at91sam9_smc.h>
b2c65616
AV		 27
28#include "generic.h"
29
b2c65616
AV		 30
31/* --------------------------------------------------------------------
32 * USB Host
33 * -------------------------------------------------------------------- */
34
35#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
c6686ff9 36static u64 ohci_dmamask = DMA_BIT_MASK(32);
b2c65616
AV		 37static struct at91_usbh_data usbh_data;
38
39static struct resource usbh_resources[] = {
40 [0] = {
41 .start = AT91SAM9263_UHP_BASE,
42 .end = AT91SAM9263_UHP_BASE + SZ_1M - 1,
43 .flags = IORESOURCE_MEM,
44 },
45 [1] = {
46 .start = AT91SAM9263_ID_UHP,
47 .end = AT91SAM9263_ID_UHP,
48 .flags = IORESOURCE_IRQ,
49 },
50};
51
52static struct platform_device at91_usbh_device = {
53 .name = "at91_ohci",
54 .id = -1,
55 .dev = {
56 .dma_mask = &ohci_dmamask,
c6686ff9 57 .coherent_dma_mask = DMA_BIT_MASK(32),
b2c65616
AV		 58 .platform_data = &usbh_data,
59 },
60 .resource = usbh_resources,
61 .num_resources = ARRAY_SIZE(usbh_resources),
62};
63
64void __init at91_add_device_usbh(struct at91_usbh_data *data)
65{
66 int i;
67
68 if (!data)
69 return;
70
71 /* Enable VBus control for UHP ports */
72 for (i = 0; i < data->ports; i++) {
73 if (data->vbus_pin[i])
74 at91_set_gpio_output(data->vbus_pin[i], 0);
75 }
76
77 usbh_data = *data;
78 platform_device_register(&at91_usbh_device);
79}
80#else
81void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
82#endif
83
84
85/* --------------------------------------------------------------------
86 * USB Device (Gadget)
87 * -------------------------------------------------------------------- */
88
89#ifdef CONFIG_USB_GADGET_AT91
90static struct at91_udc_data udc_data;
91
92static struct resource udc_resources[] = {
93 [0] = {
94 .start = AT91SAM9263_BASE_UDP,
95 .end = AT91SAM9263_BASE_UDP + SZ_16K - 1,
96 .flags = IORESOURCE_MEM,
97 },
98 [1] = {
99 .start = AT91SAM9263_ID_UDP,
100 .end = AT91SAM9263_ID_UDP,
101 .flags = IORESOURCE_IRQ,
102 },
103};
104
105static struct platform_device at91_udc_device = {
106 .name = "at91_udc",
107 .id = -1,
108 .dev = {
109 .platform_data = &udc_data,
110 },
111 .resource = udc_resources,
112 .num_resources = ARRAY_SIZE(udc_resources),
113};
114
115void __init at91_add_device_udc(struct at91_udc_data *data)
116{
117 if (!data)
118 return;
119
120 if (data->vbus_pin) {
121 at91_set_gpio_input(data->vbus_pin, 0);
122 at91_set_deglitch(data->vbus_pin, 1);
123 }
124
125 /* Pullup pin is handled internally by USB device peripheral */
126
127 udc_data = *data;
128 platform_device_register(&at91_udc_device);
129}
130#else
131void __init at91_add_device_udc(struct at91_udc_data *data) {}
132#endif
133
134
135/* --------------------------------------------------------------------
136 * Ethernet
137 * -------------------------------------------------------------------- */
138
139#if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
c6686ff9 140static u64 eth_dmamask = DMA_BIT_MASK(32);
b2c65616
AV		 141static struct at91_eth_data eth_data;
142
143static struct resource eth_resources[] = {
144 [0] = {
145 .start = AT91SAM9263_BASE_EMAC,
146 .end = AT91SAM9263_BASE_EMAC + SZ_16K - 1,
147 .flags = IORESOURCE_MEM,
148 },
149 [1] = {
150 .start = AT91SAM9263_ID_EMAC,
151 .end = AT91SAM9263_ID_EMAC,
152 .flags = IORESOURCE_IRQ,
153 },
154};
155
156static struct platform_device at91sam9263_eth_device = {
157 .name = "macb",
158 .id = -1,
159 .dev = {
160 .dma_mask = &eth_dmamask,
c6686ff9 161 .coherent_dma_mask = DMA_BIT_MASK(32),
b2c65616
AV		 162 .platform_data = &eth_data,
163 },
164 .resource = eth_resources,
165 .num_resources = ARRAY_SIZE(eth_resources),
166};
167
168void __init at91_add_device_eth(struct at91_eth_data *data)
169{
170 if (!data)
171 return;
172
173 if (data->phy_irq_pin) {
174 at91_set_gpio_input(data->phy_irq_pin, 0);
175 at91_set_deglitch(data->phy_irq_pin, 1);
176 }
177
178 /* Pins used for MII and RMII */
179 at91_set_A_periph(AT91_PIN_PE21, 0); /* ETXCK_EREFCK */
180 at91_set_B_periph(AT91_PIN_PC25, 0); /* ERXDV */
181 at91_set_A_periph(AT91_PIN_PE25, 0); /* ERX0 */
182 at91_set_A_periph(AT91_PIN_PE26, 0); /* ERX1 */
183 at91_set_A_periph(AT91_PIN_PE27, 0); /* ERXER */
184 at91_set_A_periph(AT91_PIN_PE28, 0); /* ETXEN */
185 at91_set_A_periph(AT91_PIN_PE23, 0); /* ETX0 */
186 at91_set_A_periph(AT91_PIN_PE24, 0); /* ETX1 */
187 at91_set_A_periph(AT91_PIN_PE30, 0); /* EMDIO */
188 at91_set_A_periph(AT91_PIN_PE29, 0); /* EMDC */
189
190 if (!data->is_rmii) {
191 at91_set_A_periph(AT91_PIN_PE22, 0); /* ECRS */
192 at91_set_B_periph(AT91_PIN_PC26, 0); /* ECOL */
193 at91_set_B_periph(AT91_PIN_PC22, 0); /* ERX2 */
194 at91_set_B_periph(AT91_PIN_PC23, 0); /* ERX3 */
195 at91_set_B_periph(AT91_PIN_PC27, 0); /* ERXCK */
196 at91_set_B_periph(AT91_PIN_PC20, 0); /* ETX2 */
197 at91_set_B_periph(AT91_PIN_PC21, 0); /* ETX3 */
198 at91_set_B_periph(AT91_PIN_PC24, 0); /* ETXER */
199 }
200
201 eth_data = *data;
202 platform_device_register(&at91sam9263_eth_device);
203}
204#else
205void __init at91_add_device_eth(struct at91_eth_data *data) {}
206#endif
207
208
209/* --------------------------------------------------------------------
210 * MMC / SD
211 * -------------------------------------------------------------------- */
212
213#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
c6686ff9 214static u64 mmc_dmamask = DMA_BIT_MASK(32);
b2c65616
AV		 215static struct at91_mmc_data mmc0_data, mmc1_data;
216
217static struct resource mmc0_resources[] = {
218 [0] = {
219 .start = AT91SAM9263_BASE_MCI0,
220 .end = AT91SAM9263_BASE_MCI0 + SZ_16K - 1,
221 .flags = IORESOURCE_MEM,
222 },
223 [1] = {
224 .start = AT91SAM9263_ID_MCI0,
225 .end = AT91SAM9263_ID_MCI0,
226 .flags = IORESOURCE_IRQ,
227 },
228};
229
230static struct platform_device at91sam9263_mmc0_device = {
231 .name = "at91_mci",
232 .id = 0,
233 .dev = {
234 .dma_mask = &mmc_dmamask,
c6686ff9 235 .coherent_dma_mask = DMA_BIT_MASK(32),
b2c65616
AV		 236 .platform_data = &mmc0_data,
237 },
238 .resource = mmc0_resources,
239 .num_resources = ARRAY_SIZE(mmc0_resources),
240};
241
242static struct resource mmc1_resources[] = {
243 [0] = {
244 .start = AT91SAM9263_BASE_MCI1,
245 .end = AT91SAM9263_BASE_MCI1 + SZ_16K - 1,
246 .flags = IORESOURCE_MEM,
247 },
248 [1] = {
249 .start = AT91SAM9263_ID_MCI1,
250 .end = AT91SAM9263_ID_MCI1,
251 .flags = IORESOURCE_IRQ,
252 },
253};
254
255static struct platform_device at91sam9263_mmc1_device = {
256 .name = "at91_mci",
257 .id = 1,
258 .dev = {
259 .dma_mask = &mmc_dmamask,
c6686ff9 260 .coherent_dma_mask = DMA_BIT_MASK(32),
b2c65616
AV		 261 .platform_data = &mmc1_data,
262 },
263 .resource = mmc1_resources,
264 .num_resources = ARRAY_SIZE(mmc1_resources),
265};
266
267void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
268{
269 if (!data)
270 return;
271
272 /* input/irq */
273 if (data->det_pin) {
274 at91_set_gpio_input(data->det_pin, 1);
275 at91_set_deglitch(data->det_pin, 1);
276 }
277 if (data->wp_pin)
278 at91_set_gpio_input(data->wp_pin, 1);
279 if (data->vcc_pin)
280 at91_set_gpio_output(data->vcc_pin, 0);
281
282 if (mmc_id == 0) { /* MCI0 */
283 /* CLK */
284 at91_set_A_periph(AT91_PIN_PA12, 0);
285
286 if (data->slot_b) {
287 /* CMD */
288 at91_set_A_periph(AT91_PIN_PA16, 1);
289
290 /* DAT0, maybe DAT1..DAT3 */
291 at91_set_A_periph(AT91_PIN_PA17, 1);
292 if (data->wire4) {
293 at91_set_A_periph(AT91_PIN_PA18, 1);
294 at91_set_A_periph(AT91_PIN_PA19, 1);
295 at91_set_A_periph(AT91_PIN_PA20, 1);
296 }
297 } else {
298 /* CMD */
299 at91_set_A_periph(AT91_PIN_PA1, 1);
300
301 /* DAT0, maybe DAT1..DAT3 */
302 at91_set_A_periph(AT91_PIN_PA0, 1);
303 if (data->wire4) {
304 at91_set_A_periph(AT91_PIN_PA3, 1);
305 at91_set_A_periph(AT91_PIN_PA4, 1);
306 at91_set_A_periph(AT91_PIN_PA5, 1);
307 }
308 }
309
310 mmc0_data = *data;
fb8b131b 311 at91_clock_associate("mci0_clk", &at91sam9263_mmc0_device.dev, "mci_clk");
b2c65616
AV		 312 platform_device_register(&at91sam9263_mmc0_device);
313 } else { /* MCI1 */
314 /* CLK */
315 at91_set_A_periph(AT91_PIN_PA6, 0);
316
317 if (data->slot_b) {
318 /* CMD */
319 at91_set_A_periph(AT91_PIN_PA21, 1);
320
321 /* DAT0, maybe DAT1..DAT3 */
322 at91_set_A_periph(AT91_PIN_PA22, 1);
323 if (data->wire4) {
324 at91_set_A_periph(AT91_PIN_PA23, 1);
325 at91_set_A_periph(AT91_PIN_PA24, 1);
326 at91_set_A_periph(AT91_PIN_PA25, 1);
327 }
328 } else {
329 /* CMD */
330 at91_set_A_periph(AT91_PIN_PA7, 1);
331
332 /* DAT0, maybe DAT1..DAT3 */
333 at91_set_A_periph(AT91_PIN_PA8, 1);
334 if (data->wire4) {
335 at91_set_A_periph(AT91_PIN_PA9, 1);
336 at91_set_A_periph(AT91_PIN_PA10, 1);
337 at91_set_A_periph(AT91_PIN_PA11, 1);
338 }
339 }
340
341 mmc1_data = *data;
342 at91_clock_associate("mci1_clk", &at91sam9263_mmc1_device.dev, "mci_clk");
343 platform_device_register(&at91sam9263_mmc1_device);
344 }
345}
346#else
347void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
348#endif
349
350
351/* --------------------------------------------------------------------
352 * NAND / SmartMedia
353 * -------------------------------------------------------------------- */
354
f6ed6f78 355#if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
3c3796cc 356static struct atmel_nand_data nand_data;
b2c65616
AV		 357
358#define NAND_BASE AT91_CHIPSELECT_3
359
360static struct resource nand_resources[] = {
d7a2415f 361 [0] = {
b2c65616
AV		 362 .start = NAND_BASE,
363 .end = NAND_BASE + SZ_256M - 1,
364 .flags = IORESOURCE_MEM,
d7a2415f
AV		 365 },
366 [1] = {
367 .start = AT91_BASE_SYS + AT91_ECC0,
368 .end = AT91_BASE_SYS + AT91_ECC0 + SZ_512 - 1,
369 .flags = IORESOURCE_MEM,
b2c65616
AV		 370 }
371};
372
373static struct platform_device at91sam9263_nand_device = {
3c3796cc 374 .name = "atmel_nand",
b2c65616
AV		 375 .id = -1,
376 .dev = {
377 .platform_data = &nand_data,
378 },
379 .resource = nand_resources,
380 .num_resources = ARRAY_SIZE(nand_resources),
381};
382
3c3796cc 383void __init at91_add_device_nand(struct atmel_nand_data *data)
b2c65616
AV		 384{
385 unsigned long csa, mode;
386
387 if (!data)
388 return;
389
390 csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
22823558 391 at91_sys_write(AT91_MATRIX_EBI0CSA, csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
b2c65616
AV		 392
393 /* set the bus interface characteristics */
16074b66
PV		 394 at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0)
395 | AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
b2c65616
AV		 396
397 at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3)
398 | AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
399
400 at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
401
402 if (data->bus_width_16)
403 mode = AT91_SMC_DBW_16;
404 else
405 mode = AT91_SMC_DBW_8;
406 at91_sys_write(AT91_SMC_MODE(3), mode | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(2));
407
408 /* enable pin */
409 if (data->enable_pin)
410 at91_set_gpio_output(data->enable_pin, 1);
411
412 /* ready/busy pin */
413 if (data->rdy_pin)
414 at91_set_gpio_input(data->rdy_pin, 1);
415
416 /* card detect pin */
417 if (data->det_pin)
418 at91_set_gpio_input(data->det_pin, 1);
419
420 nand_data = *data;
421 platform_device_register(&at91sam9263_nand_device);
422}
423#else
3c3796cc 424void __init at91_add_device_nand(struct atmel_nand_data *data) {}
b2c65616
AV		 425#endif
426
427
428/* --------------------------------------------------------------------
429 * TWI (i2c)
430 * -------------------------------------------------------------------- */
431
f230d3f5
AV		 432/*
433 * Prefer the GPIO code since the TWI controller isn't robust
434 * (gets overruns and underruns under load) and can only issue
435 * repeated STARTs in one scenario (the driver doesn't yet handle them).
436 */
437#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
438
439static struct i2c_gpio_platform_data pdata = {
440 .sda_pin = AT91_PIN_PB4,
441 .sda_is_open_drain = 1,
442 .scl_pin = AT91_PIN_PB5,
443 .scl_is_open_drain = 1,
444 .udelay = 2, /* ~100 kHz */
445};
446
447static struct platform_device at91sam9263_twi_device = {
448 .name = "i2c-gpio",
449 .id = -1,
450 .dev.platform_data = &pdata,
451};
452
453void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
454{
455 at91_set_GPIO_periph(AT91_PIN_PB4, 1); /* TWD (SDA) */
456 at91_set_multi_drive(AT91_PIN_PB4, 1);
457
458 at91_set_GPIO_periph(AT91_PIN_PB5, 1); /* TWCK (SCL) */
459 at91_set_multi_drive(AT91_PIN_PB5, 1);
460
461 i2c_register_board_info(0, devices, nr_devices);
462 platform_device_register(&at91sam9263_twi_device);
463}
464
465#elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
b2c65616
AV		 466
467static struct resource twi_resources[] = {
468 [0] = {
469 .start = AT91SAM9263_BASE_TWI,
470 .end = AT91SAM9263_BASE_TWI + SZ_16K - 1,
471 .flags = IORESOURCE_MEM,
472 },
473 [1] = {
474 .start = AT91SAM9263_ID_TWI,
475 .end = AT91SAM9263_ID_TWI,
476 .flags = IORESOURCE_IRQ,
477 },
478};
479
480static struct platform_device at91sam9263_twi_device = {
481 .name = "at91_i2c",
482 .id = -1,
483 .resource = twi_resources,
484 .num_resources = ARRAY_SIZE(twi_resources),
485};
486
f230d3f5 487void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
b2c65616
AV		 488{
489 /* pins used for TWI interface */
490 at91_set_A_periph(AT91_PIN_PB4, 0); /* TWD */
491 at91_set_multi_drive(AT91_PIN_PB4, 1);
492
493 at91_set_A_periph(AT91_PIN_PB5, 0); /* TWCK */
494 at91_set_multi_drive(AT91_PIN_PB5, 1);
495
f230d3f5 496 i2c_register_board_info(0, devices, nr_devices);
b2c65616
AV		 497 platform_device_register(&at91sam9263_twi_device);
498}
499#else
f230d3f5 500void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
b2c65616
AV		 501#endif
502
503
504/* --------------------------------------------------------------------
505 * SPI
506 * -------------------------------------------------------------------- */
507
508#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
c6686ff9 509static u64 spi_dmamask = DMA_BIT_MASK(32);
b2c65616
AV		 510
511static struct resource spi0_resources[] = {
512 [0] = {
513 .start = AT91SAM9263_BASE_SPI0,
514 .end = AT91SAM9263_BASE_SPI0 + SZ_16K - 1,
515 .flags = IORESOURCE_MEM,
516 },
517 [1] = {
518 .start = AT91SAM9263_ID_SPI0,
519 .end = AT91SAM9263_ID_SPI0,
520 .flags = IORESOURCE_IRQ,
521 },
522};
523
524static struct platform_device at91sam9263_spi0_device = {
525 .name = "atmel_spi",
526 .id = 0,
527 .dev = {
528 .dma_mask = &spi_dmamask,
c6686ff9 529 .coherent_dma_mask = DMA_BIT_MASK(32),
b2c65616
AV		 530 },
531 .resource = spi0_resources,
532 .num_resources = ARRAY_SIZE(spi0_resources),
533};
534
535static const unsigned spi0_standard_cs[4] = { AT91_PIN_PA5, AT91_PIN_PA3, AT91_PIN_PA4, AT91_PIN_PB11 };
536
537static struct resource spi1_resources[] = {
538 [0] = {
539 .start = AT91SAM9263_BASE_SPI1,
540 .end = AT91SAM9263_BASE_SPI1 + SZ_16K - 1,
541 .flags = IORESOURCE_MEM,
542 },
543 [1] = {
544 .start = AT91SAM9263_ID_SPI1,
545 .end = AT91SAM9263_ID_SPI1,
546 .flags = IORESOURCE_IRQ,
547 },
548};
549
550static struct platform_device at91sam9263_spi1_device = {
551 .name = "atmel_spi",
552 .id = 1,
553 .dev = {
554 .dma_mask = &spi_dmamask,
c6686ff9 555 .coherent_dma_mask = DMA_BIT_MASK(32),
b2c65616
AV		 556 },
557 .resource = spi1_resources,
558 .num_resources = ARRAY_SIZE(spi1_resources),
559};
560
561static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB15, AT91_PIN_PB16, AT91_PIN_PB17, AT91_PIN_PB18 };
562
563void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
564{
565 int i;
566 unsigned long cs_pin;
567 short enable_spi0 = 0;
568 short enable_spi1 = 0;
569
570 /* Choose SPI chip-selects */
571 for (i = 0; i < nr_devices; i++) {
572 if (devices[i].controller_data)
573 cs_pin = (unsigned long) devices[i].controller_data;
574 else if (devices[i].bus_num == 0)
575 cs_pin = spi0_standard_cs[devices[i].chip_select];
576 else
577 cs_pin = spi1_standard_cs[devices[i].chip_select];
578
579 if (devices[i].bus_num == 0)
580 enable_spi0 = 1;
581 else
582 enable_spi1 = 1;
583
584 /* enable chip-select pin */
585 at91_set_gpio_output(cs_pin, 1);
586
587 /* pass chip-select pin to driver */
588 devices[i].controller_data = (void *) cs_pin;
589 }
590
591 spi_register_board_info(devices, nr_devices);
592
593 /* Configure SPI bus(es) */
594 if (enable_spi0) {
595 at91_set_B_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
596 at91_set_B_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
7f6e2d99 597 at91_set_B_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */
b2c65616
AV		 598
599 at91_clock_associate("spi0_clk", &at91sam9263_spi0_device.dev, "spi_clk");
600 platform_device_register(&at91sam9263_spi0_device);
601 }
602 if (enable_spi1) {
603 at91_set_A_periph(AT91_PIN_PB12, 0); /* SPI1_MISO */
604 at91_set_A_periph(AT91_PIN_PB13, 0); /* SPI1_MOSI */
605 at91_set_A_periph(AT91_PIN_PB14, 0); /* SPI1_SPCK */
606
607 at91_clock_associate("spi1_clk", &at91sam9263_spi1_device.dev, "spi_clk");
608 platform_device_register(&at91sam9263_spi1_device);
609 }
610}
611#else
612void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
613#endif
614
615
7776a94c
AV		 616/* --------------------------------------------------------------------
617 * AC97
618 * -------------------------------------------------------------------- */
619
620#if defined(CONFIG_SND_AT91_AC97) || defined(CONFIG_SND_AT91_AC97_MODULE)
c6686ff9 621static u64 ac97_dmamask = DMA_BIT_MASK(32);
7776a94c
AV		 622static struct atmel_ac97_data ac97_data;
623
624static struct resource ac97_resources[] = {
625 [0] = {
626 .start = AT91SAM9263_BASE_AC97C,
627 .end = AT91SAM9263_BASE_AC97C + SZ_16K - 1,
628 .flags = IORESOURCE_MEM,
629 },
630 [1] = {
631 .start = AT91SAM9263_ID_AC97C,
632 .end = AT91SAM9263_ID_AC97C,
633 .flags = IORESOURCE_IRQ,
634 },
635};
636
637static struct platform_device at91sam9263_ac97_device = {
638 .name = "ac97c",
639 .id = 1,
640 .dev = {
641 .dma_mask = &ac97_dmamask,
c6686ff9 642 .coherent_dma_mask = DMA_BIT_MASK(32),
7776a94c
AV		 643 .platform_data = &ac97_data,
644 },
645 .resource = ac97_resources,
646 .num_resources = ARRAY_SIZE(ac97_resources),
647};
648
649void __init at91_add_device_ac97(struct atmel_ac97_data *data)
650{
651 if (!data)
652 return;
653
654 at91_set_A_periph(AT91_PIN_PB0, 0); /* AC97FS */
655 at91_set_A_periph(AT91_PIN_PB1, 0); /* AC97CK */
656 at91_set_A_periph(AT91_PIN_PB2, 0); /* AC97TX */
657 at91_set_A_periph(AT91_PIN_PB3, 0); /* AC97RX */
658
659 /* reset */
660 if (data->reset_pin)
661 at91_set_gpio_output(data->reset_pin, 0);
662
663 ac97_data = *ek_data;
664 platform_device_register(&at91sam9263_ac97_device);
665}
666#else
667void __init at91_add_device_ac97(struct atmel_ac97_data *data) {}
668#endif
669
670
671/* --------------------------------------------------------------------
672 * LCD Controller
673 * -------------------------------------------------------------------- */
674
675#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
c6686ff9 676static u64 lcdc_dmamask = DMA_BIT_MASK(32);
7776a94c
AV		 677static struct atmel_lcdfb_info lcdc_data;
678
679static struct resource lcdc_resources[] = {
680 [0] = {
681 .start = AT91SAM9263_LCDC_BASE,
682 .end = AT91SAM9263_LCDC_BASE + SZ_4K - 1,
683 .flags = IORESOURCE_MEM,
684 },
685 [1] = {
686 .start = AT91SAM9263_ID_LCDC,
687 .end = AT91SAM9263_ID_LCDC,
688 .flags = IORESOURCE_IRQ,
689 },
690};
691
692static struct platform_device at91_lcdc_device = {
693 .name = "atmel_lcdfb",
694 .id = 0,
695 .dev = {
696 .dma_mask = &lcdc_dmamask,
c6686ff9 697 .coherent_dma_mask = DMA_BIT_MASK(32),
7776a94c
AV		 698 .platform_data = &lcdc_data,
699 },
700 .resource = lcdc_resources,
701 .num_resources = ARRAY_SIZE(lcdc_resources),
702};
703
704void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
705{
706 if (!data)
707 return;
708
709 at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */
710 at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */
711 at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDDEN */
712 at91_set_B_periph(AT91_PIN_PB9, 0); /* LCDCC */
713 at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDD2 */
714 at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDD3 */
715 at91_set_A_periph(AT91_PIN_PC8, 0); /* LCDD4 */
716 at91_set_A_periph(AT91_PIN_PC9, 0); /* LCDD5 */
717 at91_set_A_periph(AT91_PIN_PC10, 0); /* LCDD6 */
718 at91_set_A_periph(AT91_PIN_PC11, 0); /* LCDD7 */
719 at91_set_A_periph(AT91_PIN_PC14, 0); /* LCDD10 */
720 at91_set_A_periph(AT91_PIN_PC15, 0); /* LCDD11 */
721 at91_set_A_periph(AT91_PIN_PC16, 0); /* LCDD12 */
722 at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD13 */
723 at91_set_A_periph(AT91_PIN_PC18, 0); /* LCDD14 */
724 at91_set_A_periph(AT91_PIN_PC19, 0); /* LCDD15 */
725 at91_set_A_periph(AT91_PIN_PC22, 0); /* LCDD18 */
726 at91_set_A_periph(AT91_PIN_PC23, 0); /* LCDD19 */
727 at91_set_A_periph(AT91_PIN_PC24, 0); /* LCDD20 */
728 at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD21 */
729 at91_set_A_periph(AT91_PIN_PC26, 0); /* LCDD22 */
730 at91_set_A_periph(AT91_PIN_PC27, 0); /* LCDD23 */
731
732 lcdc_data = *data;
733 platform_device_register(&at91_lcdc_device);
734}
735#else
736void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
737#endif
738
739
e2920802
AV		 740/* --------------------------------------------------------------------
741 * Image Sensor Interface
742 * -------------------------------------------------------------------- */
743
744#if defined(CONFIG_VIDEO_AT91_ISI) || defined(CONFIG_VIDEO_AT91_ISI_MODULE)
745
746struct resource isi_resources[] = {
747 [0] = {
748 .start = AT91SAM9263_BASE_ISI,
749 .end = AT91SAM9263_BASE_ISI + SZ_16K - 1,
750 .flags = IORESOURCE_MEM,
751 },
752 [1] = {
753 .start = AT91SAM9263_ID_ISI,
754 .end = AT91SAM9263_ID_ISI,
755 .flags = IORESOURCE_IRQ,
756 },
757};
758
759static struct platform_device at91sam9263_isi_device = {
760 .name = "at91_isi",
761 .id = -1,
762 .resource = isi_resources,
763 .num_resources = ARRAY_SIZE(isi_resources),
764};
765
766void __init at91_add_device_isi(void)
767{
768 at91_set_A_periph(AT91_PIN_PE0, 0); /* ISI_D0 */
769 at91_set_A_periph(AT91_PIN_PE1, 0); /* ISI_D1 */
770 at91_set_A_periph(AT91_PIN_PE2, 0); /* ISI_D2 */
771 at91_set_A_periph(AT91_PIN_PE3, 0); /* ISI_D3 */
772 at91_set_A_periph(AT91_PIN_PE4, 0); /* ISI_D4 */
773 at91_set_A_periph(AT91_PIN_PE5, 0); /* ISI_D5 */
774 at91_set_A_periph(AT91_PIN_PE6, 0); /* ISI_D6 */
775 at91_set_A_periph(AT91_PIN_PE7, 0); /* ISI_D7 */
776 at91_set_A_periph(AT91_PIN_PE8, 0); /* ISI_PCK */
777 at91_set_A_periph(AT91_PIN_PE9, 0); /* ISI_HSYNC */
778 at91_set_A_periph(AT91_PIN_PE10, 0); /* ISI_VSYNC */
779 at91_set_B_periph(AT91_PIN_PE11, 0); /* ISI_MCK (PCK3) */
780 at91_set_B_periph(AT91_PIN_PE12, 0); /* ISI_PD8 */
781 at91_set_B_periph(AT91_PIN_PE13, 0); /* ISI_PD9 */
782 at91_set_B_periph(AT91_PIN_PE14, 0); /* ISI_PD10 */
783 at91_set_B_periph(AT91_PIN_PE15, 0); /* ISI_PD11 */
784}
785#else
786void __init at91_add_device_isi(void) {}
787#endif
788
789
e5f40bfa
AV		 790/* --------------------------------------------------------------------
791 * Timer/Counter block
792 * -------------------------------------------------------------------- */
793
794#ifdef CONFIG_ATMEL_TCLIB
795
796static struct resource tcb_resources[] = {
797 [0] = {
798 .start = AT91SAM9263_BASE_TCB0,
799 .end = AT91SAM9263_BASE_TCB0 + SZ_16K - 1,
800 .flags = IORESOURCE_MEM,
801 },
802 [1] = {
803 .start = AT91SAM9263_ID_TCB,
804 .end = AT91SAM9263_ID_TCB,
805 .flags = IORESOURCE_IRQ,
806 },
807};
808
809static struct platform_device at91sam9263_tcb_device = {
810 .name = "atmel_tcb",
811 .id = 0,
812 .resource = tcb_resources,
813 .num_resources = ARRAY_SIZE(tcb_resources),
814};
815
816static void __init at91_add_device_tc(void)
817{
818 /* this chip has one clock and irq for all three TC channels */
819 at91_clock_associate("tcb_clk", &at91sam9263_tcb_device.dev, "t0_clk");
820 platform_device_register(&at91sam9263_tcb_device);
821}
822#else
823static void __init at91_add_device_tc(void) { }
824#endif
825
826
884f5a6a
AV		 827/* --------------------------------------------------------------------
828 * RTT
829 * -------------------------------------------------------------------- */
830
831static struct resource rtt0_resources[] = {
832 {
833 .start = AT91_BASE_SYS + AT91_RTT0,
834 .end = AT91_BASE_SYS + AT91_RTT0 + SZ_16 - 1,
835 .flags = IORESOURCE_MEM,
836 }
837};
838
839static struct platform_device at91sam9263_rtt0_device = {
840 .name = "at91_rtt",
841 .id = 0,
842 .resource = rtt0_resources,
843 .num_resources = ARRAY_SIZE(rtt0_resources),
844};
845
846static struct resource rtt1_resources[] = {
847 {
848 .start = AT91_BASE_SYS + AT91_RTT1,
849 .end = AT91_BASE_SYS + AT91_RTT1 + SZ_16 - 1,
850 .flags = IORESOURCE_MEM,
851 }
852};
853
854static struct platform_device at91sam9263_rtt1_device = {
855 .name = "at91_rtt",
856 .id = 1,
857 .resource = rtt1_resources,
858 .num_resources = ARRAY_SIZE(rtt1_resources),
859};
860
861static void __init at91_add_device_rtt(void)
862{
863 platform_device_register(&at91sam9263_rtt0_device);
864 platform_device_register(&at91sam9263_rtt1_device);
865}
866
867
868/* --------------------------------------------------------------------
869 * Watchdog
870 * -------------------------------------------------------------------- */
871
872#if defined(CONFIG_AT91SAM9_WATCHDOG) || defined(CONFIG_AT91SAM9_WATCHDOG_MODULE)
873static struct platform_device at91sam9263_wdt_device = {
874 .name = "at91_wdt",
875 .id = -1,
876 .num_resources = 0,
877};
878
879static void __init at91_add_device_watchdog(void)
880{
881 platform_device_register(&at91sam9263_wdt_device);
882}
883#else
884static void __init at91_add_device_watchdog(void) {}
885#endif
886
887
bb1ad68b
AV		 888/* --------------------------------------------------------------------
889 * PWM
890 * --------------------------------------------------------------------*/
891
892#if defined(CONFIG_ATMEL_PWM)
893static u32 pwm_mask;
894
895static struct resource pwm_resources[] = {
896 [0] = {
897 .start = AT91SAM9263_BASE_PWMC,
898 .end = AT91SAM9263_BASE_PWMC + SZ_16K - 1,
899 .flags = IORESOURCE_MEM,
900 },
901 [1] = {
902 .start = AT91SAM9263_ID_PWMC,
903 .end = AT91SAM9263_ID_PWMC,
904 .flags = IORESOURCE_IRQ,
905 },
906};
907
908static struct platform_device at91sam9263_pwm0_device = {
909 .name = "atmel_pwm",
910 .id = -1,
911 .dev = {
912 .platform_data = &pwm_mask,
913 },
914 .resource = pwm_resources,
915 .num_resources = ARRAY_SIZE(pwm_resources),
916};
917
918void __init at91_add_device_pwm(u32 mask)
919{
920 if (mask & (1 << AT91_PWM0))
921 at91_set_B_periph(AT91_PIN_PB7, 1); /* enable PWM0 */
922
923 if (mask & (1 << AT91_PWM1))
924 at91_set_B_periph(AT91_PIN_PB8, 1); /* enable PWM1 */
925
926 if (mask & (1 << AT91_PWM2))
927 at91_set_B_periph(AT91_PIN_PC29, 1); /* enable PWM2 */
928
929 if (mask & (1 << AT91_PWM3))
930 at91_set_B_periph(AT91_PIN_PB29, 1); /* enable PWM3 */
931
932 pwm_mask = mask;
933
934 platform_device_register(&at91sam9263_pwm0_device);
935}
936#else
937void __init at91_add_device_pwm(u32 mask) {}
938#endif
939
940
bfbc3266
AV		 941/* --------------------------------------------------------------------
942 * SSC -- Synchronous Serial Controller
943 * -------------------------------------------------------------------- */
944
945#if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
946static u64 ssc0_dmamask = DMA_BIT_MASK(32);
947
948static struct resource ssc0_resources[] = {
949 [0] = {
950 .start = AT91SAM9263_BASE_SSC0,
951 .end = AT91SAM9263_BASE_SSC0 + SZ_16K - 1,
952 .flags = IORESOURCE_MEM,
953 },
954 [1] = {
955 .start = AT91SAM9263_ID_SSC0,
956 .end = AT91SAM9263_ID_SSC0,
957 .flags = IORESOURCE_IRQ,
958 },
959};
960
961static struct platform_device at91sam9263_ssc0_device = {
962 .name = "ssc",
963 .id = 0,
964 .dev = {
965 .dma_mask = &ssc0_dmamask,
966 .coherent_dma_mask = DMA_BIT_MASK(32),
967 },
968 .resource = ssc0_resources,
969 .num_resources = ARRAY_SIZE(ssc0_resources),
970};
971
972static inline void configure_ssc0_pins(unsigned pins)
973{
974 if (pins & ATMEL_SSC_TF)
975 at91_set_B_periph(AT91_PIN_PB0, 1);
976 if (pins & ATMEL_SSC_TK)
977 at91_set_B_periph(AT91_PIN_PB1, 1);
978 if (pins & ATMEL_SSC_TD)
979 at91_set_B_periph(AT91_PIN_PB2, 1);
980 if (pins & ATMEL_SSC_RD)
981 at91_set_B_periph(AT91_PIN_PB3, 1);
982 if (pins & ATMEL_SSC_RK)
983 at91_set_B_periph(AT91_PIN_PB4, 1);
984 if (pins & ATMEL_SSC_RF)
985 at91_set_B_periph(AT91_PIN_PB5, 1);
986}
987
988static u64 ssc1_dmamask = DMA_BIT_MASK(32);
989
990static struct resource ssc1_resources[] = {
991 [0] = {
992 .start = AT91SAM9263_BASE_SSC1,
993 .end = AT91SAM9263_BASE_SSC1 + SZ_16K - 1,
994 .flags = IORESOURCE_MEM,
995 },
996 [1] = {
997 .start = AT91SAM9263_ID_SSC1,
998 .end = AT91SAM9263_ID_SSC1,
999 .flags = IORESOURCE_IRQ,
1000 },
1001};
1002
1003static struct platform_device at91sam9263_ssc1_device = {
1004 .name = "ssc",
1005 .id = 1,
1006 .dev = {
1007 .dma_mask = &ssc1_dmamask,
1008 .coherent_dma_mask = DMA_BIT_MASK(32),
1009 },
1010 .resource = ssc1_resources,
1011 .num_resources = ARRAY_SIZE(ssc1_resources),
1012};
1013
1014static inline void configure_ssc1_pins(unsigned pins)
1015{
1016 if (pins & ATMEL_SSC_TF)
1017 at91_set_A_periph(AT91_PIN_PB6, 1);
1018 if (pins & ATMEL_SSC_TK)
1019 at91_set_A_periph(AT91_PIN_PB7, 1);
1020 if (pins & ATMEL_SSC_TD)
1021 at91_set_A_periph(AT91_PIN_PB8, 1);
1022 if (pins & ATMEL_SSC_RD)
1023 at91_set_A_periph(AT91_PIN_PB9, 1);
1024 if (pins & ATMEL_SSC_RK)
1025 at91_set_A_periph(AT91_PIN_PB10, 1);
1026 if (pins & ATMEL_SSC_RF)
1027 at91_set_A_periph(AT91_PIN_PB11, 1);
1028}
1029
1030/*
bfbc3266
AV		 1031 * SSC controllers are accessed through library code, instead of any
1032 * kind of all-singing/all-dancing driver. For example one could be
1033 * used by a particular I2S audio codec's driver, while another one
1034 * on the same system might be used by a custom data capture driver.
1035 */
1036void __init at91_add_device_ssc(unsigned id, unsigned pins)
1037{
1038 struct platform_device *pdev;
1039
1040 /*
1041 * NOTE: caller is responsible for passing information matching
1042 * "pins" to whatever will be using each particular controller.
1043 */
1044 switch (id) {
1045 case AT91SAM9263_ID_SSC0:
1046 pdev = &at91sam9263_ssc0_device;
1047 configure_ssc0_pins(pins);
1048 at91_clock_associate("ssc0_clk", &pdev->dev, "pclk");
1049 break;
1050 case AT91SAM9263_ID_SSC1:
1051 pdev = &at91sam9263_ssc1_device;
1052 configure_ssc1_pins(pins);
1053 at91_clock_associate("ssc1_clk", &pdev->dev, "pclk");
1054 break;
1055 default:
1056 return;
1057 }
1058
1059 platform_device_register(pdev);
1060}
1061
1062#else
1063void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
1064#endif
1065
1066
b2c65616
AV		 1067/* --------------------------------------------------------------------
1068 * UART
1069 * -------------------------------------------------------------------- */
1070
1071#if defined(CONFIG_SERIAL_ATMEL)
1072
1073static struct resource dbgu_resources[] = {
1074 [0] = {
1075 .start = AT91_VA_BASE_SYS + AT91_DBGU,
1076 .end = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
1077 .flags = IORESOURCE_MEM,
1078 },
1079 [1] = {
1080 .start = AT91_ID_SYS,
1081 .end = AT91_ID_SYS,
1082 .flags = IORESOURCE_IRQ,
1083 },
1084};
1085
1086static struct atmel_uart_data dbgu_data = {
1087 .use_dma_tx = 0,
1088 .use_dma_rx = 0, /* DBGU not capable of receive DMA */
1089 .regs = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
1090};
1091
c6686ff9
AV		 1092static u64 dbgu_dmamask = DMA_BIT_MASK(32);
1093
b2c65616
AV		 1094static struct platform_device at91sam9263_dbgu_device = {
1095 .name = "atmel_usart",
1096 .id = 0,
1097 .dev = {
c6686ff9
AV		 1098 .dma_mask = &dbgu_dmamask,
1099 .coherent_dma_mask = DMA_BIT_MASK(32),
1100 .platform_data = &dbgu_data,
b2c65616
AV		 1101 },
1102 .resource = dbgu_resources,
1103 .num_resources = ARRAY_SIZE(dbgu_resources),
1104};
1105
1106static inline void configure_dbgu_pins(void)
1107{
1108 at91_set_A_periph(AT91_PIN_PC30, 0); /* DRXD */
1109 at91_set_A_periph(AT91_PIN_PC31, 1); /* DTXD */
1110}
1111
1112static struct resource uart0_resources[] = {
1113 [0] = {
1114 .start = AT91SAM9263_BASE_US0,
1115 .end = AT91SAM9263_BASE_US0 + SZ_16K - 1,
1116 .flags = IORESOURCE_MEM,
1117 },
1118 [1] = {
1119 .start = AT91SAM9263_ID_US0,
1120 .end = AT91SAM9263_ID_US0,
1121 .flags = IORESOURCE_IRQ,
1122 },
1123};
1124
1125static struct atmel_uart_data uart0_data = {
1126 .use_dma_tx = 1,
1127 .use_dma_rx = 1,
1128};
1129
c6686ff9
AV		 1130static u64 uart0_dmamask = DMA_BIT_MASK(32);
1131
b2c65616
AV		 1132static struct platform_device at91sam9263_uart0_device = {
1133 .name = "atmel_usart",
1134 .id = 1,
1135 .dev = {
c6686ff9
AV		 1136 .dma_mask = &uart0_dmamask,
1137 .coherent_dma_mask = DMA_BIT_MASK(32),
1138 .platform_data = &uart0_data,
b2c65616
AV		 1139 },
1140 .resource = uart0_resources,
1141 .num_resources = ARRAY_SIZE(uart0_resources),
1142};
1143
c8f385a6 1144static inline void configure_usart0_pins(unsigned pins)
b2c65616
AV		 1145{
1146 at91_set_A_periph(AT91_PIN_PA26, 1); /* TXD0 */
1147 at91_set_A_periph(AT91_PIN_PA27, 0); /* RXD0 */
c8f385a6
AV		 1148
1149 if (pins & ATMEL_UART_RTS)
1150 at91_set_A_periph(AT91_PIN_PA28, 0); /* RTS0 */
1151 if (pins & ATMEL_UART_CTS)
1152 at91_set_A_periph(AT91_PIN_PA29, 0); /* CTS0 */
b2c65616
AV		 1153}
1154
1155static struct resource uart1_resources[] = {
1156 [0] = {
1157 .start = AT91SAM9263_BASE_US1,
1158 .end = AT91SAM9263_BASE_US1 + SZ_16K - 1,
1159 .flags = IORESOURCE_MEM,
1160 },
1161 [1] = {
1162 .start = AT91SAM9263_ID_US1,
1163 .end = AT91SAM9263_ID_US1,
1164 .flags = IORESOURCE_IRQ,
1165 },
1166};
1167
1168static struct atmel_uart_data uart1_data = {
1169 .use_dma_tx = 1,
1170 .use_dma_rx = 1,
1171};
1172
c6686ff9
AV		 1173static u64 uart1_dmamask = DMA_BIT_MASK(32);
1174
b2c65616
AV		 1175static struct platform_device at91sam9263_uart1_device = {
1176 .name = "atmel_usart",
1177 .id = 2,
1178 .dev = {
c6686ff9
AV		 1179 .dma_mask = &uart1_dmamask,
1180 .coherent_dma_mask = DMA_BIT_MASK(32),
1181 .platform_data = &uart1_data,
b2c65616
AV		 1182 },
1183 .resource = uart1_resources,
1184 .num_resources = ARRAY_SIZE(uart1_resources),
1185};
1186
c8f385a6 1187static inline void configure_usart1_pins(unsigned pins)
b2c65616
AV		 1188{
1189 at91_set_A_periph(AT91_PIN_PD0, 1); /* TXD1 */
1190 at91_set_A_periph(AT91_PIN_PD1, 0); /* RXD1 */
c8f385a6
AV		 1191
1192 if (pins & ATMEL_UART_RTS)
1193 at91_set_B_periph(AT91_PIN_PD7, 0); /* RTS1 */
1194 if (pins & ATMEL_UART_CTS)
1195 at91_set_B_periph(AT91_PIN_PD8, 0); /* CTS1 */
b2c65616
AV		 1196}
1197
1198static struct resource uart2_resources[] = {
1199 [0] = {
1200 .start = AT91SAM9263_BASE_US2,
1201 .end = AT91SAM9263_BASE_US2 + SZ_16K - 1,
1202 .flags = IORESOURCE_MEM,
1203 },
1204 [1] = {
1205 .start = AT91SAM9263_ID_US2,
1206 .end = AT91SAM9263_ID_US2,
1207 .flags = IORESOURCE_IRQ,
1208 },
1209};
1210
1211static struct atmel_uart_data uart2_data = {
1212 .use_dma_tx = 1,
1213 .use_dma_rx = 1,
1214};
1215
c6686ff9
AV		 1216static u64 uart2_dmamask = DMA_BIT_MASK(32);
1217
b2c65616
AV		 1218static struct platform_device at91sam9263_uart2_device = {
1219 .name = "atmel_usart",
1220 .id = 3,
1221 .dev = {
c6686ff9
AV		 1222 .dma_mask = &uart2_dmamask,
1223 .coherent_dma_mask = DMA_BIT_MASK(32),
1224 .platform_data = &uart2_data,
b2c65616
AV		 1225 },
1226 .resource = uart2_resources,
1227 .num_resources = ARRAY_SIZE(uart2_resources),
1228};
1229
c8f385a6 1230static inline void configure_usart2_pins(unsigned pins)
b2c65616
AV		 1231{
1232 at91_set_A_periph(AT91_PIN_PD2, 1); /* TXD2 */
1233 at91_set_A_periph(AT91_PIN_PD3, 0); /* RXD2 */
c8f385a6
AV		 1234
1235 if (pins & ATMEL_UART_RTS)
1236 at91_set_B_periph(AT91_PIN_PD5, 0); /* RTS2 */
1237 if (pins & ATMEL_UART_CTS)
1238 at91_set_B_periph(AT91_PIN_PD6, 0); /* CTS2 */
b2c65616
AV		 1239}
1240
11aadac4 1241static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
b2c65616
AV		 1242struct platform_device *atmel_default_console_device; /* the serial console device */
1243
c8f385a6
AV		 1244void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1245{
1246 struct platform_device *pdev;
1247
1248 switch (id) {
1249 case 0: /* DBGU */
1250 pdev = &at91sam9263_dbgu_device;
1251 configure_dbgu_pins();
1252 at91_clock_associate("mck", &pdev->dev, "usart");
1253 break;
1254 case AT91SAM9263_ID_US0:
1255 pdev = &at91sam9263_uart0_device;
1256 configure_usart0_pins(pins);
1257 at91_clock_associate("usart0_clk", &pdev->dev, "usart");
1258 break;
1259 case AT91SAM9263_ID_US1:
1260 pdev = &at91sam9263_uart1_device;
1261 configure_usart1_pins(pins);
1262 at91_clock_associate("usart1_clk", &pdev->dev, "usart");
1263 break;
1264 case AT91SAM9263_ID_US2:
1265 pdev = &at91sam9263_uart2_device;
1266 configure_usart2_pins(pins);
1267 at91_clock_associate("usart2_clk", &pdev->dev, "usart");
1268 break;
1269 default:
1270 return;
1271 }
1272 pdev->id = portnr; /* update to mapped ID */
1273
1274 if (portnr < ATMEL_MAX_UART)
1275 at91_uarts[portnr] = pdev;
1276}
1277
1278void __init at91_set_serial_console(unsigned portnr)
1279{
1280 if (portnr < ATMEL_MAX_UART)
1281 atmel_default_console_device = at91_uarts[portnr];
c8f385a6
AV		 1282}
1283
b2c65616
AV		 1284void __init at91_add_device_serial(void)
1285{
1286 int i;
1287
1288 for (i = 0; i < ATMEL_MAX_UART; i++) {
1289 if (at91_uarts[i])
1290 platform_device_register(at91_uarts[i]);
1291 }
11aadac4
AV		 1292
1293 if (!atmel_default_console_device)
1294 printk(KERN_INFO "AT91: No default serial console defined.\n");
b2c65616
AV		 1295}
1296#else
c8f385a6
AV		 1297void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1298void __init at91_set_serial_console(unsigned portnr) {}
b2c65616
AV		 1299void __init at91_add_device_serial(void) {}
1300#endif
1301
1302
1303/* -------------------------------------------------------------------- */
1304/*
1305 * These devices are always present and don't need any board-specific
1306 * setup.
1307 */
1308static int __init at91_add_standard_devices(void)
1309{
884f5a6a
AV		 1310 at91_add_device_rtt();
1311 at91_add_device_watchdog();
e5f40bfa 1312 at91_add_device_tc();
b2c65616
AV		 1313 return 0;
1314}
1315
1316arch_initcall(at91_add_standard_devices);
Linux kernel - Deliverables
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