[deliverable/linux.git] / arch / arm / mach-at91 / at91sam9g45.c

/*
 *  Chip-specific setup code for the AT91SAM9G45 family
 *
 *  Copyright (C) 2009 Atmel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 */

#include <linux/module.h>
#include <linux/dma-mapping.h>

#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/system_misc.h>
#include <mach/at91sam9g45.h>
#include <mach/at91_pmc.h>
#include <mach/cpu.h>

#include "at91_aic.h"
#include "soc.h"
#include "generic.h"
#include "clock.h"
#include "sam9_smc.h"

/* --------------------------------------------------------------------
 *  Clocks
 * -------------------------------------------------------------------- */

/*
 * The peripheral clocks.
 */
static struct clk pioA_clk = {
	.name		= "pioA_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_PIOA,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk pioB_clk = {
	.name		= "pioB_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_PIOB,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk pioC_clk = {
	.name		= "pioC_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_PIOC,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk pioDE_clk = {
	.name		= "pioDE_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_PIODE,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk trng_clk = {
	.name		= "trng_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_TRNG,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart0_clk = {
	.name		= "usart0_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_US0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart1_clk = {
	.name		= "usart1_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_US1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart2_clk = {
	.name		= "usart2_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_US2,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart3_clk = {
	.name		= "usart3_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_US3,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk mmc0_clk = {
	.name		= "mci0_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_MCI0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk twi0_clk = {
	.name		= "twi0_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_TWI0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk twi1_clk = {
	.name		= "twi1_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_TWI1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk spi0_clk = {
	.name		= "spi0_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_SPI0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk spi1_clk = {
	.name		= "spi1_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_SPI1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk ssc0_clk = {
	.name		= "ssc0_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_SSC0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk ssc1_clk = {
	.name		= "ssc1_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_SSC1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk tcb0_clk = {
	.name		= "tcb0_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_TCB,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk pwm_clk = {
	.name		= "pwm_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_PWMC,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk tsc_clk = {
	.name		= "tsc_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_TSC,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk dma_clk = {
	.name		= "dma_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_DMA,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk uhphs_clk = {
	.name		= "uhphs_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_UHPHS,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk lcdc_clk = {
	.name		= "lcdc_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_LCDC,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk ac97_clk = {
	.name		= "ac97_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_AC97C,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk macb_clk = {
	.name		= "pclk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_EMAC,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk isi_clk = {
	.name		= "isi_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_ISI,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk udphs_clk = {
	.name		= "udphs_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_UDPHS,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk mmc1_clk = {
	.name		= "mci1_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_MCI1,
	.type		= CLK_TYPE_PERIPHERAL,
};

/* Video decoder clock - Only for sam9m10/sam9m11 */
static struct clk vdec_clk = {
	.name		= "vdec_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_VDEC,
	.type		= CLK_TYPE_PERIPHERAL,
};

static struct clk adc_op_clk = {
	.name		= "adc_op_clk",
	.type		= CLK_TYPE_PERIPHERAL,
	.rate_hz	= 13200000,
};

/* AES/TDES/SHA clock - Only for sam9m11/sam9g56 */
static struct clk aestdessha_clk = {
	.name		= "aestdessha_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_AESTDESSHA,
	.type		= CLK_TYPE_PERIPHERAL,
};

static struct clk *periph_clocks[] __initdata = {
	&pioA_clk,
	&pioB_clk,
	&pioC_clk,
	&pioDE_clk,
	&trng_clk,
	&usart0_clk,
	&usart1_clk,
	&usart2_clk,
	&usart3_clk,
	&mmc0_clk,
	&twi0_clk,
	&twi1_clk,
	&spi0_clk,
	&spi1_clk,
	&ssc0_clk,
	&ssc1_clk,
	&tcb0_clk,
	&pwm_clk,
	&tsc_clk,
	&dma_clk,
	&uhphs_clk,
	&lcdc_clk,
	&ac97_clk,
	&macb_clk,
	&isi_clk,
	&udphs_clk,
	&mmc1_clk,
	&adc_op_clk,
	&aestdessha_clk,
	// irq0
};

static struct clk_lookup periph_clocks_lookups[] = {
	/* One additional fake clock for macb_hclk */
	CLKDEV_CON_ID("hclk", &macb_clk),
	/* One additional fake clock for ohci */
	CLKDEV_CON_ID("ohci_clk", &uhphs_clk),
	CLKDEV_CON_DEV_ID("hclk", "at91sam9g45-lcdfb.0", &lcdc_clk),
	CLKDEV_CON_DEV_ID("hclk", "at91sam9g45es-lcdfb.0", &lcdc_clk),
	CLKDEV_CON_DEV_ID("ehci_clk", "atmel-ehci", &uhphs_clk),
	CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
	CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
	CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.0", &mmc0_clk),
	CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.1", &mmc1_clk),
	CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
	CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
	CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb0_clk),
	CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tcb0_clk),
	CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.0", &twi0_clk),
	CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.1", &twi1_clk),
	CLKDEV_CON_DEV_ID("pclk", "at91sam9g45_ssc.0", &ssc0_clk),
	CLKDEV_CON_DEV_ID("pclk", "at91sam9g45_ssc.1", &ssc1_clk),
	CLKDEV_CON_DEV_ID("pclk", "fff9c000.ssc", &ssc0_clk),
	CLKDEV_CON_DEV_ID("pclk", "fffa0000.ssc", &ssc1_clk),
	CLKDEV_CON_DEV_ID(NULL, "atmel-trng", &trng_clk),
	CLKDEV_CON_DEV_ID(NULL, "atmel_sha", &aestdessha_clk),
	CLKDEV_CON_DEV_ID(NULL, "atmel_tdes", &aestdessha_clk),
	CLKDEV_CON_DEV_ID(NULL, "atmel_aes", &aestdessha_clk),
	/* more usart lookup table for DT entries */
	CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck),
	CLKDEV_CON_DEV_ID("usart", "fff8c000.serial", &usart0_clk),
	CLKDEV_CON_DEV_ID("usart", "fff90000.serial", &usart1_clk),
	CLKDEV_CON_DEV_ID("usart", "fff94000.serial", &usart2_clk),
	CLKDEV_CON_DEV_ID("usart", "fff98000.serial", &usart3_clk),
	/* more tc lookup table for DT entries */
	CLKDEV_CON_DEV_ID("t0_clk", "fff7c000.timer", &tcb0_clk),
	CLKDEV_CON_DEV_ID("t0_clk", "fffd4000.timer", &tcb0_clk),
	CLKDEV_CON_DEV_ID("hclk", "700000.ohci", &uhphs_clk),
	CLKDEV_CON_DEV_ID("ehci_clk", "800000.ehci", &uhphs_clk),
	CLKDEV_CON_DEV_ID("mci_clk", "fff80000.mmc", &mmc0_clk),
	CLKDEV_CON_DEV_ID("mci_clk", "fffd0000.mmc", &mmc1_clk),
	CLKDEV_CON_DEV_ID(NULL, "fff84000.i2c", &twi0_clk),
	CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi1_clk),
	CLKDEV_CON_DEV_ID("spi_clk", "fffa4000.spi", &spi0_clk),
	CLKDEV_CON_DEV_ID("spi_clk", "fffa8000.spi", &spi1_clk),
	/* fake hclk clock */
	CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk),
	CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk),
	CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioB_clk),
	CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioC_clk),
	CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioDE_clk),
	CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioDE_clk),

	CLKDEV_CON_ID("pioA", &pioA_clk),
	CLKDEV_CON_ID("pioB", &pioB_clk),
	CLKDEV_CON_ID("pioC", &pioC_clk),
	CLKDEV_CON_ID("pioD", &pioDE_clk),
	CLKDEV_CON_ID("pioE", &pioDE_clk),
	/* Fake adc clock */
	CLKDEV_CON_ID("adc_clk", &tsc_clk),
};

static struct clk_lookup usart_clocks_lookups[] = {
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
};

/*
 * The two programmable clocks.
 * You must configure pin multiplexing to bring these signals out.
 */
static struct clk pck0 = {
	.name		= "pck0",
	.pmc_mask	= AT91_PMC_PCK0,
	.type		= CLK_TYPE_PROGRAMMABLE,
	.id		= 0,
};
static struct clk pck1 = {
	.name		= "pck1",
	.pmc_mask	= AT91_PMC_PCK1,
	.type		= CLK_TYPE_PROGRAMMABLE,
	.id		= 1,
};

static void __init at91sam9g45_register_clocks(void)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
		clk_register(periph_clocks[i]);

	clkdev_add_table(periph_clocks_lookups,
			 ARRAY_SIZE(periph_clocks_lookups));
	clkdev_add_table(usart_clocks_lookups,
			 ARRAY_SIZE(usart_clocks_lookups));

	if (cpu_is_at91sam9m10() || cpu_is_at91sam9m11())
		clk_register(&vdec_clk);

	clk_register(&pck0);
	clk_register(&pck1);
}

/* --------------------------------------------------------------------
 *  GPIO
 * -------------------------------------------------------------------- */

static struct at91_gpio_bank at91sam9g45_gpio[] __initdata = {
	{
		.id		= AT91SAM9G45_ID_PIOA,
		.regbase	= AT91SAM9G45_BASE_PIOA,
	}, {
		.id		= AT91SAM9G45_ID_PIOB,
		.regbase	= AT91SAM9G45_BASE_PIOB,
	}, {
		.id		= AT91SAM9G45_ID_PIOC,
		.regbase	= AT91SAM9G45_BASE_PIOC,
	}, {
		.id		= AT91SAM9G45_ID_PIODE,
		.regbase	= AT91SAM9G45_BASE_PIOD,
	}, {
		.id		= AT91SAM9G45_ID_PIODE,
		.regbase	= AT91SAM9G45_BASE_PIOE,
	}
};

/* --------------------------------------------------------------------
 *  AT91SAM9G45 processor initialization
 * -------------------------------------------------------------------- */

static void __init at91sam9g45_map_io(void)
{
	at91_init_sram(0, AT91SAM9G45_SRAM_BASE, AT91SAM9G45_SRAM_SIZE);
}

static void __init at91sam9g45_ioremap_registers(void)
{
	at91_ioremap_shdwc(AT91SAM9G45_BASE_SHDWC);
	at91_ioremap_rstc(AT91SAM9G45_BASE_RSTC);
	at91_ioremap_ramc(0, AT91SAM9G45_BASE_DDRSDRC1, 512);
	at91_ioremap_ramc(1, AT91SAM9G45_BASE_DDRSDRC0, 512);
	at91sam926x_ioremap_pit(AT91SAM9G45_BASE_PIT);
	at91sam9_ioremap_smc(0, AT91SAM9G45_BASE_SMC);
	at91_ioremap_matrix(AT91SAM9G45_BASE_MATRIX);
}

static void __init at91sam9g45_initialize(void)
{
	arm_pm_idle = at91sam9_idle;
	arm_pm_restart = at91sam9g45_restart;
	at91_extern_irq = (1 << AT91SAM9G45_ID_IRQ0);

	/* Register GPIO subsystem */
	at91_gpio_init(at91sam9g45_gpio, 5);
}

/* --------------------------------------------------------------------
 *  Interrupt initialization
 * -------------------------------------------------------------------- */

/*
 * The default interrupt priority levels (0 = lowest, 7 = highest).
 */
static unsigned int at91sam9g45_default_irq_priority[NR_AIC_IRQS] __initdata = {
	7,	/* Advanced Interrupt Controller (FIQ) */
	7,	/* System Peripherals */
	1,	/* Parallel IO Controller A */
	1,	/* Parallel IO Controller B */
	1,	/* Parallel IO Controller C */
	1,	/* Parallel IO Controller D and E */
	0,
	5,	/* USART 0 */
	5,	/* USART 1 */
	5,	/* USART 2 */
	5,	/* USART 3 */
	0,	/* Multimedia Card Interface 0 */
	6,	/* Two-Wire Interface 0 */
	6,	/* Two-Wire Interface 1 */
	5,	/* Serial Peripheral Interface 0 */
	5,	/* Serial Peripheral Interface 1 */
	4,	/* Serial Synchronous Controller 0 */
	4,	/* Serial Synchronous Controller 1 */
	0,	/* Timer Counter 0, 1, 2, 3, 4 and 5 */
	0,	/* Pulse Width Modulation Controller */
	0,	/* Touch Screen Controller */
	0,	/* DMA Controller */
	2,	/* USB Host High Speed port */
	3,	/* LDC Controller */
	5,	/* AC97 Controller */
	3,	/* Ethernet */
	0,	/* Image Sensor Interface */
	2,	/* USB Device High speed port */
	0,	/* AESTDESSHA Crypto HW Accelerators */
	0,	/* Multimedia Card Interface 1 */
	0,
	0,	/* Advanced Interrupt Controller (IRQ0) */
};

AT91_SOC_START(at91sam9g45)
	.map_io = at91sam9g45_map_io,
	.default_irq_priority = at91sam9g45_default_irq_priority,
	.ioremap_registers = at91sam9g45_ioremap_registers,
	.register_clocks = at91sam9g45_register_clocks,
	.init = at91sam9g45_initialize,
AT91_SOC_END
Commit	Line	Data
789b23bc NF	1	/*
	2	* Chip-specific setup code for the AT91SAM9G45 family
	3	*
	4	* Copyright (C) 2009 Atmel Corporation.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	*/
	12
	13	#include <linux/module.h>
f407c2e3	14	#include <linux/dma-mapping.h>
789b23bc NF	15
	16	#include <asm/irq.h>
	17	#include <asm/mach/arch.h>
	18	#include <asm/mach/map.h>
9f97da78	19	#include <asm/system_misc.h>
789b23bc NF	20	#include <mach/at91sam9g45.h>
789b23bc NF	21	#include <mach/at91_pmc.h>
5f9f0a41	22	#include <mach/cpu.h>
789b23bc	23
a510b9ba	24	#include "at91_aic.h"
21d08b9d	25	#include "soc.h"
789b23bc NF	26	#include "generic.h"
789b23bc NF	27	#include "clock.h"
faee0cc3	28	#include "sam9_smc.h"
789b23bc	29
789b23bc NF	30	/* --------------------------------------------------------------------
	31	* Clocks
	32	* -------------------------------------------------------------------- */
	33
	34	/*
	35	* The peripheral clocks.
	36	*/
	37	static struct clk pioA_clk = {
	38	.name = "pioA_clk",
	39	.pmc_mask = 1 << AT91SAM9G45_ID_PIOA,
	40	.type = CLK_TYPE_PERIPHERAL,
	41	};
	42	static struct clk pioB_clk = {
	43	.name = "pioB_clk",
	44	.pmc_mask = 1 << AT91SAM9G45_ID_PIOB,
	45	.type = CLK_TYPE_PERIPHERAL,
	46	};
	47	static struct clk pioC_clk = {
	48	.name = "pioC_clk",
	49	.pmc_mask = 1 << AT91SAM9G45_ID_PIOC,
	50	.type = CLK_TYPE_PERIPHERAL,
	51	};
	52	static struct clk pioDE_clk = {
	53	.name = "pioDE_clk",
	54	.pmc_mask = 1 << AT91SAM9G45_ID_PIODE,
	55	.type = CLK_TYPE_PERIPHERAL,
	56	};
237a62a1 PK	57	static struct clk trng_clk = {
	58	.name = "trng_clk",
	59	.pmc_mask = 1 << AT91SAM9G45_ID_TRNG,
	60	.type = CLK_TYPE_PERIPHERAL,
	61	};
789b23bc NF	62	static struct clk usart0_clk = {
	63	.name = "usart0_clk",
	64	.pmc_mask = 1 << AT91SAM9G45_ID_US0,
	65	.type = CLK_TYPE_PERIPHERAL,
	66	};
	67	static struct clk usart1_clk = {
	68	.name = "usart1_clk",
	69	.pmc_mask = 1 << AT91SAM9G45_ID_US1,
	70	.type = CLK_TYPE_PERIPHERAL,
	71	};
	72	static struct clk usart2_clk = {
	73	.name = "usart2_clk",
	74	.pmc_mask = 1 << AT91SAM9G45_ID_US2,
	75	.type = CLK_TYPE_PERIPHERAL,
	76	};
	77	static struct clk usart3_clk = {
	78	.name = "usart3_clk",
	79	.pmc_mask = 1 << AT91SAM9G45_ID_US3,
	80	.type = CLK_TYPE_PERIPHERAL,
	81	};
	82	static struct clk mmc0_clk = {
	83	.name = "mci0_clk",
	84	.pmc_mask = 1 << AT91SAM9G45_ID_MCI0,
	85	.type = CLK_TYPE_PERIPHERAL,
	86	};
	87	static struct clk twi0_clk = {
	88	.name = "twi0_clk",
	89	.pmc_mask = 1 << AT91SAM9G45_ID_TWI0,
	90	.type = CLK_TYPE_PERIPHERAL,
	91	};
	92	static struct clk twi1_clk = {
	93	.name = "twi1_clk",
	94	.pmc_mask = 1 << AT91SAM9G45_ID_TWI1,
	95	.type = CLK_TYPE_PERIPHERAL,
	96	};
	97	static struct clk spi0_clk = {
	98	.name = "spi0_clk",
	99	.pmc_mask = 1 << AT91SAM9G45_ID_SPI0,
	100	.type = CLK_TYPE_PERIPHERAL,
	101	};
	102	static struct clk spi1_clk = {
	103	.name = "spi1_clk",
	104	.pmc_mask = 1 << AT91SAM9G45_ID_SPI1,
	105	.type = CLK_TYPE_PERIPHERAL,
	106	};
	107	static struct clk ssc0_clk = {
	108	.name = "ssc0_clk",
	109	.pmc_mask = 1 << AT91SAM9G45_ID_SSC0,
	110	.type = CLK_TYPE_PERIPHERAL,
	111	};
	112	static struct clk ssc1_clk = {
	113	.name = "ssc1_clk",
	114	.pmc_mask = 1 << AT91SAM9G45_ID_SSC1,
	115	.type = CLK_TYPE_PERIPHERAL,
	116	};
ab64511c FG	117	static struct clk tcb0_clk = {
ab64511c FG	118	.name = "tcb0_clk",
789b23bc NF	119	.pmc_mask = 1 << AT91SAM9G45_ID_TCB,
	120	.type = CLK_TYPE_PERIPHERAL,
	121	};
	122	static struct clk pwm_clk = {
	123	.name = "pwm_clk",
	124	.pmc_mask = 1 << AT91SAM9G45_ID_PWMC,
	125	.type = CLK_TYPE_PERIPHERAL,
	126	};
	127	static struct clk tsc_clk = {
	128	.name = "tsc_clk",
	129	.pmc_mask = 1 << AT91SAM9G45_ID_TSC,
	130	.type = CLK_TYPE_PERIPHERAL,
	131	};
	132	static struct clk dma_clk = {
	133	.name = "dma_clk",
	134	.pmc_mask = 1 << AT91SAM9G45_ID_DMA,
	135	.type = CLK_TYPE_PERIPHERAL,
	136	};
	137	static struct clk uhphs_clk = {
	138	.name = "uhphs_clk",
	139	.pmc_mask = 1 << AT91SAM9G45_ID_UHPHS,
	140	.type = CLK_TYPE_PERIPHERAL,
	141	};
	142	static struct clk lcdc_clk = {
	143	.name = "lcdc_clk",
	144	.pmc_mask = 1 << AT91SAM9G45_ID_LCDC,
	145	.type = CLK_TYPE_PERIPHERAL,
	146	};
	147	static struct clk ac97_clk = {
	148	.name = "ac97_clk",
	149	.pmc_mask = 1 << AT91SAM9G45_ID_AC97C,
	150	.type = CLK_TYPE_PERIPHERAL,
	151	};
	152	static struct clk macb_clk = {
865d605e	153	.name = "pclk",
789b23bc NF	154	.pmc_mask = 1 << AT91SAM9G45_ID_EMAC,
	155	.type = CLK_TYPE_PERIPHERAL,
	156	};
	157	static struct clk isi_clk = {
	158	.name = "isi_clk",
	159	.pmc_mask = 1 << AT91SAM9G45_ID_ISI,
	160	.type = CLK_TYPE_PERIPHERAL,
	161	};
	162	static struct clk udphs_clk = {
	163	.name = "udphs_clk",
	164	.pmc_mask = 1 << AT91SAM9G45_ID_UDPHS,
	165	.type = CLK_TYPE_PERIPHERAL,
	166	};
	167	static struct clk mmc1_clk = {
	168	.name = "mci1_clk",
	169	.pmc_mask = 1 << AT91SAM9G45_ID_MCI1,
	170	.type = CLK_TYPE_PERIPHERAL,
	171	};
	172
5f9f0a41 NF	173	/* Video decoder clock - Only for sam9m10/sam9m11 */
	174	static struct clk vdec_clk = {
	175	.name = "vdec_clk",
	176	.pmc_mask = 1 << AT91SAM9G45_ID_VDEC,
	177	.type = CLK_TYPE_PERIPHERAL,
	178	};
	179
4a5920e8 MR	180	static struct clk adc_op_clk = {
	181	.name = "adc_op_clk",
	182	.type = CLK_TYPE_PERIPHERAL,
	183	.rate_hz = 13200000,
	184	};
	185
815e9721 NR	186	/* AES/TDES/SHA clock - Only for sam9m11/sam9g56 */
	187	static struct clk aestdessha_clk = {
	188	.name = "aestdessha_clk",
	189	.pmc_mask = 1 << AT91SAM9G45_ID_AESTDESSHA,
	190	.type = CLK_TYPE_PERIPHERAL,
	191	};
	192
789b23bc NF	193	static struct clk *periph_clocks[] __initdata = {
	194	&pioA_clk,
	195	&pioB_clk,
	196	&pioC_clk,
	197	&pioDE_clk,
237a62a1	198	&trng_clk,
789b23bc NF	199	&usart0_clk,
	200	&usart1_clk,
	201	&usart2_clk,
	202	&usart3_clk,
	203	&mmc0_clk,
	204	&twi0_clk,
	205	&twi1_clk,
	206	&spi0_clk,
	207	&spi1_clk,
	208	&ssc0_clk,
	209	&ssc1_clk,
ab64511c	210	&tcb0_clk,
789b23bc NF	211	&pwm_clk,
	212	&tsc_clk,
	213	&dma_clk,
	214	&uhphs_clk,
	215	&lcdc_clk,
	216	&ac97_clk,
	217	&macb_clk,
	218	&isi_clk,
	219	&udphs_clk,
	220	&mmc1_clk,
4a5920e8	221	&adc_op_clk,
815e9721	222	&aestdessha_clk,
789b23bc	223	// irq0
bd602995 JCPV	224	};
	225
	226	static struct clk_lookup periph_clocks_lookups[] = {
865d605e JI	227	/* One additional fake clock for macb_hclk */
865d605e JI	228	CLKDEV_CON_ID("hclk", &macb_clk),
bd602995 JCPV	229	/* One additional fake clock for ohci */
bd602995 JCPV	230	CLKDEV_CON_ID("ohci_clk", &uhphs_clk),
bbd44f6b JH	231	CLKDEV_CON_DEV_ID("hclk", "at91sam9g45-lcdfb.0", &lcdc_clk),
bbd44f6b JH	232	CLKDEV_CON_DEV_ID("hclk", "at91sam9g45es-lcdfb.0", &lcdc_clk),
9d87159e JCPV	233	CLKDEV_CON_DEV_ID("ehci_clk", "atmel-ehci", &uhphs_clk),
	234	CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
	235	CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
	236	CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.0", &mmc0_clk),
	237	CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.1", &mmc1_clk),
bd602995 JCPV	238	CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
	239	CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
	240	CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb0_clk),
	241	CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tcb0_clk),
fac368a0 NV	242	CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.0", &twi0_clk),
fac368a0 NV	243	CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.1", &twi1_clk),
636036d2 BS	244	CLKDEV_CON_DEV_ID("pclk", "at91sam9g45_ssc.0", &ssc0_clk),
636036d2 BS	245	CLKDEV_CON_DEV_ID("pclk", "at91sam9g45_ssc.1", &ssc1_clk),
099343c6 BS	246	CLKDEV_CON_DEV_ID("pclk", "fff9c000.ssc", &ssc0_clk),
099343c6 BS	247	CLKDEV_CON_DEV_ID("pclk", "fffa0000.ssc", &ssc1_clk),
237a62a1	248	CLKDEV_CON_DEV_ID(NULL, "atmel-trng", &trng_clk),
815e9721 NR	249	CLKDEV_CON_DEV_ID(NULL, "atmel_sha", &aestdessha_clk),
	250	CLKDEV_CON_DEV_ID(NULL, "atmel_tdes", &aestdessha_clk),
	251	CLKDEV_CON_DEV_ID(NULL, "atmel_aes", &aestdessha_clk),
49fe2ba3 NF	252	/* more usart lookup table for DT entries */
	253	CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck),
	254	CLKDEV_CON_DEV_ID("usart", "fff8c000.serial", &usart0_clk),
	255	CLKDEV_CON_DEV_ID("usart", "fff90000.serial", &usart1_clk),
	256	CLKDEV_CON_DEV_ID("usart", "fff94000.serial", &usart2_clk),
	257	CLKDEV_CON_DEV_ID("usart", "fff98000.serial", &usart3_clk),
3a61a5da NF	258	/* more tc lookup table for DT entries */
	259	CLKDEV_CON_DEV_ID("t0_clk", "fff7c000.timer", &tcb0_clk),
	260	CLKDEV_CON_DEV_ID("t0_clk", "fffd4000.timer", &tcb0_clk),
6a062459	261	CLKDEV_CON_DEV_ID("hclk", "700000.ohci", &uhphs_clk),
62c5553a	262	CLKDEV_CON_DEV_ID("ehci_clk", "800000.ehci", &uhphs_clk),
23e3b24f LD	263	CLKDEV_CON_DEV_ID("mci_clk", "fff80000.mmc", &mmc0_clk),
23e3b24f LD	264	CLKDEV_CON_DEV_ID("mci_clk", "fffd0000.mmc", &mmc1_clk),
f7d19b90 LD	265	CLKDEV_CON_DEV_ID(NULL, "fff84000.i2c", &twi0_clk),
f7d19b90 LD	266	CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi1_clk),
f0db66a5 RG	267	CLKDEV_CON_DEV_ID("spi_clk", "fffa4000.spi", &spi0_clk),
f0db66a5 RG	268	CLKDEV_CON_DEV_ID("spi_clk", "fffa8000.spi", &spi1_clk),
0af4316b JCPV	269	/* fake hclk clock */
0af4316b JCPV	270	CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk),
5314ec8e JCPV	271	CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk),
	272	CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioB_clk),
	273	CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioC_clk),
	274	CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioDE_clk),
	275	CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioDE_clk),
	276
619d4a4b JCPV	277	CLKDEV_CON_ID("pioA", &pioA_clk),
	278	CLKDEV_CON_ID("pioB", &pioB_clk),
	279	CLKDEV_CON_ID("pioC", &pioC_clk),
	280	CLKDEV_CON_ID("pioD", &pioDE_clk),
	281	CLKDEV_CON_ID("pioE", &pioDE_clk),
4a5920e8 MR	282	/* Fake adc clock */
4a5920e8 MR	283	CLKDEV_CON_ID("adc_clk", &tsc_clk),
bd602995 JCPV	284	};
	285
	286	static struct clk_lookup usart_clocks_lookups[] = {
	287	CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
	288	CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
	289	CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
	290	CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
	291	CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
789b23bc NF	292	};
	293
	294	/*
	295	* The two programmable clocks.
	296	* You must configure pin multiplexing to bring these signals out.
	297	*/
	298	static struct clk pck0 = {
	299	.name = "pck0",
	300	.pmc_mask = AT91_PMC_PCK0,
	301	.type = CLK_TYPE_PROGRAMMABLE,
	302	.id = 0,
	303	};
	304	static struct clk pck1 = {
	305	.name = "pck1",
	306	.pmc_mask = AT91_PMC_PCK1,
	307	.type = CLK_TYPE_PROGRAMMABLE,
	308	.id = 1,
	309	};
	310
	311	static void __init at91sam9g45_register_clocks(void)
	312	{
	313	int i;
	314
	315	for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
	316	clk_register(periph_clocks[i]);
	317
bd602995 JCPV	318	clkdev_add_table(periph_clocks_lookups,
	319	ARRAY_SIZE(periph_clocks_lookups));
	320	clkdev_add_table(usart_clocks_lookups,
	321	ARRAY_SIZE(usart_clocks_lookups));
	322
5f9f0a41 NF	323	if (cpu_is_at91sam9m10() \|\| cpu_is_at91sam9m11())
	324	clk_register(&vdec_clk);
	325
789b23bc NF	326	clk_register(&pck0);
	327	clk_register(&pck1);
	328	}
	329
	330	/* --------------------------------------------------------------------
	331	* GPIO
	332	* -------------------------------------------------------------------- */
	333
1a2d9156	334	static struct at91_gpio_bank at91sam9g45_gpio[] __initdata = {
789b23bc NF	335	{
789b23bc NF	336	.id = AT91SAM9G45_ID_PIOA,
80e91cb8	337	.regbase = AT91SAM9G45_BASE_PIOA,
789b23bc NF	338	}, {
789b23bc NF	339	.id = AT91SAM9G45_ID_PIOB,
80e91cb8	340	.regbase = AT91SAM9G45_BASE_PIOB,
789b23bc NF	341	}, {
789b23bc NF	342	.id = AT91SAM9G45_ID_PIOC,
80e91cb8	343	.regbase = AT91SAM9G45_BASE_PIOC,
789b23bc NF	344	}, {
789b23bc NF	345	.id = AT91SAM9G45_ID_PIODE,
80e91cb8	346	.regbase = AT91SAM9G45_BASE_PIOD,
789b23bc NF	347	}, {
789b23bc NF	348	.id = AT91SAM9G45_ID_PIODE,
80e91cb8	349	.regbase = AT91SAM9G45_BASE_PIOE,
789b23bc NF	350	}
	351	};
	352
789b23bc NF	353	/* --------------------------------------------------------------------
	354	* AT91SAM9G45 processor initialization
	355	* -------------------------------------------------------------------- */
	356
21d08b9d	357	static void __init at91sam9g45_map_io(void)
789b23bc	358	{
f0051d82	359	at91_init_sram(0, AT91SAM9G45_SRAM_BASE, AT91SAM9G45_SRAM_SIZE);
1b021a3b	360	}
789b23bc	361
cfa5a1fe JCPV	362	static void __init at91sam9g45_ioremap_registers(void)
cfa5a1fe JCPV	363	{
f22deee5	364	at91_ioremap_shdwc(AT91SAM9G45_BASE_SHDWC);
e9f68b5c	365	at91_ioremap_rstc(AT91SAM9G45_BASE_RSTC);
f363c407 JCPV	366	at91_ioremap_ramc(0, AT91SAM9G45_BASE_DDRSDRC1, 512);
f363c407 JCPV	367	at91_ioremap_ramc(1, AT91SAM9G45_BASE_DDRSDRC0, 512);
4ab0c599	368	at91sam926x_ioremap_pit(AT91SAM9G45_BASE_PIT);
faee0cc3	369	at91sam9_ioremap_smc(0, AT91SAM9G45_BASE_SMC);
4342d647	370	at91_ioremap_matrix(AT91SAM9G45_BASE_MATRIX);
cfa5a1fe JCPV	371	}
cfa5a1fe JCPV	372
46539374	373	static void __init at91sam9g45_initialize(void)
1b021a3b	374	{
0d781716	375	arm_pm_idle = at91sam9_idle;
1b2073e7	376	arm_pm_restart = at91sam9g45_restart;
789b23bc NF	377	at91_extern_irq = (1 << AT91SAM9G45_ID_IRQ0);
789b23bc NF	378
789b23bc NF	379	/* Register GPIO subsystem */
	380	at91_gpio_init(at91sam9g45_gpio, 5);
	381	}
	382
	383	/* --------------------------------------------------------------------
	384	* Interrupt initialization
	385	* -------------------------------------------------------------------- */
	386
	387	/*
	388	* The default interrupt priority levels (0 = lowest, 7 = highest).
	389	*/
	390	static unsigned int at91sam9g45_default_irq_priority[NR_AIC_IRQS] __initdata = {
	391	7, /* Advanced Interrupt Controller (FIQ) */
	392	7, /* System Peripherals */
	393	1, /* Parallel IO Controller A */
	394	1, /* Parallel IO Controller B */
	395	1, /* Parallel IO Controller C */
	396	1, /* Parallel IO Controller D and E */
	397	0,
	398	5, /* USART 0 */
	399	5, /* USART 1 */
	400	5, /* USART 2 */
	401	5, /* USART 3 */
	402	0, /* Multimedia Card Interface 0 */
	403	6, /* Two-Wire Interface 0 */
	404	6, /* Two-Wire Interface 1 */
	405	5, /* Serial Peripheral Interface 0 */
	406	5, /* Serial Peripheral Interface 1 */
	407	4, /* Serial Synchronous Controller 0 */
	408	4, /* Serial Synchronous Controller 1 */
	409	0, /* Timer Counter 0, 1, 2, 3, 4 and 5 */
	410	0, /* Pulse Width Modulation Controller */
	411	0, /* Touch Screen Controller */
	412	0, /* DMA Controller */
	413	2, /* USB Host High Speed port */
	414	3, /* LDC Controller */
	415	5, /* AC97 Controller */
	416	3, /* Ethernet */
	417	0, /* Image Sensor Interface */
	418	2, /* USB Device High speed port */
815e9721	419	0, /* AESTDESSHA Crypto HW Accelerators */
789b23bc NF	420	0, /* Multimedia Card Interface 1 */
	421	0,
	422	0, /* Advanced Interrupt Controller (IRQ0) */
	423	};
	424
84ddb087	425	AT91_SOC_START(at91sam9g45)
21d08b9d	426	.map_io = at91sam9g45_map_io,
92100c12	427	.default_irq_priority = at91sam9g45_default_irq_priority,
cfa5a1fe	428	.ioremap_registers = at91sam9g45_ioremap_registers,
51ddec76	429	.register_clocks = at91sam9g45_register_clocks,
21d08b9d	430	.init = at91sam9g45_initialize,
8d39e0fd	431	AT91_SOC_END