[deliverable/linux.git] / arch / arm / mach-at91 / at91sam9g45.c

/*
 *  Chip-specific setup code for the AT91SAM9G45 family
 *
 *  Copyright (C) 2009 Atmel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 */

#include <linux/module.h>
#include <linux/pm.h>

#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <mach/at91sam9g45.h>
#include <mach/at91_pmc.h>
#include <mach/at91_rstc.h>
#include <mach/at91_shdwc.h>
#include <mach/cpu.h>

#include "soc.h"
#include "generic.h"
#include "clock.h"

static struct map_desc at91sam9g45_sram_desc[] __initdata = {
	{
		.virtual	= AT91_IO_VIRT_BASE - AT91SAM9G45_SRAM_SIZE,
		.pfn		= __phys_to_pfn(AT91SAM9G45_SRAM_BASE),
		.length		= AT91SAM9G45_SRAM_SIZE,
		.type		= MT_DEVICE,
	}
};

/* --------------------------------------------------------------------
 *  Clocks
 * -------------------------------------------------------------------- */

/*
 * The peripheral clocks.
 */
static struct clk pioA_clk = {
	.name		= "pioA_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_PIOA,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk pioB_clk = {
	.name		= "pioB_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_PIOB,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk pioC_clk = {
	.name		= "pioC_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_PIOC,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk pioDE_clk = {
	.name		= "pioDE_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_PIODE,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart0_clk = {
	.name		= "usart0_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_US0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart1_clk = {
	.name		= "usart1_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_US1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart2_clk = {
	.name		= "usart2_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_US2,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart3_clk = {
	.name		= "usart3_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_US3,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk mmc0_clk = {
	.name		= "mci0_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_MCI0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk twi0_clk = {
	.name		= "twi0_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_TWI0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk twi1_clk = {
	.name		= "twi1_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_TWI1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk spi0_clk = {
	.name		= "spi0_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_SPI0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk spi1_clk = {
	.name		= "spi1_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_SPI1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk ssc0_clk = {
	.name		= "ssc0_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_SSC0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk ssc1_clk = {
	.name		= "ssc1_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_SSC1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk tcb0_clk = {
	.name		= "tcb0_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_TCB,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk pwm_clk = {
	.name		= "pwm_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_PWMC,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk tsc_clk = {
	.name		= "tsc_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_TSC,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk dma_clk = {
	.name		= "dma_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_DMA,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk uhphs_clk = {
	.name		= "uhphs_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_UHPHS,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk lcdc_clk = {
	.name		= "lcdc_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_LCDC,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk ac97_clk = {
	.name		= "ac97_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_AC97C,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk macb_clk = {
	.name		= "macb_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_EMAC,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk isi_clk = {
	.name		= "isi_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_ISI,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk udphs_clk = {
	.name		= "udphs_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_UDPHS,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk mmc1_clk = {
	.name		= "mci1_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_MCI1,
	.type		= CLK_TYPE_PERIPHERAL,
};

/* Video decoder clock - Only for sam9m10/sam9m11 */
static struct clk vdec_clk = {
	.name		= "vdec_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_VDEC,
	.type		= CLK_TYPE_PERIPHERAL,
};

static struct clk *periph_clocks[] __initdata = {
	&pioA_clk,
	&pioB_clk,
	&pioC_clk,
	&pioDE_clk,
	&usart0_clk,
	&usart1_clk,
	&usart2_clk,
	&usart3_clk,
	&mmc0_clk,
	&twi0_clk,
	&twi1_clk,
	&spi0_clk,
	&spi1_clk,
	&ssc0_clk,
	&ssc1_clk,
	&tcb0_clk,
	&pwm_clk,
	&tsc_clk,
	&dma_clk,
	&uhphs_clk,
	&lcdc_clk,
	&ac97_clk,
	&macb_clk,
	&isi_clk,
	&udphs_clk,
	&mmc1_clk,
	// irq0
};

static struct clk_lookup periph_clocks_lookups[] = {
	/* One additional fake clock for ohci */
	CLKDEV_CON_ID("ohci_clk", &uhphs_clk),
	CLKDEV_CON_DEV_ID("ehci_clk", "atmel-ehci", &uhphs_clk),
	CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
	CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
	CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.0", &mmc0_clk),
	CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.1", &mmc1_clk),
	CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
	CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
	CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb0_clk),
	CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tcb0_clk),
	CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
	CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
};

static struct clk_lookup usart_clocks_lookups[] = {
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
};

/*
 * The two programmable clocks.
 * You must configure pin multiplexing to bring these signals out.
 */
static struct clk pck0 = {
	.name		= "pck0",
	.pmc_mask	= AT91_PMC_PCK0,
	.type		= CLK_TYPE_PROGRAMMABLE,
	.id		= 0,
};
static struct clk pck1 = {
	.name		= "pck1",
	.pmc_mask	= AT91_PMC_PCK1,
	.type		= CLK_TYPE_PROGRAMMABLE,
	.id		= 1,
};

static void __init at91sam9g45_register_clocks(void)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
		clk_register(periph_clocks[i]);

	clkdev_add_table(periph_clocks_lookups,
			 ARRAY_SIZE(periph_clocks_lookups));
	clkdev_add_table(usart_clocks_lookups,
			 ARRAY_SIZE(usart_clocks_lookups));

	if (cpu_is_at91sam9m10() || cpu_is_at91sam9m11())
		clk_register(&vdec_clk);

	clk_register(&pck0);
	clk_register(&pck1);
}

static struct clk_lookup console_clock_lookup;

void __init at91sam9g45_set_console_clock(int id)
{
	if (id >= ARRAY_SIZE(usart_clocks_lookups))
		return;

	console_clock_lookup.con_id = "usart";
	console_clock_lookup.clk = usart_clocks_lookups[id].clk;
	clkdev_add(&console_clock_lookup);
}

/* --------------------------------------------------------------------
 *  GPIO
 * -------------------------------------------------------------------- */

static struct at91_gpio_bank at91sam9g45_gpio[] = {
	{
		.id		= AT91SAM9G45_ID_PIOA,
		.offset		= AT91_PIOA,
		.clock		= &pioA_clk,
	}, {
		.id		= AT91SAM9G45_ID_PIOB,
		.offset		= AT91_PIOB,
		.clock		= &pioB_clk,
	}, {
		.id		= AT91SAM9G45_ID_PIOC,
		.offset		= AT91_PIOC,
		.clock		= &pioC_clk,
	}, {
		.id		= AT91SAM9G45_ID_PIODE,
		.offset		= AT91_PIOD,
		.clock		= &pioDE_clk,
	}, {
		.id		= AT91SAM9G45_ID_PIODE,
		.offset		= AT91_PIOE,
		.clock		= &pioDE_clk,
	}
};

static void at91sam9g45_reset(void)
{
	at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
}

static void at91sam9g45_poweroff(void)
{
	at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
}


/* --------------------------------------------------------------------
 *  AT91SAM9G45 processor initialization
 * -------------------------------------------------------------------- */

static void __init at91sam9g45_map_io(void)
{
	iotable_init(at91sam9g45_sram_desc, ARRAY_SIZE(at91sam9g45_sram_desc));
}

static void __init at91sam9g45_initialize(void)
{
	at91_arch_reset = at91sam9g45_reset;
	pm_power_off = at91sam9g45_poweroff;
	at91_extern_irq = (1 << AT91SAM9G45_ID_IRQ0);

	/* Register the processor-specific clocks */
	at91sam9g45_register_clocks();

	/* Register GPIO subsystem */
	at91_gpio_init(at91sam9g45_gpio, 5);
}

/* --------------------------------------------------------------------
 *  Interrupt initialization
 * -------------------------------------------------------------------- */

/*
 * The default interrupt priority levels (0 = lowest, 7 = highest).
 */
static unsigned int at91sam9g45_default_irq_priority[NR_AIC_IRQS] __initdata = {
	7,	/* Advanced Interrupt Controller (FIQ) */
	7,	/* System Peripherals */
	1,	/* Parallel IO Controller A */
	1,	/* Parallel IO Controller B */
	1,	/* Parallel IO Controller C */
	1,	/* Parallel IO Controller D and E */
	0,
	5,	/* USART 0 */
	5,	/* USART 1 */
	5,	/* USART 2 */
	5,	/* USART 3 */
	0,	/* Multimedia Card Interface 0 */
	6,	/* Two-Wire Interface 0 */
	6,	/* Two-Wire Interface 1 */
	5,	/* Serial Peripheral Interface 0 */
	5,	/* Serial Peripheral Interface 1 */
	4,	/* Serial Synchronous Controller 0 */
	4,	/* Serial Synchronous Controller 1 */
	0,	/* Timer Counter 0, 1, 2, 3, 4 and 5 */
	0,	/* Pulse Width Modulation Controller */
	0,	/* Touch Screen Controller */
	0,	/* DMA Controller */
	2,	/* USB Host High Speed port */
	3,	/* LDC Controller */
	5,	/* AC97 Controller */
	3,	/* Ethernet */
	0,	/* Image Sensor Interface */
	2,	/* USB Device High speed port */
	0,
	0,	/* Multimedia Card Interface 1 */
	0,
	0,	/* Advanced Interrupt Controller (IRQ0) */
};

struct at91_init_soc __initdata at91sam9g45_soc = {
	.map_io = at91sam9g45_map_io,
	.default_irq_priority = at91sam9g45_default_irq_priority,
	.init = at91sam9g45_initialize,
};
Commit	Line	Data
789b23bc NF	1	/*
	2	* Chip-specific setup code for the AT91SAM9G45 family
	3	*
	4	* Copyright (C) 2009 Atmel Corporation.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	*/
	12
	13	#include <linux/module.h>
	14	#include <linux/pm.h>
	15
	16	#include <asm/irq.h>
	17	#include <asm/mach/arch.h>
	18	#include <asm/mach/map.h>
	19	#include <mach/at91sam9g45.h>
	20	#include <mach/at91_pmc.h>
	21	#include <mach/at91_rstc.h>
	22	#include <mach/at91_shdwc.h>
5f9f0a41	23	#include <mach/cpu.h>
789b23bc	24
21d08b9d	25	#include "soc.h"
789b23bc NF	26	#include "generic.h"
	27	#include "clock.h"
	28
21d08b9d	29	static struct map_desc at91sam9g45_sram_desc[] __initdata = {
789b23bc	30	{
789b23bc NF	31	.virtual = AT91_IO_VIRT_BASE - AT91SAM9G45_SRAM_SIZE,
	32	.pfn = __phys_to_pfn(AT91SAM9G45_SRAM_BASE),
	33	.length = AT91SAM9G45_SRAM_SIZE,
	34	.type = MT_DEVICE,
	35	}
	36	};
	37
	38	/* --------------------------------------------------------------------
	39	* Clocks
	40	* -------------------------------------------------------------------- */
	41
	42	/*
	43	* The peripheral clocks.
	44	*/
	45	static struct clk pioA_clk = {
	46	.name = "pioA_clk",
	47	.pmc_mask = 1 << AT91SAM9G45_ID_PIOA,
	48	.type = CLK_TYPE_PERIPHERAL,
	49	};
	50	static struct clk pioB_clk = {
	51	.name = "pioB_clk",
	52	.pmc_mask = 1 << AT91SAM9G45_ID_PIOB,
	53	.type = CLK_TYPE_PERIPHERAL,
	54	};
	55	static struct clk pioC_clk = {
	56	.name = "pioC_clk",
	57	.pmc_mask = 1 << AT91SAM9G45_ID_PIOC,
	58	.type = CLK_TYPE_PERIPHERAL,
	59	};
	60	static struct clk pioDE_clk = {
	61	.name = "pioDE_clk",
	62	.pmc_mask = 1 << AT91SAM9G45_ID_PIODE,
	63	.type = CLK_TYPE_PERIPHERAL,
	64	};
	65	static struct clk usart0_clk = {
	66	.name = "usart0_clk",
	67	.pmc_mask = 1 << AT91SAM9G45_ID_US0,
	68	.type = CLK_TYPE_PERIPHERAL,
	69	};
	70	static struct clk usart1_clk = {
	71	.name = "usart1_clk",
	72	.pmc_mask = 1 << AT91SAM9G45_ID_US1,
	73	.type = CLK_TYPE_PERIPHERAL,
	74	};
	75	static struct clk usart2_clk = {
	76	.name = "usart2_clk",
	77	.pmc_mask = 1 << AT91SAM9G45_ID_US2,
	78	.type = CLK_TYPE_PERIPHERAL,
	79	};
	80	static struct clk usart3_clk = {
	81	.name = "usart3_clk",
	82	.pmc_mask = 1 << AT91SAM9G45_ID_US3,
	83	.type = CLK_TYPE_PERIPHERAL,
	84	};
	85	static struct clk mmc0_clk = {
	86	.name = "mci0_clk",
	87	.pmc_mask = 1 << AT91SAM9G45_ID_MCI0,
	88	.type = CLK_TYPE_PERIPHERAL,
	89	};
	90	static struct clk twi0_clk = {
	91	.name = "twi0_clk",
	92	.pmc_mask = 1 << AT91SAM9G45_ID_TWI0,
	93	.type = CLK_TYPE_PERIPHERAL,
	94	};
95	static struct clk twi1_clk = {
96	.name = "twi1_clk",
97	.pmc_mask = 1 << AT91SAM9G45_ID_TWI1,
98	.type = CLK_TYPE_PERIPHERAL,
99	};
100	static struct clk spi0_clk = {
101	.name = "spi0_clk",
102	.pmc_mask = 1 << AT91SAM9G45_ID_SPI0,
103	.type = CLK_TYPE_PERIPHERAL,
104	};
105	static struct clk spi1_clk = {
106	.name = "spi1_clk",
107	.pmc_mask = 1 << AT91SAM9G45_ID_SPI1,
108	.type = CLK_TYPE_PERIPHERAL,
109	};
110	static struct clk ssc0_clk = {
111	.name = "ssc0_clk",
112	.pmc_mask = 1 << AT91SAM9G45_ID_SSC0,
113	.type = CLK_TYPE_PERIPHERAL,
114	};
115	static struct clk ssc1_clk = {
116	.name = "ssc1_clk",
117	.pmc_mask = 1 << AT91SAM9G45_ID_SSC1,
118	.type = CLK_TYPE_PERIPHERAL,
119	};
ab64511c FG	120	static struct clk tcb0_clk = {
ab64511c FG	121	.name = "tcb0_clk",
789b23bc NF	122	.pmc_mask = 1 << AT91SAM9G45_ID_TCB,
	123	.type = CLK_TYPE_PERIPHERAL,
	124	};
	125	static struct clk pwm_clk = {
	126	.name = "pwm_clk",
	127	.pmc_mask = 1 << AT91SAM9G45_ID_PWMC,
	128	.type = CLK_TYPE_PERIPHERAL,
	129	};
	130	static struct clk tsc_clk = {
	131	.name = "tsc_clk",
	132	.pmc_mask = 1 << AT91SAM9G45_ID_TSC,
	133	.type = CLK_TYPE_PERIPHERAL,
	134	};
	135	static struct clk dma_clk = {
	136	.name = "dma_clk",
	137	.pmc_mask = 1 << AT91SAM9G45_ID_DMA,
	138	.type = CLK_TYPE_PERIPHERAL,
	139	};
	140	static struct clk uhphs_clk = {
	141	.name = "uhphs_clk",
	142	.pmc_mask = 1 << AT91SAM9G45_ID_UHPHS,
	143	.type = CLK_TYPE_PERIPHERAL,
	144	};
	145	static struct clk lcdc_clk = {
	146	.name = "lcdc_clk",
	147	.pmc_mask = 1 << AT91SAM9G45_ID_LCDC,
	148	.type = CLK_TYPE_PERIPHERAL,
	149	};
	150	static struct clk ac97_clk = {
	151	.name = "ac97_clk",
	152	.pmc_mask = 1 << AT91SAM9G45_ID_AC97C,
	153	.type = CLK_TYPE_PERIPHERAL,
	154	};
	155	static struct clk macb_clk = {
	156	.name = "macb_clk",
	157	.pmc_mask = 1 << AT91SAM9G45_ID_EMAC,
	158	.type = CLK_TYPE_PERIPHERAL,
	159	};
	160	static struct clk isi_clk = {
	161	.name = "isi_clk",
	162	.pmc_mask = 1 << AT91SAM9G45_ID_ISI,
	163	.type = CLK_TYPE_PERIPHERAL,
	164	};
	165	static struct clk udphs_clk = {
	166	.name = "udphs_clk",
	167	.pmc_mask = 1 << AT91SAM9G45_ID_UDPHS,
	168	.type = CLK_TYPE_PERIPHERAL,
	169	};
	170	static struct clk mmc1_clk = {
	171	.name = "mci1_clk",
	172	.pmc_mask = 1 << AT91SAM9G45_ID_MCI1,
	173	.type = CLK_TYPE_PERIPHERAL,
	174	};
	175
5f9f0a41 NF	176	/* Video decoder clock - Only for sam9m10/sam9m11 */
	177	static struct clk vdec_clk = {
	178	.name = "vdec_clk",
	179	.pmc_mask = 1 << AT91SAM9G45_ID_VDEC,
	180	.type = CLK_TYPE_PERIPHERAL,
	181	};
	182
789b23bc NF	183	static struct clk *periph_clocks[] __initdata = {
	184	&pioA_clk,
	185	&pioB_clk,
	186	&pioC_clk,
	187	&pioDE_clk,
	188	&usart0_clk,
	189	&usart1_clk,
	190	&usart2_clk,
	191	&usart3_clk,
	192	&mmc0_clk,
	193	&twi0_clk,
	194	&twi1_clk,
	195	&spi0_clk,
	196	&spi1_clk,
	197	&ssc0_clk,
	198	&ssc1_clk,
ab64511c	199	&tcb0_clk,
789b23bc NF	200	&pwm_clk,
	201	&tsc_clk,
	202	&dma_clk,
	203	&uhphs_clk,
	204	&lcdc_clk,
	205	&ac97_clk,
	206	&macb_clk,
	207	&isi_clk,
	208	&udphs_clk,
	209	&mmc1_clk,
	210	// irq0
bd602995 JCPV	211	};
	212
	213	static struct clk_lookup periph_clocks_lookups[] = {
	214	/* One additional fake clock for ohci */
	215	CLKDEV_CON_ID("ohci_clk", &uhphs_clk),
9d87159e JCPV	216	CLKDEV_CON_DEV_ID("ehci_clk", "atmel-ehci", &uhphs_clk),
	217	CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
	218	CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
	219	CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.0", &mmc0_clk),
	220	CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.1", &mmc1_clk),
bd602995 JCPV	221	CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
	222	CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
	223	CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb0_clk),
	224	CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tcb0_clk),
	225	CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
	226	CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
	227	};
	228
	229	static struct clk_lookup usart_clocks_lookups[] = {
	230	CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
	231	CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
	232	CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
	233	CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
	234	CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
789b23bc NF	235	};
	236
	237	/*
	238	* The two programmable clocks.
	239	* You must configure pin multiplexing to bring these signals out.
	240	*/
	241	static struct clk pck0 = {
	242	.name = "pck0",
	243	.pmc_mask = AT91_PMC_PCK0,
	244	.type = CLK_TYPE_PROGRAMMABLE,
	245	.id = 0,
	246	};
	247	static struct clk pck1 = {
	248	.name = "pck1",
	249	.pmc_mask = AT91_PMC_PCK1,
	250	.type = CLK_TYPE_PROGRAMMABLE,
	251	.id = 1,
	252	};
	253
	254	static void __init at91sam9g45_register_clocks(void)
	255	{
	256	int i;
	257
	258	for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
	259	clk_register(periph_clocks[i]);
	260
bd602995 JCPV	261	clkdev_add_table(periph_clocks_lookups,
	262	ARRAY_SIZE(periph_clocks_lookups));
	263	clkdev_add_table(usart_clocks_lookups,
	264	ARRAY_SIZE(usart_clocks_lookups));
	265
5f9f0a41 NF	266	if (cpu_is_at91sam9m10() \|\| cpu_is_at91sam9m11())
	267	clk_register(&vdec_clk);
	268
789b23bc NF	269	clk_register(&pck0);
	270	clk_register(&pck1);
	271	}
	272
bd602995 JCPV	273	static struct clk_lookup console_clock_lookup;
	274
	275	void __init at91sam9g45_set_console_clock(int id)
	276	{
	277	if (id >= ARRAY_SIZE(usart_clocks_lookups))
	278	return;
	279
	280	console_clock_lookup.con_id = "usart";
	281	console_clock_lookup.clk = usart_clocks_lookups[id].clk;
	282	clkdev_add(&console_clock_lookup);
	283	}
	284
789b23bc NF	285	/* --------------------------------------------------------------------
	286	* GPIO
	287	* -------------------------------------------------------------------- */
	288
	289	static struct at91_gpio_bank at91sam9g45_gpio[] = {
	290	{
	291	.id = AT91SAM9G45_ID_PIOA,
	292	.offset = AT91_PIOA,
	293	.clock = &pioA_clk,
	294	}, {
	295	.id = AT91SAM9G45_ID_PIOB,
	296	.offset = AT91_PIOB,
	297	.clock = &pioB_clk,
	298	}, {
	299	.id = AT91SAM9G45_ID_PIOC,
	300	.offset = AT91_PIOC,
	301	.clock = &pioC_clk,
	302	}, {
	303	.id = AT91SAM9G45_ID_PIODE,
	304	.offset = AT91_PIOD,
	305	.clock = &pioDE_clk,
	306	}, {
	307	.id = AT91SAM9G45_ID_PIODE,
	308	.offset = AT91_PIOE,
	309	.clock = &pioDE_clk,
	310	}
	311	};
	312
	313	static void at91sam9g45_reset(void)
	314	{
	315	at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY \| AT91_RSTC_PROCRST \| AT91_RSTC_PERRST);
	316	}
	317
	318	static void at91sam9g45_poweroff(void)
	319	{
	320	at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY \| AT91_SHDW_SHDW);
	321	}
	322
	323
	324	/* --------------------------------------------------------------------
	325	* AT91SAM9G45 processor initialization
	326	* -------------------------------------------------------------------- */
	327
21d08b9d	328	static void __init at91sam9g45_map_io(void)
789b23bc	329	{
21d08b9d	330	iotable_init(at91sam9g45_sram_desc, ARRAY_SIZE(at91sam9g45_sram_desc));
1b021a3b	331	}
789b23bc	332
46539374	333	static void __init at91sam9g45_initialize(void)
1b021a3b	334	{
789b23bc NF	335	at91_arch_reset = at91sam9g45_reset;
	336	pm_power_off = at91sam9g45_poweroff;
	337	at91_extern_irq = (1 << AT91SAM9G45_ID_IRQ0);
	338
789b23bc NF	339	/* Register the processor-specific clocks */
	340	at91sam9g45_register_clocks();
	341
	342	/* Register GPIO subsystem */
	343	at91_gpio_init(at91sam9g45_gpio, 5);
	344	}
	345
	346	/* --------------------------------------------------------------------
	347	* Interrupt initialization
	348	* -------------------------------------------------------------------- */
	349
	350	/*
	351	* The default interrupt priority levels (0 = lowest, 7 = highest).
	352	*/
	353	static unsigned int at91sam9g45_default_irq_priority[NR_AIC_IRQS] __initdata = {
	354	7, /* Advanced Interrupt Controller (FIQ) */
	355	7, /* System Peripherals */
	356	1, /* Parallel IO Controller A */
	357	1, /* Parallel IO Controller B */
	358	1, /* Parallel IO Controller C */
	359	1, /* Parallel IO Controller D and E */
	360	0,
	361	5, /* USART 0 */
	362	5, /* USART 1 */
	363	5, /* USART 2 */
	364	5, /* USART 3 */
	365	0, /* Multimedia Card Interface 0 */
	366	6, /* Two-Wire Interface 0 */
	367	6, /* Two-Wire Interface 1 */
	368	5, /* Serial Peripheral Interface 0 */
	369	5, /* Serial Peripheral Interface 1 */
	370	4, /* Serial Synchronous Controller 0 */
	371	4, /* Serial Synchronous Controller 1 */
	372	0, /* Timer Counter 0, 1, 2, 3, 4 and 5 */
	373	0, /* Pulse Width Modulation Controller */
	374	0, /* Touch Screen Controller */
	375	0, /* DMA Controller */
	376	2, /* USB Host High Speed port */
	377	3, /* LDC Controller */
	378	5, /* AC97 Controller */
	379	3, /* Ethernet */
	380	0, /* Image Sensor Interface */
	381	2, /* USB Device High speed port */
	382	0,
	383	0, /* Multimedia Card Interface 1 */
	384	0,
	385	0, /* Advanced Interrupt Controller (IRQ0) */
	386	};
	387
8c3583b6	388	struct at91_init_soc __initdata at91sam9g45_soc = {
21d08b9d	389	.map_io = at91sam9g45_map_io,
92100c12	390	.default_irq_priority = at91sam9g45_default_irq_priority,
21d08b9d JCPV	391	.init = at91sam9g45_initialize,
21d08b9d JCPV	392	};