[deliverable/linux.git] / arch / arm / mach-at91 / at91sam9g45.c

/*
 *  Chip-specific setup code for the AT91SAM9G45 family
 *
 *  Copyright (C) 2009 Atmel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 */

#include <linux/module.h>
#include <linux/pm.h>

#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <mach/at91sam9g45.h>
#include <mach/at91_pmc.h>
#include <mach/at91_rstc.h>
#include <mach/at91_shdwc.h>
#include <mach/cpu.h>

#include "soc.h"
#include "generic.h"
#include "clock.h"

/* --------------------------------------------------------------------
 *  Clocks
 * -------------------------------------------------------------------- */

/*
 * The peripheral clocks.
 */
static struct clk pioA_clk = {
	.name		= "pioA_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_PIOA,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk pioB_clk = {
	.name		= "pioB_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_PIOB,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk pioC_clk = {
	.name		= "pioC_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_PIOC,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk pioDE_clk = {
	.name		= "pioDE_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_PIODE,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart0_clk = {
	.name		= "usart0_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_US0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart1_clk = {
	.name		= "usart1_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_US1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart2_clk = {
	.name		= "usart2_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_US2,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart3_clk = {
	.name		= "usart3_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_US3,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk mmc0_clk = {
	.name		= "mci0_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_MCI0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk twi0_clk = {
	.name		= "twi0_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_TWI0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk twi1_clk = {
	.name		= "twi1_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_TWI1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk spi0_clk = {
	.name		= "spi0_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_SPI0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk spi1_clk = {
	.name		= "spi1_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_SPI1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk ssc0_clk = {
	.name		= "ssc0_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_SSC0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk ssc1_clk = {
	.name		= "ssc1_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_SSC1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk tcb0_clk = {
	.name		= "tcb0_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_TCB,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk pwm_clk = {
	.name		= "pwm_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_PWMC,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk tsc_clk = {
	.name		= "tsc_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_TSC,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk dma_clk = {
	.name		= "dma_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_DMA,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk uhphs_clk = {
	.name		= "uhphs_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_UHPHS,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk lcdc_clk = {
	.name		= "lcdc_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_LCDC,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk ac97_clk = {
	.name		= "ac97_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_AC97C,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk macb_clk = {
	.name		= "macb_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_EMAC,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk isi_clk = {
	.name		= "isi_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_ISI,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk udphs_clk = {
	.name		= "udphs_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_UDPHS,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk mmc1_clk = {
	.name		= "mci1_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_MCI1,
	.type		= CLK_TYPE_PERIPHERAL,
};

/* Video decoder clock - Only for sam9m10/sam9m11 */
static struct clk vdec_clk = {
	.name		= "vdec_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_VDEC,
	.type		= CLK_TYPE_PERIPHERAL,
};

static struct clk *periph_clocks[] __initdata = {
	&pioA_clk,
	&pioB_clk,
	&pioC_clk,
	&pioDE_clk,
	&usart0_clk,
	&usart1_clk,
	&usart2_clk,
	&usart3_clk,
	&mmc0_clk,
	&twi0_clk,
	&twi1_clk,
	&spi0_clk,
	&spi1_clk,
	&ssc0_clk,
	&ssc1_clk,
	&tcb0_clk,
	&pwm_clk,
	&tsc_clk,
	&dma_clk,
	&uhphs_clk,
	&lcdc_clk,
	&ac97_clk,
	&macb_clk,
	&isi_clk,
	&udphs_clk,
	&mmc1_clk,
	// irq0
};

static struct clk_lookup periph_clocks_lookups[] = {
	/* One additional fake clock for ohci */
	CLKDEV_CON_ID("ohci_clk", &uhphs_clk),
	CLKDEV_CON_DEV_ID("ehci_clk", "atmel-ehci", &uhphs_clk),
	CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
	CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
	CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.0", &mmc0_clk),
	CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.1", &mmc1_clk),
	CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
	CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
	CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb0_clk),
	CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tcb0_clk),
	CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
	CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
};

static struct clk_lookup usart_clocks_lookups[] = {
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
};

/*
 * The two programmable clocks.
 * You must configure pin multiplexing to bring these signals out.
 */
static struct clk pck0 = {
	.name		= "pck0",
	.pmc_mask	= AT91_PMC_PCK0,
	.type		= CLK_TYPE_PROGRAMMABLE,
	.id		= 0,
};
static struct clk pck1 = {
	.name		= "pck1",
	.pmc_mask	= AT91_PMC_PCK1,
	.type		= CLK_TYPE_PROGRAMMABLE,
	.id		= 1,
};

static void __init at91sam9g45_register_clocks(void)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
		clk_register(periph_clocks[i]);

	clkdev_add_table(periph_clocks_lookups,
			 ARRAY_SIZE(periph_clocks_lookups));
	clkdev_add_table(usart_clocks_lookups,
			 ARRAY_SIZE(usart_clocks_lookups));

	if (cpu_is_at91sam9m10() || cpu_is_at91sam9m11())
		clk_register(&vdec_clk);

	clk_register(&pck0);
	clk_register(&pck1);
}

static struct clk_lookup console_clock_lookup;

void __init at91sam9g45_set_console_clock(int id)
{
	if (id >= ARRAY_SIZE(usart_clocks_lookups))
		return;

	console_clock_lookup.con_id = "usart";
	console_clock_lookup.clk = usart_clocks_lookups[id].clk;
	clkdev_add(&console_clock_lookup);
}

/* --------------------------------------------------------------------
 *  GPIO
 * -------------------------------------------------------------------- */

static struct at91_gpio_bank at91sam9g45_gpio[] = {
	{
		.id		= AT91SAM9G45_ID_PIOA,
		.offset		= AT91_PIOA,
		.clock		= &pioA_clk,
	}, {
		.id		= AT91SAM9G45_ID_PIOB,
		.offset		= AT91_PIOB,
		.clock		= &pioB_clk,
	}, {
		.id		= AT91SAM9G45_ID_PIOC,
		.offset		= AT91_PIOC,
		.clock		= &pioC_clk,
	}, {
		.id		= AT91SAM9G45_ID_PIODE,
		.offset		= AT91_PIOD,
		.clock		= &pioDE_clk,
	}, {
		.id		= AT91SAM9G45_ID_PIODE,
		.offset		= AT91_PIOE,
		.clock		= &pioDE_clk,
	}
};

static void at91sam9g45_reset(void)
{
	at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
}

static void at91sam9g45_poweroff(void)
{
	at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
}


/* --------------------------------------------------------------------
 *  AT91SAM9G45 processor initialization
 * -------------------------------------------------------------------- */

static void __init at91sam9g45_map_io(void)
{
	at91_init_sram(0, AT91SAM9G45_SRAM_BASE, AT91SAM9G45_SRAM_SIZE);
}

static void __init at91sam9g45_initialize(void)
{
	at91_arch_reset = at91sam9g45_reset;
	pm_power_off = at91sam9g45_poweroff;
	at91_extern_irq = (1 << AT91SAM9G45_ID_IRQ0);

	/* Register GPIO subsystem */
	at91_gpio_init(at91sam9g45_gpio, 5);
}

/* --------------------------------------------------------------------
 *  Interrupt initialization
 * -------------------------------------------------------------------- */

/*
 * The default interrupt priority levels (0 = lowest, 7 = highest).
 */
static unsigned int at91sam9g45_default_irq_priority[NR_AIC_IRQS] __initdata = {
	7,	/* Advanced Interrupt Controller (FIQ) */
	7,	/* System Peripherals */
	1,	/* Parallel IO Controller A */
	1,	/* Parallel IO Controller B */
	1,	/* Parallel IO Controller C */
	1,	/* Parallel IO Controller D and E */
	0,
	5,	/* USART 0 */
	5,	/* USART 1 */
	5,	/* USART 2 */
	5,	/* USART 3 */
	0,	/* Multimedia Card Interface 0 */
	6,	/* Two-Wire Interface 0 */
	6,	/* Two-Wire Interface 1 */
	5,	/* Serial Peripheral Interface 0 */
	5,	/* Serial Peripheral Interface 1 */
	4,	/* Serial Synchronous Controller 0 */
	4,	/* Serial Synchronous Controller 1 */
	0,	/* Timer Counter 0, 1, 2, 3, 4 and 5 */
	0,	/* Pulse Width Modulation Controller */
	0,	/* Touch Screen Controller */
	0,	/* DMA Controller */
	2,	/* USB Host High Speed port */
	3,	/* LDC Controller */
	5,	/* AC97 Controller */
	3,	/* Ethernet */
	0,	/* Image Sensor Interface */
	2,	/* USB Device High speed port */
	0,
	0,	/* Multimedia Card Interface 1 */
	0,
	0,	/* Advanced Interrupt Controller (IRQ0) */
};

struct at91_init_soc __initdata at91sam9g45_soc = {
	.map_io = at91sam9g45_map_io,
	.default_irq_priority = at91sam9g45_default_irq_priority,
	.register_clocks = at91sam9g45_register_clocks,
	.init = at91sam9g45_initialize,
};
Commit	Line	Data
789b23bc NF	1	/*
	2	* Chip-specific setup code for the AT91SAM9G45 family
	3	*
	4	* Copyright (C) 2009 Atmel Corporation.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	*/
	12
	13	#include <linux/module.h>
	14	#include <linux/pm.h>
	15
	16	#include <asm/irq.h>
	17	#include <asm/mach/arch.h>
	18	#include <asm/mach/map.h>
	19	#include <mach/at91sam9g45.h>
	20	#include <mach/at91_pmc.h>
	21	#include <mach/at91_rstc.h>
	22	#include <mach/at91_shdwc.h>
5f9f0a41	23	#include <mach/cpu.h>
789b23bc	24
21d08b9d	25	#include "soc.h"
789b23bc NF	26	#include "generic.h"
	27	#include "clock.h"
	28
789b23bc NF	29	/* --------------------------------------------------------------------
	30	* Clocks
	31	* -------------------------------------------------------------------- */
	32
	33	/*
	34	* The peripheral clocks.
	35	*/
	36	static struct clk pioA_clk = {
	37	.name = "pioA_clk",
	38	.pmc_mask = 1 << AT91SAM9G45_ID_PIOA,
	39	.type = CLK_TYPE_PERIPHERAL,
	40	};
	41	static struct clk pioB_clk = {
	42	.name = "pioB_clk",
	43	.pmc_mask = 1 << AT91SAM9G45_ID_PIOB,
	44	.type = CLK_TYPE_PERIPHERAL,
	45	};
	46	static struct clk pioC_clk = {
	47	.name = "pioC_clk",
	48	.pmc_mask = 1 << AT91SAM9G45_ID_PIOC,
	49	.type = CLK_TYPE_PERIPHERAL,
	50	};
	51	static struct clk pioDE_clk = {
	52	.name = "pioDE_clk",
	53	.pmc_mask = 1 << AT91SAM9G45_ID_PIODE,
	54	.type = CLK_TYPE_PERIPHERAL,
	55	};
	56	static struct clk usart0_clk = {
	57	.name = "usart0_clk",
	58	.pmc_mask = 1 << AT91SAM9G45_ID_US0,
	59	.type = CLK_TYPE_PERIPHERAL,
	60	};
	61	static struct clk usart1_clk = {
	62	.name = "usart1_clk",
	63	.pmc_mask = 1 << AT91SAM9G45_ID_US1,
	64	.type = CLK_TYPE_PERIPHERAL,
	65	};
	66	static struct clk usart2_clk = {
	67	.name = "usart2_clk",
	68	.pmc_mask = 1 << AT91SAM9G45_ID_US2,
	69	.type = CLK_TYPE_PERIPHERAL,
	70	};
	71	static struct clk usart3_clk = {
	72	.name = "usart3_clk",
	73	.pmc_mask = 1 << AT91SAM9G45_ID_US3,
	74	.type = CLK_TYPE_PERIPHERAL,
	75	};
	76	static struct clk mmc0_clk = {
	77	.name = "mci0_clk",
	78	.pmc_mask = 1 << AT91SAM9G45_ID_MCI0,
	79	.type = CLK_TYPE_PERIPHERAL,
	80	};
	81	static struct clk twi0_clk = {
	82	.name = "twi0_clk",
	83	.pmc_mask = 1 << AT91SAM9G45_ID_TWI0,
	84	.type = CLK_TYPE_PERIPHERAL,
	85	};
	86	static struct clk twi1_clk = {
	87	.name = "twi1_clk",
	88	.pmc_mask = 1 << AT91SAM9G45_ID_TWI1,
	89	.type = CLK_TYPE_PERIPHERAL,
	90	};
	91	static struct clk spi0_clk = {
	92	.name = "spi0_clk",
93	.pmc_mask = 1 << AT91SAM9G45_ID_SPI0,
94	.type = CLK_TYPE_PERIPHERAL,
95	};
96	static struct clk spi1_clk = {
97	.name = "spi1_clk",
98	.pmc_mask = 1 << AT91SAM9G45_ID_SPI1,
99	.type = CLK_TYPE_PERIPHERAL,
100	};
101	static struct clk ssc0_clk = {
102	.name = "ssc0_clk",
103	.pmc_mask = 1 << AT91SAM9G45_ID_SSC0,
104	.type = CLK_TYPE_PERIPHERAL,
105	};
106	static struct clk ssc1_clk = {
107	.name = "ssc1_clk",
108	.pmc_mask = 1 << AT91SAM9G45_ID_SSC1,
109	.type = CLK_TYPE_PERIPHERAL,
110	};
ab64511c FG	111	static struct clk tcb0_clk = {
ab64511c FG	112	.name = "tcb0_clk",
789b23bc NF	113	.pmc_mask = 1 << AT91SAM9G45_ID_TCB,
	114	.type = CLK_TYPE_PERIPHERAL,
	115	};
	116	static struct clk pwm_clk = {
	117	.name = "pwm_clk",
	118	.pmc_mask = 1 << AT91SAM9G45_ID_PWMC,
	119	.type = CLK_TYPE_PERIPHERAL,
	120	};
	121	static struct clk tsc_clk = {
	122	.name = "tsc_clk",
	123	.pmc_mask = 1 << AT91SAM9G45_ID_TSC,
	124	.type = CLK_TYPE_PERIPHERAL,
	125	};
	126	static struct clk dma_clk = {
	127	.name = "dma_clk",
	128	.pmc_mask = 1 << AT91SAM9G45_ID_DMA,
	129	.type = CLK_TYPE_PERIPHERAL,
	130	};
	131	static struct clk uhphs_clk = {
	132	.name = "uhphs_clk",
	133	.pmc_mask = 1 << AT91SAM9G45_ID_UHPHS,
	134	.type = CLK_TYPE_PERIPHERAL,
	135	};
	136	static struct clk lcdc_clk = {
	137	.name = "lcdc_clk",
	138	.pmc_mask = 1 << AT91SAM9G45_ID_LCDC,
	139	.type = CLK_TYPE_PERIPHERAL,
	140	};
	141	static struct clk ac97_clk = {
	142	.name = "ac97_clk",
	143	.pmc_mask = 1 << AT91SAM9G45_ID_AC97C,
	144	.type = CLK_TYPE_PERIPHERAL,
	145	};
	146	static struct clk macb_clk = {
	147	.name = "macb_clk",
	148	.pmc_mask = 1 << AT91SAM9G45_ID_EMAC,
	149	.type = CLK_TYPE_PERIPHERAL,
	150	};
	151	static struct clk isi_clk = {
	152	.name = "isi_clk",
	153	.pmc_mask = 1 << AT91SAM9G45_ID_ISI,
	154	.type = CLK_TYPE_PERIPHERAL,
	155	};
	156	static struct clk udphs_clk = {
	157	.name = "udphs_clk",
	158	.pmc_mask = 1 << AT91SAM9G45_ID_UDPHS,
	159	.type = CLK_TYPE_PERIPHERAL,
	160	};
	161	static struct clk mmc1_clk = {
	162	.name = "mci1_clk",
	163	.pmc_mask = 1 << AT91SAM9G45_ID_MCI1,
	164	.type = CLK_TYPE_PERIPHERAL,
	165	};
	166
5f9f0a41 NF	167	/* Video decoder clock - Only for sam9m10/sam9m11 */
	168	static struct clk vdec_clk = {
	169	.name = "vdec_clk",
	170	.pmc_mask = 1 << AT91SAM9G45_ID_VDEC,
	171	.type = CLK_TYPE_PERIPHERAL,
	172	};
	173
789b23bc NF	174	static struct clk *periph_clocks[] __initdata = {
	175	&pioA_clk,
	176	&pioB_clk,
	177	&pioC_clk,
	178	&pioDE_clk,
	179	&usart0_clk,
	180	&usart1_clk,
	181	&usart2_clk,
	182	&usart3_clk,
	183	&mmc0_clk,
	184	&twi0_clk,
	185	&twi1_clk,
	186	&spi0_clk,
	187	&spi1_clk,
	188	&ssc0_clk,
	189	&ssc1_clk,
ab64511c	190	&tcb0_clk,
789b23bc NF	191	&pwm_clk,
	192	&tsc_clk,
	193	&dma_clk,
	194	&uhphs_clk,
	195	&lcdc_clk,
	196	&ac97_clk,
	197	&macb_clk,
	198	&isi_clk,
	199	&udphs_clk,
	200	&mmc1_clk,
	201	// irq0
bd602995 JCPV	202	};
	203
	204	static struct clk_lookup periph_clocks_lookups[] = {
	205	/* One additional fake clock for ohci */
	206	CLKDEV_CON_ID("ohci_clk", &uhphs_clk),
9d87159e JCPV	207	CLKDEV_CON_DEV_ID("ehci_clk", "atmel-ehci", &uhphs_clk),
	208	CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
	209	CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
	210	CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.0", &mmc0_clk),
	211	CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.1", &mmc1_clk),
bd602995 JCPV	212	CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
	213	CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
	214	CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb0_clk),
	215	CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tcb0_clk),
	216	CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
	217	CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
	218	};
	219
	220	static struct clk_lookup usart_clocks_lookups[] = {
	221	CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
	222	CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
	223	CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
	224	CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
	225	CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
789b23bc NF	226	};
	227
	228	/*
	229	* The two programmable clocks.
	230	* You must configure pin multiplexing to bring these signals out.
	231	*/
	232	static struct clk pck0 = {
	233	.name = "pck0",
	234	.pmc_mask = AT91_PMC_PCK0,
	235	.type = CLK_TYPE_PROGRAMMABLE,
	236	.id = 0,
	237	};
	238	static struct clk pck1 = {
	239	.name = "pck1",
	240	.pmc_mask = AT91_PMC_PCK1,
	241	.type = CLK_TYPE_PROGRAMMABLE,
	242	.id = 1,
	243	};
	244
	245	static void __init at91sam9g45_register_clocks(void)
	246	{
	247	int i;
	248
	249	for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
	250	clk_register(periph_clocks[i]);
	251
bd602995 JCPV	252	clkdev_add_table(periph_clocks_lookups,
	253	ARRAY_SIZE(periph_clocks_lookups));
	254	clkdev_add_table(usart_clocks_lookups,
	255	ARRAY_SIZE(usart_clocks_lookups));
	256
5f9f0a41 NF	257	if (cpu_is_at91sam9m10() \|\| cpu_is_at91sam9m11())
	258	clk_register(&vdec_clk);
	259
789b23bc NF	260	clk_register(&pck0);
	261	clk_register(&pck1);
	262	}
	263
bd602995 JCPV	264	static struct clk_lookup console_clock_lookup;
	265
	266	void __init at91sam9g45_set_console_clock(int id)
	267	{
	268	if (id >= ARRAY_SIZE(usart_clocks_lookups))
	269	return;
	270
	271	console_clock_lookup.con_id = "usart";
	272	console_clock_lookup.clk = usart_clocks_lookups[id].clk;
	273	clkdev_add(&console_clock_lookup);
	274	}
	275
789b23bc NF	276	/* --------------------------------------------------------------------
	277	* GPIO
	278	* -------------------------------------------------------------------- */
	279
	280	static struct at91_gpio_bank at91sam9g45_gpio[] = {
	281	{
	282	.id = AT91SAM9G45_ID_PIOA,
	283	.offset = AT91_PIOA,
	284	.clock = &pioA_clk,
	285	}, {
	286	.id = AT91SAM9G45_ID_PIOB,
	287	.offset = AT91_PIOB,
	288	.clock = &pioB_clk,
	289	}, {
	290	.id = AT91SAM9G45_ID_PIOC,
	291	.offset = AT91_PIOC,
	292	.clock = &pioC_clk,
	293	}, {
	294	.id = AT91SAM9G45_ID_PIODE,
	295	.offset = AT91_PIOD,
	296	.clock = &pioDE_clk,
	297	}, {
	298	.id = AT91SAM9G45_ID_PIODE,
	299	.offset = AT91_PIOE,
	300	.clock = &pioDE_clk,
	301	}
	302	};
	303
	304	static void at91sam9g45_reset(void)
	305	{
	306	at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY \| AT91_RSTC_PROCRST \| AT91_RSTC_PERRST);
	307	}
	308
	309	static void at91sam9g45_poweroff(void)
	310	{
	311	at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY \| AT91_SHDW_SHDW);
	312	}
	313
	314
	315	/* --------------------------------------------------------------------
	316	* AT91SAM9G45 processor initialization
	317	* -------------------------------------------------------------------- */
	318
21d08b9d	319	static void __init at91sam9g45_map_io(void)
789b23bc	320	{
f0051d82	321	at91_init_sram(0, AT91SAM9G45_SRAM_BASE, AT91SAM9G45_SRAM_SIZE);
1b021a3b	322	}
789b23bc	323
46539374	324	static void __init at91sam9g45_initialize(void)
1b021a3b	325	{
789b23bc NF	326	at91_arch_reset = at91sam9g45_reset;
	327	pm_power_off = at91sam9g45_poweroff;
	328	at91_extern_irq = (1 << AT91SAM9G45_ID_IRQ0);
	329
789b23bc NF	330	/* Register GPIO subsystem */
	331	at91_gpio_init(at91sam9g45_gpio, 5);
	332	}
	333
	334	/* --------------------------------------------------------------------
	335	* Interrupt initialization
	336	* -------------------------------------------------------------------- */
	337
	338	/*
	339	* The default interrupt priority levels (0 = lowest, 7 = highest).
	340	*/
	341	static unsigned int at91sam9g45_default_irq_priority[NR_AIC_IRQS] __initdata = {
	342	7, /* Advanced Interrupt Controller (FIQ) */
	343	7, /* System Peripherals */
	344	1, /* Parallel IO Controller A */
	345	1, /* Parallel IO Controller B */
	346	1, /* Parallel IO Controller C */
	347	1, /* Parallel IO Controller D and E */
	348	0,
	349	5, /* USART 0 */
	350	5, /* USART 1 */
	351	5, /* USART 2 */
	352	5, /* USART 3 */
	353	0, /* Multimedia Card Interface 0 */
	354	6, /* Two-Wire Interface 0 */
	355	6, /* Two-Wire Interface 1 */
	356	5, /* Serial Peripheral Interface 0 */
	357	5, /* Serial Peripheral Interface 1 */
	358	4, /* Serial Synchronous Controller 0 */
	359	4, /* Serial Synchronous Controller 1 */
	360	0, /* Timer Counter 0, 1, 2, 3, 4 and 5 */
	361	0, /* Pulse Width Modulation Controller */
	362	0, /* Touch Screen Controller */
	363	0, /* DMA Controller */
	364	2, /* USB Host High Speed port */
	365	3, /* LDC Controller */
	366	5, /* AC97 Controller */
	367	3, /* Ethernet */
	368	0, /* Image Sensor Interface */
	369	2, /* USB Device High speed port */
	370	0,
	371	0, /* Multimedia Card Interface 1 */
	372	0,
	373	0, /* Advanced Interrupt Controller (IRQ0) */
	374	};
	375
8c3583b6	376	struct at91_init_soc __initdata at91sam9g45_soc = {
21d08b9d	377	.map_io = at91sam9g45_map_io,
92100c12	378	.default_irq_priority = at91sam9g45_default_irq_priority,
51ddec76	379	.register_clocks = at91sam9g45_register_clocks,
21d08b9d JCPV	380	.init = at91sam9g45_initialize,
21d08b9d JCPV	381	};