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ARM: at91/dt: kizbox: define main crystal frequency
[deliverable/linux.git] / arch / arm / mach-at91 / at91sam9g45.c
CommitLineData
789b23bc
NF		 1/*
2 * Chip-specific setup code for the AT91SAM9G45 family
3 *
4 * Copyright (C) 2009 Atmel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 */
12
13#include <linux/module.h>
f407c2e3 14#include <linux/dma-mapping.h>
2edb90ae 15#include <linux/clk/at91_pmc.h>
789b23bc
NF		 16
17#include <asm/irq.h>
18#include <asm/mach/arch.h>
19#include <asm/mach/map.h>
9f97da78 20#include <asm/system_misc.h>
789b23bc 21#include <mach/at91sam9g45.h>
5f9f0a41 22#include <mach/cpu.h>
ac11a1d4 23#include <mach/hardware.h>
789b23bc 24
a510b9ba 25#include "at91_aic.h"
21d08b9d 26#include "soc.h"
789b23bc
NF		 27#include "generic.h"
28#include "clock.h"
faee0cc3 29#include "sam9_smc.h"
5ad945ea 30#include "pm.h"
789b23bc 31
789b23bc
NF		 32/* --------------------------------------------------------------------
33 * Clocks
34 * -------------------------------------------------------------------- */
35
36/*
37 * The peripheral clocks.
38 */
39static struct clk pioA_clk = {
40 .name = "pioA_clk",
41 .pmc_mask = 1 << AT91SAM9G45_ID_PIOA,
42 .type = CLK_TYPE_PERIPHERAL,
43};
44static struct clk pioB_clk = {
45 .name = "pioB_clk",
46 .pmc_mask = 1 << AT91SAM9G45_ID_PIOB,
47 .type = CLK_TYPE_PERIPHERAL,
48};
49static struct clk pioC_clk = {
50 .name = "pioC_clk",
51 .pmc_mask = 1 << AT91SAM9G45_ID_PIOC,
52 .type = CLK_TYPE_PERIPHERAL,
53};
54static struct clk pioDE_clk = {
55 .name = "pioDE_clk",
56 .pmc_mask = 1 << AT91SAM9G45_ID_PIODE,
57 .type = CLK_TYPE_PERIPHERAL,
58};
237a62a1
PK		 59static struct clk trng_clk = {
60 .name = "trng_clk",
61 .pmc_mask = 1 << AT91SAM9G45_ID_TRNG,
62 .type = CLK_TYPE_PERIPHERAL,
63};
789b23bc
NF		 64static struct clk usart0_clk = {
65 .name = "usart0_clk",
66 .pmc_mask = 1 << AT91SAM9G45_ID_US0,
67 .type = CLK_TYPE_PERIPHERAL,
68};
69static struct clk usart1_clk = {
70 .name = "usart1_clk",
71 .pmc_mask = 1 << AT91SAM9G45_ID_US1,
72 .type = CLK_TYPE_PERIPHERAL,
73};
74static struct clk usart2_clk = {
75 .name = "usart2_clk",
76 .pmc_mask = 1 << AT91SAM9G45_ID_US2,
77 .type = CLK_TYPE_PERIPHERAL,
78};
79static struct clk usart3_clk = {
80 .name = "usart3_clk",
81 .pmc_mask = 1 << AT91SAM9G45_ID_US3,
82 .type = CLK_TYPE_PERIPHERAL,
83};
84static struct clk mmc0_clk = {
85 .name = "mci0_clk",
86 .pmc_mask = 1 << AT91SAM9G45_ID_MCI0,
87 .type = CLK_TYPE_PERIPHERAL,
88};
89static struct clk twi0_clk = {
90 .name = "twi0_clk",
91 .pmc_mask = 1 << AT91SAM9G45_ID_TWI0,
92 .type = CLK_TYPE_PERIPHERAL,
93};
94static struct clk twi1_clk = {
95 .name = "twi1_clk",
96 .pmc_mask = 1 << AT91SAM9G45_ID_TWI1,
97 .type = CLK_TYPE_PERIPHERAL,
98};
99static struct clk spi0_clk = {
100 .name = "spi0_clk",
101 .pmc_mask = 1 << AT91SAM9G45_ID_SPI0,
102 .type = CLK_TYPE_PERIPHERAL,
103};
104static struct clk spi1_clk = {
105 .name = "spi1_clk",
106 .pmc_mask = 1 << AT91SAM9G45_ID_SPI1,
107 .type = CLK_TYPE_PERIPHERAL,
108};
109static struct clk ssc0_clk = {
110 .name = "ssc0_clk",
111 .pmc_mask = 1 << AT91SAM9G45_ID_SSC0,
112 .type = CLK_TYPE_PERIPHERAL,
113};
114static struct clk ssc1_clk = {
115 .name = "ssc1_clk",
116 .pmc_mask = 1 << AT91SAM9G45_ID_SSC1,
117 .type = CLK_TYPE_PERIPHERAL,
118};
ab64511c
FG		 119static struct clk tcb0_clk = {
120 .name = "tcb0_clk",
789b23bc
NF		 121 .pmc_mask = 1 << AT91SAM9G45_ID_TCB,
122 .type = CLK_TYPE_PERIPHERAL,
123};
124static struct clk pwm_clk = {
125 .name = "pwm_clk",
126 .pmc_mask = 1 << AT91SAM9G45_ID_PWMC,
127 .type = CLK_TYPE_PERIPHERAL,
128};
129static struct clk tsc_clk = {
130 .name = "tsc_clk",
131 .pmc_mask = 1 << AT91SAM9G45_ID_TSC,
132 .type = CLK_TYPE_PERIPHERAL,
133};
134static struct clk dma_clk = {
135 .name = "dma_clk",
136 .pmc_mask = 1 << AT91SAM9G45_ID_DMA,
137 .type = CLK_TYPE_PERIPHERAL,
138};
139static struct clk uhphs_clk = {
140 .name = "uhphs_clk",
141 .pmc_mask = 1 << AT91SAM9G45_ID_UHPHS,
142 .type = CLK_TYPE_PERIPHERAL,
143};
144static struct clk lcdc_clk = {
145 .name = "lcdc_clk",
146 .pmc_mask = 1 << AT91SAM9G45_ID_LCDC,
147 .type = CLK_TYPE_PERIPHERAL,
148};
149static struct clk ac97_clk = {
150 .name = "ac97_clk",
151 .pmc_mask = 1 << AT91SAM9G45_ID_AC97C,
152 .type = CLK_TYPE_PERIPHERAL,
153};
154static struct clk macb_clk = {
865d605e 155 .name = "pclk",
789b23bc
NF		 156 .pmc_mask = 1 << AT91SAM9G45_ID_EMAC,
157 .type = CLK_TYPE_PERIPHERAL,
158};
159static struct clk isi_clk = {
160 .name = "isi_clk",
161 .pmc_mask = 1 << AT91SAM9G45_ID_ISI,
162 .type = CLK_TYPE_PERIPHERAL,
163};
164static struct clk udphs_clk = {
165 .name = "udphs_clk",
166 .pmc_mask = 1 << AT91SAM9G45_ID_UDPHS,
167 .type = CLK_TYPE_PERIPHERAL,
168};
169static struct clk mmc1_clk = {
170 .name = "mci1_clk",
171 .pmc_mask = 1 << AT91SAM9G45_ID_MCI1,
172 .type = CLK_TYPE_PERIPHERAL,
173};
174
5f9f0a41
NF		 175/* Video decoder clock - Only for sam9m10/sam9m11 */
176static struct clk vdec_clk = {
177 .name = "vdec_clk",
178 .pmc_mask = 1 << AT91SAM9G45_ID_VDEC,
179 .type = CLK_TYPE_PERIPHERAL,
180};
181
4a5920e8
MR		 182static struct clk adc_op_clk = {
183 .name = "adc_op_clk",
184 .type = CLK_TYPE_PERIPHERAL,
cab91594 185 .rate_hz = 300000,
4a5920e8
MR		 186};
187
815e9721
NR		 188/* AES/TDES/SHA clock - Only for sam9m11/sam9g56 */
189static struct clk aestdessha_clk = {
190 .name = "aestdessha_clk",
191 .pmc_mask = 1 << AT91SAM9G45_ID_AESTDESSHA,
192 .type = CLK_TYPE_PERIPHERAL,
193};
194
789b23bc
NF		 195static struct clk *periph_clocks[] __initdata = {
196 &pioA_clk,
197 &pioB_clk,
198 &pioC_clk,
199 &pioDE_clk,
237a62a1 200 &trng_clk,
789b23bc
NF		 201 &usart0_clk,
202 &usart1_clk,
203 &usart2_clk,
204 &usart3_clk,
205 &mmc0_clk,
206 &twi0_clk,
207 &twi1_clk,
208 &spi0_clk,
209 &spi1_clk,
210 &ssc0_clk,
211 &ssc1_clk,
ab64511c 212 &tcb0_clk,
789b23bc
NF		 213 &pwm_clk,
214 &tsc_clk,
215 &dma_clk,
216 &uhphs_clk,
217 &lcdc_clk,
218 &ac97_clk,
219 &macb_clk,
220 &isi_clk,
221 &udphs_clk,
222 &mmc1_clk,
4a5920e8 223 &adc_op_clk,
815e9721 224 &aestdessha_clk,
789b23bc 225 // irq0
bd602995
JCPV		 226};
227
228static struct clk_lookup periph_clocks_lookups[] = {
865d605e
JI		 229 /* One additional fake clock for macb_hclk */
230 CLKDEV_CON_ID("hclk", &macb_clk),
bd602995
JCPV		 231 /* One additional fake clock for ohci */
232 CLKDEV_CON_ID("ohci_clk", &uhphs_clk),
bbd44f6b
JH		 233 CLKDEV_CON_DEV_ID("hclk", "at91sam9g45-lcdfb.0", &lcdc_clk),
234 CLKDEV_CON_DEV_ID("hclk", "at91sam9g45es-lcdfb.0", &lcdc_clk),
9d87159e
JCPV		 235 CLKDEV_CON_DEV_ID("ehci_clk", "atmel-ehci", &uhphs_clk),
236 CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
237 CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
238 CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.0", &mmc0_clk),
239 CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.1", &mmc1_clk),
bd602995
JCPV		 240 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
241 CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
242 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb0_clk),
243 CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tcb0_clk),
fac368a0
NV		 244 CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.0", &twi0_clk),
245 CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.1", &twi1_clk),
636036d2
BS		 246 CLKDEV_CON_DEV_ID("pclk", "at91sam9g45_ssc.0", &ssc0_clk),
247 CLKDEV_CON_DEV_ID("pclk", "at91sam9g45_ssc.1", &ssc1_clk),
099343c6
BS		 248 CLKDEV_CON_DEV_ID("pclk", "fff9c000.ssc", &ssc0_clk),
249 CLKDEV_CON_DEV_ID("pclk", "fffa0000.ssc", &ssc1_clk),
237a62a1 250 CLKDEV_CON_DEV_ID(NULL, "atmel-trng", &trng_clk),
815e9721
NR		 251 CLKDEV_CON_DEV_ID(NULL, "atmel_sha", &aestdessha_clk),
252 CLKDEV_CON_DEV_ID(NULL, "atmel_tdes", &aestdessha_clk),
253 CLKDEV_CON_DEV_ID(NULL, "atmel_aes", &aestdessha_clk),
49fe2ba3
NF		 254 /* more usart lookup table for DT entries */
255 CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck),
256 CLKDEV_CON_DEV_ID("usart", "fff8c000.serial", &usart0_clk),
257 CLKDEV_CON_DEV_ID("usart", "fff90000.serial", &usart1_clk),
258 CLKDEV_CON_DEV_ID("usart", "fff94000.serial", &usart2_clk),
259 CLKDEV_CON_DEV_ID("usart", "fff98000.serial", &usart3_clk),
3a61a5da
NF		 260 /* more tc lookup table for DT entries */
261 CLKDEV_CON_DEV_ID("t0_clk", "fff7c000.timer", &tcb0_clk),
262 CLKDEV_CON_DEV_ID("t0_clk", "fffd4000.timer", &tcb0_clk),
6a062459 263 CLKDEV_CON_DEV_ID("hclk", "700000.ohci", &uhphs_clk),
62c5553a 264 CLKDEV_CON_DEV_ID("ehci_clk", "800000.ehci", &uhphs_clk),
23e3b24f
LD		 265 CLKDEV_CON_DEV_ID("mci_clk", "fff80000.mmc", &mmc0_clk),
266 CLKDEV_CON_DEV_ID("mci_clk", "fffd0000.mmc", &mmc1_clk),
f7d19b90
LD		 267 CLKDEV_CON_DEV_ID(NULL, "fff84000.i2c", &twi0_clk),
268 CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi1_clk),
f0db66a5
RG		 269 CLKDEV_CON_DEV_ID("spi_clk", "fffa4000.spi", &spi0_clk),
270 CLKDEV_CON_DEV_ID("spi_clk", "fffa8000.spi", &spi1_clk),
3cba498f
JCPV		 271 CLKDEV_CON_DEV_ID("hclk", "600000.gadget", &utmi_clk),
272 CLKDEV_CON_DEV_ID("pclk", "600000.gadget", &udphs_clk),
0af4316b
JCPV		 273 /* fake hclk clock */
274 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk),
5314ec8e
JCPV		 275 CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk),
276 CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioB_clk),
277 CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioC_clk),
278 CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioDE_clk),
279 CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioDE_clk),
280
619d4a4b
JCPV		 281 CLKDEV_CON_ID("pioA", &pioA_clk),
282 CLKDEV_CON_ID("pioB", &pioB_clk),
283 CLKDEV_CON_ID("pioC", &pioC_clk),
284 CLKDEV_CON_ID("pioD", &pioDE_clk),
285 CLKDEV_CON_ID("pioE", &pioDE_clk),
4a5920e8
MR		 286 /* Fake adc clock */
287 CLKDEV_CON_ID("adc_clk", &tsc_clk),
050208df 288 CLKDEV_CON_DEV_ID(NULL, "fffb8000.pwm", &pwm_clk),
bd602995
JCPV		 289};
290
291static struct clk_lookup usart_clocks_lookups[] = {
292 CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
293 CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
294 CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
295 CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
296 CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
789b23bc
NF		 297};
298
299/*
300 * The two programmable clocks.
301 * You must configure pin multiplexing to bring these signals out.
302 */
303static struct clk pck0 = {
304 .name = "pck0",
305 .pmc_mask = AT91_PMC_PCK0,
306 .type = CLK_TYPE_PROGRAMMABLE,
307 .id = 0,
308};
309static struct clk pck1 = {
310 .name = "pck1",
311 .pmc_mask = AT91_PMC_PCK1,
312 .type = CLK_TYPE_PROGRAMMABLE,
313 .id = 1,
314};
315
316static void __init at91sam9g45_register_clocks(void)
317{
318 int i;
319
320 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
321 clk_register(periph_clocks[i]);
322
bd602995
JCPV		 323 clkdev_add_table(periph_clocks_lookups,
324 ARRAY_SIZE(periph_clocks_lookups));
325 clkdev_add_table(usart_clocks_lookups,
326 ARRAY_SIZE(usart_clocks_lookups));
327
5f9f0a41
NF		 328 if (cpu_is_at91sam9m10() || cpu_is_at91sam9m11())
329 clk_register(&vdec_clk);
330
789b23bc
NF		 331 clk_register(&pck0);
332 clk_register(&pck1);
333}
334
335/* --------------------------------------------------------------------
336 * GPIO
337 * -------------------------------------------------------------------- */
338
1a2d9156 339static struct at91_gpio_bank at91sam9g45_gpio[] __initdata = {
789b23bc
NF		 340 {
341 .id = AT91SAM9G45_ID_PIOA,
80e91cb8 342 .regbase = AT91SAM9G45_BASE_PIOA,
789b23bc
NF		 343 }, {
344 .id = AT91SAM9G45_ID_PIOB,
80e91cb8 345 .regbase = AT91SAM9G45_BASE_PIOB,
789b23bc
NF		 346 }, {
347 .id = AT91SAM9G45_ID_PIOC,
80e91cb8 348 .regbase = AT91SAM9G45_BASE_PIOC,
789b23bc
NF		 349 }, {
350 .id = AT91SAM9G45_ID_PIODE,
80e91cb8 351 .regbase = AT91SAM9G45_BASE_PIOD,
789b23bc
NF		 352 }, {
353 .id = AT91SAM9G45_ID_PIODE,
80e91cb8 354 .regbase = AT91SAM9G45_BASE_PIOE,
789b23bc
NF		 355 }
356};
357
789b23bc
NF		 358/* --------------------------------------------------------------------
359 * AT91SAM9G45 processor initialization
360 * -------------------------------------------------------------------- */
361
21d08b9d 362static void __init at91sam9g45_map_io(void)
789b23bc 363{
f0051d82 364 at91_init_sram(0, AT91SAM9G45_SRAM_BASE, AT91SAM9G45_SRAM_SIZE);
1b021a3b 365}
789b23bc 366
cfa5a1fe
JCPV		 367static void __init at91sam9g45_ioremap_registers(void)
368{
f22deee5 369 at91_ioremap_shdwc(AT91SAM9G45_BASE_SHDWC);
e9f68b5c 370 at91_ioremap_rstc(AT91SAM9G45_BASE_RSTC);
f363c407
JCPV		 371 at91_ioremap_ramc(0, AT91SAM9G45_BASE_DDRSDRC1, 512);
372 at91_ioremap_ramc(1, AT91SAM9G45_BASE_DDRSDRC0, 512);
4ab0c599 373 at91sam926x_ioremap_pit(AT91SAM9G45_BASE_PIT);
faee0cc3 374 at91sam9_ioremap_smc(0, AT91SAM9G45_BASE_SMC);
4342d647 375 at91_ioremap_matrix(AT91SAM9G45_BASE_MATRIX);
6b625891 376 at91_pm_set_standby(at91_ddr_standby);
cfa5a1fe
JCPV		 377}
378
46539374 379static void __init at91sam9g45_initialize(void)
1b021a3b 380{
0d781716 381 arm_pm_idle = at91sam9_idle;
1b2073e7 382 arm_pm_restart = at91sam9g45_restart;
789b23bc 383
6de714c2 384 at91_sysirq_mask_rtc(AT91SAM9G45_BASE_RTC);
94c4c79f 385 at91_sysirq_mask_rtt(AT91SAM9G45_BASE_RTT);
6de714c2 386
789b23bc
NF		 387 /* Register GPIO subsystem */
388 at91_gpio_init(at91sam9g45_gpio, 5);
389}
390
391/* --------------------------------------------------------------------
392 * Interrupt initialization
393 * -------------------------------------------------------------------- */
394
395/*
396 * The default interrupt priority levels (0 = lowest, 7 = highest).
397 */
398static unsigned int at91sam9g45_default_irq_priority[NR_AIC_IRQS] __initdata = {
399 7, /* Advanced Interrupt Controller (FIQ) */
400 7, /* System Peripherals */
401 1, /* Parallel IO Controller A */
402 1, /* Parallel IO Controller B */
403 1, /* Parallel IO Controller C */
404 1, /* Parallel IO Controller D and E */
405 0,
406 5, /* USART 0 */
407 5, /* USART 1 */
408 5, /* USART 2 */
409 5, /* USART 3 */
410 0, /* Multimedia Card Interface 0 */
411 6, /* Two-Wire Interface 0 */
412 6, /* Two-Wire Interface 1 */
413 5, /* Serial Peripheral Interface 0 */
414 5, /* Serial Peripheral Interface 1 */
415 4, /* Serial Synchronous Controller 0 */
416 4, /* Serial Synchronous Controller 1 */
417 0, /* Timer Counter 0, 1, 2, 3, 4 and 5 */
418 0, /* Pulse Width Modulation Controller */
419 0, /* Touch Screen Controller */
420 0, /* DMA Controller */
421 2, /* USB Host High Speed port */
422 3, /* LDC Controller */
423 5, /* AC97 Controller */
424 3, /* Ethernet */
425 0, /* Image Sensor Interface */
426 2, /* USB Device High speed port */
815e9721 427 0, /* AESTDESSHA Crypto HW Accelerators */
789b23bc
NF		 428 0, /* Multimedia Card Interface 1 */
429 0,
430 0, /* Advanced Interrupt Controller (IRQ0) */
431};
432
84ddb087 433AT91_SOC_START(at91sam9g45)
21d08b9d 434 .map_io = at91sam9g45_map_io,
92100c12 435 .default_irq_priority = at91sam9g45_default_irq_priority,
546c830c 436 .extern_irq = (1 << AT91SAM9G45_ID_IRQ0),
cfa5a1fe 437 .ioremap_registers = at91sam9g45_ioremap_registers,
51ddec76 438 .register_clocks = at91sam9g45_register_clocks,
21d08b9d 439 .init = at91sam9g45_initialize,
8d39e0fd 440AT91_SOC_END
Linux kernel - Deliverables
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