[deliverable/linux.git] / arch / arm / mach-at91 / at91sam9g45.c

/*
 *  Chip-specific setup code for the AT91SAM9G45 family
 *
 *  Copyright (C) 2009 Atmel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 */

#include <linux/module.h>
#include <linux/pm.h>
#include <linux/dma-mapping.h>

#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <mach/at91sam9g45.h>
#include <mach/at91_pmc.h>
#include <mach/at91_rstc.h>
#include <mach/at91_shdwc.h>
#include <mach/cpu.h>

#include "soc.h"
#include "generic.h"
#include "clock.h"

/* --------------------------------------------------------------------
 *  Clocks
 * -------------------------------------------------------------------- */

/*
 * The peripheral clocks.
 */
static struct clk pioA_clk = {
	.name		= "pioA_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_PIOA,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk pioB_clk = {
	.name		= "pioB_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_PIOB,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk pioC_clk = {
	.name		= "pioC_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_PIOC,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk pioDE_clk = {
	.name		= "pioDE_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_PIODE,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk trng_clk = {
	.name		= "trng_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_TRNG,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart0_clk = {
	.name		= "usart0_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_US0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart1_clk = {
	.name		= "usart1_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_US1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart2_clk = {
	.name		= "usart2_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_US2,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart3_clk = {
	.name		= "usart3_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_US3,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk mmc0_clk = {
	.name		= "mci0_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_MCI0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk twi0_clk = {
	.name		= "twi0_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_TWI0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk twi1_clk = {
	.name		= "twi1_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_TWI1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk spi0_clk = {
	.name		= "spi0_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_SPI0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk spi1_clk = {
	.name		= "spi1_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_SPI1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk ssc0_clk = {
	.name		= "ssc0_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_SSC0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk ssc1_clk = {
	.name		= "ssc1_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_SSC1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk tcb0_clk = {
	.name		= "tcb0_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_TCB,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk pwm_clk = {
	.name		= "pwm_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_PWMC,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk tsc_clk = {
	.name		= "tsc_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_TSC,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk dma_clk = {
	.name		= "dma_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_DMA,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk uhphs_clk = {
	.name		= "uhphs_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_UHPHS,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk lcdc_clk = {
	.name		= "lcdc_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_LCDC,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk ac97_clk = {
	.name		= "ac97_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_AC97C,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk macb_clk = {
	.name		= "macb_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_EMAC,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk isi_clk = {
	.name		= "isi_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_ISI,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk udphs_clk = {
	.name		= "udphs_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_UDPHS,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk mmc1_clk = {
	.name		= "mci1_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_MCI1,
	.type		= CLK_TYPE_PERIPHERAL,
};

/* Video decoder clock - Only for sam9m10/sam9m11 */
static struct clk vdec_clk = {
	.name		= "vdec_clk",
	.pmc_mask	= 1 << AT91SAM9G45_ID_VDEC,
	.type		= CLK_TYPE_PERIPHERAL,
};

static struct clk *periph_clocks[] __initdata = {
	&pioA_clk,
	&pioB_clk,
	&pioC_clk,
	&pioDE_clk,
	&trng_clk,
	&usart0_clk,
	&usart1_clk,
	&usart2_clk,
	&usart3_clk,
	&mmc0_clk,
	&twi0_clk,
	&twi1_clk,
	&spi0_clk,
	&spi1_clk,
	&ssc0_clk,
	&ssc1_clk,
	&tcb0_clk,
	&pwm_clk,
	&tsc_clk,
	&dma_clk,
	&uhphs_clk,
	&lcdc_clk,
	&ac97_clk,
	&macb_clk,
	&isi_clk,
	&udphs_clk,
	&mmc1_clk,
	// irq0
};

static struct clk_lookup periph_clocks_lookups[] = {
	/* One additional fake clock for ohci */
	CLKDEV_CON_ID("ohci_clk", &uhphs_clk),
	CLKDEV_CON_DEV_ID("ehci_clk", "atmel-ehci", &uhphs_clk),
	CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
	CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
	CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.0", &mmc0_clk),
	CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.1", &mmc1_clk),
	CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
	CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
	CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb0_clk),
	CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tcb0_clk),
	CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
	CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
	CLKDEV_CON_DEV_ID(NULL, "atmel-trng", &trng_clk),
	/* more usart lookup table for DT entries */
	CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck),
	CLKDEV_CON_DEV_ID("usart", "fff8c000.serial", &usart0_clk),
	CLKDEV_CON_DEV_ID("usart", "fff90000.serial", &usart1_clk),
	CLKDEV_CON_DEV_ID("usart", "fff94000.serial", &usart2_clk),
	CLKDEV_CON_DEV_ID("usart", "fff98000.serial", &usart3_clk),
	/* fake hclk clock */
	CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk),
};

static struct clk_lookup usart_clocks_lookups[] = {
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
};

/*
 * The two programmable clocks.
 * You must configure pin multiplexing to bring these signals out.
 */
static struct clk pck0 = {
	.name		= "pck0",
	.pmc_mask	= AT91_PMC_PCK0,
	.type		= CLK_TYPE_PROGRAMMABLE,
	.id		= 0,
};
static struct clk pck1 = {
	.name		= "pck1",
	.pmc_mask	= AT91_PMC_PCK1,
	.type		= CLK_TYPE_PROGRAMMABLE,
	.id		= 1,
};

static void __init at91sam9g45_register_clocks(void)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
		clk_register(periph_clocks[i]);

	clkdev_add_table(periph_clocks_lookups,
			 ARRAY_SIZE(periph_clocks_lookups));
	clkdev_add_table(usart_clocks_lookups,
			 ARRAY_SIZE(usart_clocks_lookups));

	if (cpu_is_at91sam9m10() || cpu_is_at91sam9m11())
		clk_register(&vdec_clk);

	clk_register(&pck0);
	clk_register(&pck1);
}

static struct clk_lookup console_clock_lookup;

void __init at91sam9g45_set_console_clock(int id)
{
	if (id >= ARRAY_SIZE(usart_clocks_lookups))
		return;

	console_clock_lookup.con_id = "usart";
	console_clock_lookup.clk = usart_clocks_lookups[id].clk;
	clkdev_add(&console_clock_lookup);
}

/* --------------------------------------------------------------------
 *  GPIO
 * -------------------------------------------------------------------- */

static struct at91_gpio_bank at91sam9g45_gpio[] = {
	{
		.id		= AT91SAM9G45_ID_PIOA,
		.regbase	= AT91SAM9G45_BASE_PIOA,
		.clock		= &pioA_clk,
	}, {
		.id		= AT91SAM9G45_ID_PIOB,
		.regbase	= AT91SAM9G45_BASE_PIOB,
		.clock		= &pioB_clk,
	}, {
		.id		= AT91SAM9G45_ID_PIOC,
		.regbase	= AT91SAM9G45_BASE_PIOC,
		.clock		= &pioC_clk,
	}, {
		.id		= AT91SAM9G45_ID_PIODE,
		.regbase	= AT91SAM9G45_BASE_PIOD,
		.clock		= &pioDE_clk,
	}, {
		.id		= AT91SAM9G45_ID_PIODE,
		.regbase	= AT91SAM9G45_BASE_PIOE,
		.clock		= &pioDE_clk,
	}
};

static void at91sam9g45_reset(void)
{
	at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
}

static void at91sam9g45_poweroff(void)
{
	at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
}


/* --------------------------------------------------------------------
 *  AT91SAM9G45 processor initialization
 * -------------------------------------------------------------------- */

static void __init at91sam9g45_map_io(void)
{
	at91_init_sram(0, AT91SAM9G45_SRAM_BASE, AT91SAM9G45_SRAM_SIZE);
	init_consistent_dma_size(SZ_4M);
}

static void __init at91sam9g45_initialize(void)
{
	at91_arch_reset = at91sam9g45_reset;
	pm_power_off = at91sam9g45_poweroff;
	at91_extern_irq = (1 << AT91SAM9G45_ID_IRQ0);

	/* Register GPIO subsystem */
	at91_gpio_init(at91sam9g45_gpio, 5);
}

/* --------------------------------------------------------------------
 *  Interrupt initialization
 * -------------------------------------------------------------------- */

/*
 * The default interrupt priority levels (0 = lowest, 7 = highest).
 */
static unsigned int at91sam9g45_default_irq_priority[NR_AIC_IRQS] __initdata = {
	7,	/* Advanced Interrupt Controller (FIQ) */
	7,	/* System Peripherals */
	1,	/* Parallel IO Controller A */
	1,	/* Parallel IO Controller B */
	1,	/* Parallel IO Controller C */
	1,	/* Parallel IO Controller D and E */
	0,
	5,	/* USART 0 */
	5,	/* USART 1 */
	5,	/* USART 2 */
	5,	/* USART 3 */
	0,	/* Multimedia Card Interface 0 */
	6,	/* Two-Wire Interface 0 */
	6,	/* Two-Wire Interface 1 */
	5,	/* Serial Peripheral Interface 0 */
	5,	/* Serial Peripheral Interface 1 */
	4,	/* Serial Synchronous Controller 0 */
	4,	/* Serial Synchronous Controller 1 */
	0,	/* Timer Counter 0, 1, 2, 3, 4 and 5 */
	0,	/* Pulse Width Modulation Controller */
	0,	/* Touch Screen Controller */
	0,	/* DMA Controller */
	2,	/* USB Host High Speed port */
	3,	/* LDC Controller */
	5,	/* AC97 Controller */
	3,	/* Ethernet */
	0,	/* Image Sensor Interface */
	2,	/* USB Device High speed port */
	0,
	0,	/* Multimedia Card Interface 1 */
	0,
	0,	/* Advanced Interrupt Controller (IRQ0) */
};

struct at91_init_soc __initdata at91sam9g45_soc = {
	.map_io = at91sam9g45_map_io,
	.default_irq_priority = at91sam9g45_default_irq_priority,
	.register_clocks = at91sam9g45_register_clocks,
	.init = at91sam9g45_initialize,
};
Commit	Line	Data
789b23bc NF	1	/*
	2	* Chip-specific setup code for the AT91SAM9G45 family
	3	*
	4	* Copyright (C) 2009 Atmel Corporation.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	*/
	12
	13	#include <linux/module.h>
	14	#include <linux/pm.h>
f407c2e3	15	#include <linux/dma-mapping.h>
789b23bc NF	16
	17	#include <asm/irq.h>
	18	#include <asm/mach/arch.h>
	19	#include <asm/mach/map.h>
	20	#include <mach/at91sam9g45.h>
	21	#include <mach/at91_pmc.h>
	22	#include <mach/at91_rstc.h>
	23	#include <mach/at91_shdwc.h>
5f9f0a41	24	#include <mach/cpu.h>
789b23bc	25
21d08b9d	26	#include "soc.h"
789b23bc NF	27	#include "generic.h"
	28	#include "clock.h"
	29
789b23bc NF	30	/* --------------------------------------------------------------------
	31	* Clocks
	32	* -------------------------------------------------------------------- */
	33
	34	/*
	35	* The peripheral clocks.
	36	*/
	37	static struct clk pioA_clk = {
	38	.name = "pioA_clk",
	39	.pmc_mask = 1 << AT91SAM9G45_ID_PIOA,
	40	.type = CLK_TYPE_PERIPHERAL,
	41	};
	42	static struct clk pioB_clk = {
	43	.name = "pioB_clk",
	44	.pmc_mask = 1 << AT91SAM9G45_ID_PIOB,
	45	.type = CLK_TYPE_PERIPHERAL,
	46	};
	47	static struct clk pioC_clk = {
	48	.name = "pioC_clk",
	49	.pmc_mask = 1 << AT91SAM9G45_ID_PIOC,
	50	.type = CLK_TYPE_PERIPHERAL,
	51	};
	52	static struct clk pioDE_clk = {
	53	.name = "pioDE_clk",
	54	.pmc_mask = 1 << AT91SAM9G45_ID_PIODE,
	55	.type = CLK_TYPE_PERIPHERAL,
	56	};
237a62a1 PK	57	static struct clk trng_clk = {
	58	.name = "trng_clk",
	59	.pmc_mask = 1 << AT91SAM9G45_ID_TRNG,
	60	.type = CLK_TYPE_PERIPHERAL,
	61	};
789b23bc NF	62	static struct clk usart0_clk = {
	63	.name = "usart0_clk",
	64	.pmc_mask = 1 << AT91SAM9G45_ID_US0,
	65	.type = CLK_TYPE_PERIPHERAL,
	66	};
	67	static struct clk usart1_clk = {
	68	.name = "usart1_clk",
	69	.pmc_mask = 1 << AT91SAM9G45_ID_US1,
	70	.type = CLK_TYPE_PERIPHERAL,
	71	};
	72	static struct clk usart2_clk = {
	73	.name = "usart2_clk",
	74	.pmc_mask = 1 << AT91SAM9G45_ID_US2,
	75	.type = CLK_TYPE_PERIPHERAL,
	76	};
	77	static struct clk usart3_clk = {
	78	.name = "usart3_clk",
	79	.pmc_mask = 1 << AT91SAM9G45_ID_US3,
	80	.type = CLK_TYPE_PERIPHERAL,
	81	};
	82	static struct clk mmc0_clk = {
	83	.name = "mci0_clk",
	84	.pmc_mask = 1 << AT91SAM9G45_ID_MCI0,
	85	.type = CLK_TYPE_PERIPHERAL,
	86	};
	87	static struct clk twi0_clk = {
	88	.name = "twi0_clk",
	89	.pmc_mask = 1 << AT91SAM9G45_ID_TWI0,
	90	.type = CLK_TYPE_PERIPHERAL,
	91	};
	92	static struct clk twi1_clk = {
	93	.name = "twi1_clk",
	94	.pmc_mask = 1 << AT91SAM9G45_ID_TWI1,
	95	.type = CLK_TYPE_PERIPHERAL,
	96	};
	97	static struct clk spi0_clk = {
	98	.name = "spi0_clk",
	99	.pmc_mask = 1 << AT91SAM9G45_ID_SPI0,
	100	.type = CLK_TYPE_PERIPHERAL,
	101	};
	102	static struct clk spi1_clk = {
	103	.name = "spi1_clk",
	104	.pmc_mask = 1 << AT91SAM9G45_ID_SPI1,
	105	.type = CLK_TYPE_PERIPHERAL,
	106	};
	107	static struct clk ssc0_clk = {
	108	.name = "ssc0_clk",
	109	.pmc_mask = 1 << AT91SAM9G45_ID_SSC0,
	110	.type = CLK_TYPE_PERIPHERAL,
	111	};
	112	static struct clk ssc1_clk = {
	113	.name = "ssc1_clk",
	114	.pmc_mask = 1 << AT91SAM9G45_ID_SSC1,
	115	.type = CLK_TYPE_PERIPHERAL,
	116	};
ab64511c FG	117	static struct clk tcb0_clk = {
ab64511c FG	118	.name = "tcb0_clk",
789b23bc NF	119	.pmc_mask = 1 << AT91SAM9G45_ID_TCB,
	120	.type = CLK_TYPE_PERIPHERAL,
	121	};
	122	static struct clk pwm_clk = {
	123	.name = "pwm_clk",
	124	.pmc_mask = 1 << AT91SAM9G45_ID_PWMC,
	125	.type = CLK_TYPE_PERIPHERAL,
	126	};
	127	static struct clk tsc_clk = {
	128	.name = "tsc_clk",
	129	.pmc_mask = 1 << AT91SAM9G45_ID_TSC,
	130	.type = CLK_TYPE_PERIPHERAL,
	131	};
	132	static struct clk dma_clk = {
	133	.name = "dma_clk",
	134	.pmc_mask = 1 << AT91SAM9G45_ID_DMA,
	135	.type = CLK_TYPE_PERIPHERAL,
	136	};
	137	static struct clk uhphs_clk = {
	138	.name = "uhphs_clk",
	139	.pmc_mask = 1 << AT91SAM9G45_ID_UHPHS,
	140	.type = CLK_TYPE_PERIPHERAL,
	141	};
	142	static struct clk lcdc_clk = {
	143	.name = "lcdc_clk",
	144	.pmc_mask = 1 << AT91SAM9G45_ID_LCDC,
	145	.type = CLK_TYPE_PERIPHERAL,
	146	};
	147	static struct clk ac97_clk = {
	148	.name = "ac97_clk",
	149	.pmc_mask = 1 << AT91SAM9G45_ID_AC97C,
	150	.type = CLK_TYPE_PERIPHERAL,
	151	};
	152	static struct clk macb_clk = {
	153	.name = "macb_clk",
	154	.pmc_mask = 1 << AT91SAM9G45_ID_EMAC,
	155	.type = CLK_TYPE_PERIPHERAL,
	156	};
	157	static struct clk isi_clk = {
	158	.name = "isi_clk",
	159	.pmc_mask = 1 << AT91SAM9G45_ID_ISI,
	160	.type = CLK_TYPE_PERIPHERAL,
	161	};
	162	static struct clk udphs_clk = {
	163	.name = "udphs_clk",
	164	.pmc_mask = 1 << AT91SAM9G45_ID_UDPHS,
	165	.type = CLK_TYPE_PERIPHERAL,
	166	};
	167	static struct clk mmc1_clk = {
	168	.name = "mci1_clk",
	169	.pmc_mask = 1 << AT91SAM9G45_ID_MCI1,
	170	.type = CLK_TYPE_PERIPHERAL,
	171	};
	172
5f9f0a41 NF	173	/* Video decoder clock - Only for sam9m10/sam9m11 */
	174	static struct clk vdec_clk = {
	175	.name = "vdec_clk",
	176	.pmc_mask = 1 << AT91SAM9G45_ID_VDEC,
	177	.type = CLK_TYPE_PERIPHERAL,
	178	};
	179
789b23bc NF	180	static struct clk *periph_clocks[] __initdata = {
	181	&pioA_clk,
	182	&pioB_clk,
	183	&pioC_clk,
	184	&pioDE_clk,
237a62a1	185	&trng_clk,
789b23bc NF	186	&usart0_clk,
	187	&usart1_clk,
	188	&usart2_clk,
	189	&usart3_clk,
	190	&mmc0_clk,
	191	&twi0_clk,
	192	&twi1_clk,
	193	&spi0_clk,
	194	&spi1_clk,
	195	&ssc0_clk,
	196	&ssc1_clk,
ab64511c	197	&tcb0_clk,
789b23bc NF	198	&pwm_clk,
	199	&tsc_clk,
	200	&dma_clk,
	201	&uhphs_clk,
	202	&lcdc_clk,
	203	&ac97_clk,
	204	&macb_clk,
	205	&isi_clk,
	206	&udphs_clk,
	207	&mmc1_clk,
	208	// irq0
bd602995 JCPV	209	};
	210
	211	static struct clk_lookup periph_clocks_lookups[] = {
	212	/* One additional fake clock for ohci */
	213	CLKDEV_CON_ID("ohci_clk", &uhphs_clk),
9d87159e JCPV	214	CLKDEV_CON_DEV_ID("ehci_clk", "atmel-ehci", &uhphs_clk),
	215	CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
	216	CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
	217	CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.0", &mmc0_clk),
	218	CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.1", &mmc1_clk),
bd602995 JCPV	219	CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
	220	CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
	221	CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb0_clk),
	222	CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tcb0_clk),
	223	CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
	224	CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
237a62a1	225	CLKDEV_CON_DEV_ID(NULL, "atmel-trng", &trng_clk),
49fe2ba3 NF	226	/* more usart lookup table for DT entries */
	227	CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck),
	228	CLKDEV_CON_DEV_ID("usart", "fff8c000.serial", &usart0_clk),
	229	CLKDEV_CON_DEV_ID("usart", "fff90000.serial", &usart1_clk),
	230	CLKDEV_CON_DEV_ID("usart", "fff94000.serial", &usart2_clk),
	231	CLKDEV_CON_DEV_ID("usart", "fff98000.serial", &usart3_clk),
0af4316b JCPV	232	/* fake hclk clock */
0af4316b JCPV	233	CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk),
bd602995 JCPV	234	};
	235
	236	static struct clk_lookup usart_clocks_lookups[] = {
	237	CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
	238	CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
	239	CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
	240	CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
	241	CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
789b23bc NF	242	};
	243
	244	/*
	245	* The two programmable clocks.
	246	* You must configure pin multiplexing to bring these signals out.
	247	*/
	248	static struct clk pck0 = {
	249	.name = "pck0",
	250	.pmc_mask = AT91_PMC_PCK0,
	251	.type = CLK_TYPE_PROGRAMMABLE,
	252	.id = 0,
	253	};
	254	static struct clk pck1 = {
	255	.name = "pck1",
	256	.pmc_mask = AT91_PMC_PCK1,
	257	.type = CLK_TYPE_PROGRAMMABLE,
	258	.id = 1,
	259	};
	260
	261	static void __init at91sam9g45_register_clocks(void)
	262	{
	263	int i;
	264
	265	for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
	266	clk_register(periph_clocks[i]);
	267
bd602995 JCPV	268	clkdev_add_table(periph_clocks_lookups,
	269	ARRAY_SIZE(periph_clocks_lookups));
	270	clkdev_add_table(usart_clocks_lookups,
	271	ARRAY_SIZE(usart_clocks_lookups));
	272
5f9f0a41 NF	273	if (cpu_is_at91sam9m10() \|\| cpu_is_at91sam9m11())
	274	clk_register(&vdec_clk);
	275
789b23bc NF	276	clk_register(&pck0);
	277	clk_register(&pck1);
	278	}
	279
bd602995 JCPV	280	static struct clk_lookup console_clock_lookup;
	281
	282	void __init at91sam9g45_set_console_clock(int id)
	283	{
	284	if (id >= ARRAY_SIZE(usart_clocks_lookups))
	285	return;
	286
	287	console_clock_lookup.con_id = "usart";
	288	console_clock_lookup.clk = usart_clocks_lookups[id].clk;
	289	clkdev_add(&console_clock_lookup);
	290	}
	291
789b23bc NF	292	/* --------------------------------------------------------------------
	293	* GPIO
	294	* -------------------------------------------------------------------- */
	295
	296	static struct at91_gpio_bank at91sam9g45_gpio[] = {
	297	{
	298	.id = AT91SAM9G45_ID_PIOA,
80e91cb8	299	.regbase = AT91SAM9G45_BASE_PIOA,
789b23bc NF	300	.clock = &pioA_clk,
	301	}, {
	302	.id = AT91SAM9G45_ID_PIOB,
80e91cb8	303	.regbase = AT91SAM9G45_BASE_PIOB,
789b23bc NF	304	.clock = &pioB_clk,
	305	}, {
	306	.id = AT91SAM9G45_ID_PIOC,
80e91cb8	307	.regbase = AT91SAM9G45_BASE_PIOC,
789b23bc NF	308	.clock = &pioC_clk,
	309	}, {
	310	.id = AT91SAM9G45_ID_PIODE,
80e91cb8	311	.regbase = AT91SAM9G45_BASE_PIOD,
789b23bc NF	312	.clock = &pioDE_clk,
	313	}, {
	314	.id = AT91SAM9G45_ID_PIODE,
80e91cb8	315	.regbase = AT91SAM9G45_BASE_PIOE,
789b23bc NF	316	.clock = &pioDE_clk,
	317	}
	318	};
	319
	320	static void at91sam9g45_reset(void)
	321	{
	322	at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY \| AT91_RSTC_PROCRST \| AT91_RSTC_PERRST);
	323	}
	324
	325	static void at91sam9g45_poweroff(void)
	326	{
	327	at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY \| AT91_SHDW_SHDW);
	328	}
	329
	330
	331	/* --------------------------------------------------------------------
	332	* AT91SAM9G45 processor initialization
	333	* -------------------------------------------------------------------- */
	334
21d08b9d	335	static void __init at91sam9g45_map_io(void)
789b23bc	336	{
f0051d82	337	at91_init_sram(0, AT91SAM9G45_SRAM_BASE, AT91SAM9G45_SRAM_SIZE);
f407c2e3	338	init_consistent_dma_size(SZ_4M);
1b021a3b	339	}
789b23bc	340
46539374	341	static void __init at91sam9g45_initialize(void)
1b021a3b	342	{
789b23bc NF	343	at91_arch_reset = at91sam9g45_reset;
	344	pm_power_off = at91sam9g45_poweroff;
	345	at91_extern_irq = (1 << AT91SAM9G45_ID_IRQ0);
	346
789b23bc NF	347	/* Register GPIO subsystem */
	348	at91_gpio_init(at91sam9g45_gpio, 5);
	349	}
	350
	351	/* --------------------------------------------------------------------
	352	* Interrupt initialization
	353	* -------------------------------------------------------------------- */
	354
	355	/*
	356	* The default interrupt priority levels (0 = lowest, 7 = highest).
	357	*/
	358	static unsigned int at91sam9g45_default_irq_priority[NR_AIC_IRQS] __initdata = {
	359	7, /* Advanced Interrupt Controller (FIQ) */
	360	7, /* System Peripherals */
	361	1, /* Parallel IO Controller A */
	362	1, /* Parallel IO Controller B */
	363	1, /* Parallel IO Controller C */
	364	1, /* Parallel IO Controller D and E */
	365	0,
	366	5, /* USART 0 */
	367	5, /* USART 1 */
	368	5, /* USART 2 */
	369	5, /* USART 3 */
	370	0, /* Multimedia Card Interface 0 */
	371	6, /* Two-Wire Interface 0 */
	372	6, /* Two-Wire Interface 1 */
	373	5, /* Serial Peripheral Interface 0 */
	374	5, /* Serial Peripheral Interface 1 */
	375	4, /* Serial Synchronous Controller 0 */
	376	4, /* Serial Synchronous Controller 1 */
	377	0, /* Timer Counter 0, 1, 2, 3, 4 and 5 */
	378	0, /* Pulse Width Modulation Controller */
	379	0, /* Touch Screen Controller */
	380	0, /* DMA Controller */
	381	2, /* USB Host High Speed port */
	382	3, /* LDC Controller */
	383	5, /* AC97 Controller */
	384	3, /* Ethernet */
	385	0, /* Image Sensor Interface */
	386	2, /* USB Device High speed port */
	387	0,
	388	0, /* Multimedia Card Interface 1 */
	389	0,
	390	0, /* Advanced Interrupt Controller (IRQ0) */
	391	};
	392
8c3583b6	393	struct at91_init_soc __initdata at91sam9g45_soc = {
21d08b9d	394	.map_io = at91sam9g45_map_io,
92100c12	395	.default_irq_priority = at91sam9g45_default_irq_priority,
51ddec76	396	.register_clocks = at91sam9g45_register_clocks,
21d08b9d JCPV	397	.init = at91sam9g45_initialize,
21d08b9d JCPV	398	};