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789b23bc NF |
1 | /* |
2 | * On-Chip devices setup code for the AT91SAM9G45 family | |
3 | * | |
4 | * Copyright (C) 2009 Atmel Corporation. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | */ | |
12 | #include <asm/mach/arch.h> | |
13 | #include <asm/mach/map.h> | |
14 | ||
15 | #include <linux/dma-mapping.h> | |
2f8163ba | 16 | #include <linux/gpio.h> |
343754f5 | 17 | #include <linux/clk.h> |
789b23bc NF |
18 | #include <linux/platform_device.h> |
19 | #include <linux/i2c-gpio.h> | |
75305d76 | 20 | #include <linux/atmel-mci.h> |
789b23bc NF |
21 | |
22 | #include <linux/fb.h> | |
23 | #include <video/atmel_lcdc.h> | |
24 | ||
25 | #include <mach/board.h> | |
789b23bc NF |
26 | #include <mach/at91sam9g45.h> |
27 | #include <mach/at91sam9g45_matrix.h> | |
4342d647 | 28 | #include <mach/at91_matrix.h> |
789b23bc | 29 | #include <mach/at91sam9_smc.h> |
40262b2b | 30 | #include <mach/at_hdmac.h> |
75305d76 | 31 | #include <mach/atmel-mci.h> |
789b23bc | 32 | |
343754f5 JW |
33 | #include <media/atmel-isi.h> |
34 | ||
789b23bc | 35 | #include "generic.h" |
343754f5 | 36 | #include "clock.h" |
789b23bc NF |
37 | |
38 | ||
40262b2b NF |
39 | /* -------------------------------------------------------------------- |
40 | * HDMAC - AHB DMA Controller | |
41 | * -------------------------------------------------------------------- */ | |
42 | ||
43 | #if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE) | |
44 | static u64 hdmac_dmamask = DMA_BIT_MASK(32); | |
45 | ||
40262b2b NF |
46 | static struct resource hdmac_resources[] = { |
47 | [0] = { | |
9627b200 JCPV |
48 | .start = AT91SAM9G45_BASE_DMA, |
49 | .end = AT91SAM9G45_BASE_DMA + SZ_512 - 1, | |
40262b2b NF |
50 | .flags = IORESOURCE_MEM, |
51 | }, | |
8d2602e0 | 52 | [1] = { |
40262b2b NF |
53 | .start = AT91SAM9G45_ID_DMA, |
54 | .end = AT91SAM9G45_ID_DMA, | |
55 | .flags = IORESOURCE_IRQ, | |
56 | }, | |
57 | }; | |
58 | ||
59 | static struct platform_device at_hdmac_device = { | |
bdad0b9a | 60 | .name = "at91sam9g45_dma", |
40262b2b NF |
61 | .id = -1, |
62 | .dev = { | |
63 | .dma_mask = &hdmac_dmamask, | |
64 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
40262b2b NF |
65 | }, |
66 | .resource = hdmac_resources, | |
67 | .num_resources = ARRAY_SIZE(hdmac_resources), | |
68 | }; | |
69 | ||
70 | void __init at91_add_device_hdmac(void) | |
71 | { | |
2756bf5c NF |
72 | #if defined(CONFIG_OF) |
73 | struct device_node *of_node = | |
74 | of_find_node_by_name(NULL, "dma-controller"); | |
75 | ||
76 | if (of_node) | |
77 | of_node_put(of_node); | |
78 | else | |
79 | #endif | |
80 | platform_device_register(&at_hdmac_device); | |
40262b2b NF |
81 | } |
82 | #else | |
83 | void __init at91_add_device_hdmac(void) {} | |
84 | #endif | |
85 | ||
86 | ||
789b23bc NF |
87 | /* -------------------------------------------------------------------- |
88 | * USB Host (OHCI) | |
89 | * -------------------------------------------------------------------- */ | |
90 | ||
91 | #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) | |
92 | static u64 ohci_dmamask = DMA_BIT_MASK(32); | |
93 | static struct at91_usbh_data usbh_ohci_data; | |
94 | ||
95 | static struct resource usbh_ohci_resources[] = { | |
96 | [0] = { | |
97 | .start = AT91SAM9G45_OHCI_BASE, | |
98 | .end = AT91SAM9G45_OHCI_BASE + SZ_1M - 1, | |
99 | .flags = IORESOURCE_MEM, | |
100 | }, | |
101 | [1] = { | |
102 | .start = AT91SAM9G45_ID_UHPHS, | |
103 | .end = AT91SAM9G45_ID_UHPHS, | |
104 | .flags = IORESOURCE_IRQ, | |
105 | }, | |
106 | }; | |
107 | ||
108 | static struct platform_device at91_usbh_ohci_device = { | |
109 | .name = "at91_ohci", | |
110 | .id = -1, | |
111 | .dev = { | |
112 | .dma_mask = &ohci_dmamask, | |
113 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
114 | .platform_data = &usbh_ohci_data, | |
115 | }, | |
116 | .resource = usbh_ohci_resources, | |
117 | .num_resources = ARRAY_SIZE(usbh_ohci_resources), | |
118 | }; | |
119 | ||
120 | void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) | |
121 | { | |
122 | int i; | |
123 | ||
124 | if (!data) | |
125 | return; | |
126 | ||
127 | /* Enable VBus control for UHP ports */ | |
128 | for (i = 0; i < data->ports; i++) { | |
cc9f9aef | 129 | if (gpio_is_valid(data->vbus_pin[i])) |
789b23bc NF |
130 | at91_set_gpio_output(data->vbus_pin[i], 0); |
131 | } | |
132 | ||
1fcaea7e TP |
133 | /* Enable overcurrent notification */ |
134 | for (i = 0; i < data->ports; i++) { | |
135 | if (data->overcurrent_pin[i]) | |
136 | at91_set_gpio_input(data->overcurrent_pin[i], 1); | |
137 | } | |
138 | ||
789b23bc NF |
139 | usbh_ohci_data = *data; |
140 | platform_device_register(&at91_usbh_ohci_device); | |
141 | } | |
142 | #else | |
143 | void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) {} | |
144 | #endif | |
145 | ||
146 | ||
f51f78c0 NF |
147 | /* -------------------------------------------------------------------- |
148 | * USB Host HS (EHCI) | |
149 | * Needs an OHCI host for low and full speed management | |
150 | * -------------------------------------------------------------------- */ | |
151 | ||
152 | #if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_EHCI_HCD_MODULE) | |
153 | static u64 ehci_dmamask = DMA_BIT_MASK(32); | |
154 | static struct at91_usbh_data usbh_ehci_data; | |
155 | ||
156 | static struct resource usbh_ehci_resources[] = { | |
157 | [0] = { | |
158 | .start = AT91SAM9G45_EHCI_BASE, | |
159 | .end = AT91SAM9G45_EHCI_BASE + SZ_1M - 1, | |
160 | .flags = IORESOURCE_MEM, | |
161 | }, | |
162 | [1] = { | |
163 | .start = AT91SAM9G45_ID_UHPHS, | |
164 | .end = AT91SAM9G45_ID_UHPHS, | |
165 | .flags = IORESOURCE_IRQ, | |
166 | }, | |
167 | }; | |
168 | ||
169 | static struct platform_device at91_usbh_ehci_device = { | |
170 | .name = "atmel-ehci", | |
171 | .id = -1, | |
172 | .dev = { | |
173 | .dma_mask = &ehci_dmamask, | |
174 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
175 | .platform_data = &usbh_ehci_data, | |
176 | }, | |
177 | .resource = usbh_ehci_resources, | |
178 | .num_resources = ARRAY_SIZE(usbh_ehci_resources), | |
179 | }; | |
180 | ||
181 | void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data) | |
182 | { | |
183 | int i; | |
184 | ||
185 | if (!data) | |
186 | return; | |
187 | ||
188 | /* Enable VBus control for UHP ports */ | |
189 | for (i = 0; i < data->ports; i++) { | |
cc9f9aef | 190 | if (gpio_is_valid(data->vbus_pin[i])) |
f51f78c0 NF |
191 | at91_set_gpio_output(data->vbus_pin[i], 0); |
192 | } | |
193 | ||
194 | usbh_ehci_data = *data; | |
f51f78c0 NF |
195 | platform_device_register(&at91_usbh_ehci_device); |
196 | } | |
197 | #else | |
198 | void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data) {} | |
199 | #endif | |
200 | ||
201 | ||
789b23bc NF |
202 | /* -------------------------------------------------------------------- |
203 | * USB HS Device (Gadget) | |
204 | * -------------------------------------------------------------------- */ | |
205 | ||
dd0b3825 | 206 | #if defined(CONFIG_USB_ATMEL_USBA) || defined(CONFIG_USB_ATMEL_USBA_MODULE) |
789b23bc NF |
207 | static struct resource usba_udc_resources[] = { |
208 | [0] = { | |
209 | .start = AT91SAM9G45_UDPHS_FIFO, | |
210 | .end = AT91SAM9G45_UDPHS_FIFO + SZ_512K - 1, | |
211 | .flags = IORESOURCE_MEM, | |
212 | }, | |
213 | [1] = { | |
214 | .start = AT91SAM9G45_BASE_UDPHS, | |
215 | .end = AT91SAM9G45_BASE_UDPHS + SZ_1K - 1, | |
216 | .flags = IORESOURCE_MEM, | |
217 | }, | |
218 | [2] = { | |
219 | .start = AT91SAM9G45_ID_UDPHS, | |
220 | .end = AT91SAM9G45_ID_UDPHS, | |
221 | .flags = IORESOURCE_IRQ, | |
222 | }, | |
223 | }; | |
224 | ||
225 | #define EP(nam, idx, maxpkt, maxbk, dma, isoc) \ | |
226 | [idx] = { \ | |
227 | .name = nam, \ | |
228 | .index = idx, \ | |
229 | .fifo_size = maxpkt, \ | |
230 | .nr_banks = maxbk, \ | |
231 | .can_dma = dma, \ | |
232 | .can_isoc = isoc, \ | |
233 | } | |
234 | ||
235 | static struct usba_ep_data usba_udc_ep[] __initdata = { | |
236 | EP("ep0", 0, 64, 1, 0, 0), | |
237 | EP("ep1", 1, 1024, 2, 1, 1), | |
238 | EP("ep2", 2, 1024, 2, 1, 1), | |
239 | EP("ep3", 3, 1024, 3, 1, 0), | |
240 | EP("ep4", 4, 1024, 3, 1, 0), | |
241 | EP("ep5", 5, 1024, 3, 1, 1), | |
242 | EP("ep6", 6, 1024, 3, 1, 1), | |
243 | }; | |
244 | ||
245 | #undef EP | |
246 | ||
247 | /* | |
248 | * pdata doesn't have room for any endpoints, so we need to | |
249 | * append room for the ones we need right after it. | |
250 | */ | |
251 | static struct { | |
252 | struct usba_platform_data pdata; | |
253 | struct usba_ep_data ep[7]; | |
254 | } usba_udc_data; | |
255 | ||
256 | static struct platform_device at91_usba_udc_device = { | |
257 | .name = "atmel_usba_udc", | |
258 | .id = -1, | |
259 | .dev = { | |
260 | .platform_data = &usba_udc_data.pdata, | |
261 | }, | |
262 | .resource = usba_udc_resources, | |
263 | .num_resources = ARRAY_SIZE(usba_udc_resources), | |
264 | }; | |
265 | ||
266 | void __init at91_add_device_usba(struct usba_platform_data *data) | |
267 | { | |
268 | usba_udc_data.pdata.vbus_pin = -EINVAL; | |
269 | usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep); | |
6eab04a8 | 270 | memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep)); |
789b23bc | 271 | |
cc9f9aef | 272 | if (data && gpio_is_valid(data->vbus_pin)) { |
789b23bc NF |
273 | at91_set_gpio_input(data->vbus_pin, 0); |
274 | at91_set_deglitch(data->vbus_pin, 1); | |
275 | usba_udc_data.pdata.vbus_pin = data->vbus_pin; | |
276 | } | |
277 | ||
278 | /* Pullup pin is handled internally by USB device peripheral */ | |
279 | ||
789b23bc NF |
280 | platform_device_register(&at91_usba_udc_device); |
281 | } | |
282 | #else | |
283 | void __init at91_add_device_usba(struct usba_platform_data *data) {} | |
284 | #endif | |
285 | ||
286 | ||
287 | /* -------------------------------------------------------------------- | |
288 | * Ethernet | |
289 | * -------------------------------------------------------------------- */ | |
290 | ||
291 | #if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE) | |
292 | static u64 eth_dmamask = DMA_BIT_MASK(32); | |
84e0cdb0 | 293 | static struct macb_platform_data eth_data; |
789b23bc NF |
294 | |
295 | static struct resource eth_resources[] = { | |
296 | [0] = { | |
297 | .start = AT91SAM9G45_BASE_EMAC, | |
298 | .end = AT91SAM9G45_BASE_EMAC + SZ_16K - 1, | |
299 | .flags = IORESOURCE_MEM, | |
300 | }, | |
301 | [1] = { | |
302 | .start = AT91SAM9G45_ID_EMAC, | |
303 | .end = AT91SAM9G45_ID_EMAC, | |
304 | .flags = IORESOURCE_IRQ, | |
305 | }, | |
306 | }; | |
307 | ||
308 | static struct platform_device at91sam9g45_eth_device = { | |
309 | .name = "macb", | |
310 | .id = -1, | |
311 | .dev = { | |
312 | .dma_mask = ð_dmamask, | |
313 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
314 | .platform_data = ð_data, | |
315 | }, | |
316 | .resource = eth_resources, | |
317 | .num_resources = ARRAY_SIZE(eth_resources), | |
318 | }; | |
319 | ||
84e0cdb0 | 320 | void __init at91_add_device_eth(struct macb_platform_data *data) |
789b23bc NF |
321 | { |
322 | if (!data) | |
323 | return; | |
324 | ||
cc9f9aef | 325 | if (gpio_is_valid(data->phy_irq_pin)) { |
789b23bc NF |
326 | at91_set_gpio_input(data->phy_irq_pin, 0); |
327 | at91_set_deglitch(data->phy_irq_pin, 1); | |
328 | } | |
329 | ||
330 | /* Pins used for MII and RMII */ | |
331 | at91_set_A_periph(AT91_PIN_PA17, 0); /* ETXCK_EREFCK */ | |
332 | at91_set_A_periph(AT91_PIN_PA15, 0); /* ERXDV */ | |
333 | at91_set_A_periph(AT91_PIN_PA12, 0); /* ERX0 */ | |
334 | at91_set_A_periph(AT91_PIN_PA13, 0); /* ERX1 */ | |
335 | at91_set_A_periph(AT91_PIN_PA16, 0); /* ERXER */ | |
336 | at91_set_A_periph(AT91_PIN_PA14, 0); /* ETXEN */ | |
337 | at91_set_A_periph(AT91_PIN_PA10, 0); /* ETX0 */ | |
338 | at91_set_A_periph(AT91_PIN_PA11, 0); /* ETX1 */ | |
339 | at91_set_A_periph(AT91_PIN_PA19, 0); /* EMDIO */ | |
340 | at91_set_A_periph(AT91_PIN_PA18, 0); /* EMDC */ | |
341 | ||
342 | if (!data->is_rmii) { | |
343 | at91_set_B_periph(AT91_PIN_PA29, 0); /* ECRS */ | |
344 | at91_set_B_periph(AT91_PIN_PA30, 0); /* ECOL */ | |
345 | at91_set_B_periph(AT91_PIN_PA8, 0); /* ERX2 */ | |
346 | at91_set_B_periph(AT91_PIN_PA9, 0); /* ERX3 */ | |
347 | at91_set_B_periph(AT91_PIN_PA28, 0); /* ERXCK */ | |
348 | at91_set_B_periph(AT91_PIN_PA6, 0); /* ETX2 */ | |
349 | at91_set_B_periph(AT91_PIN_PA7, 0); /* ETX3 */ | |
350 | at91_set_B_periph(AT91_PIN_PA27, 0); /* ETXER */ | |
351 | } | |
352 | ||
353 | eth_data = *data; | |
354 | platform_device_register(&at91sam9g45_eth_device); | |
355 | } | |
356 | #else | |
84e0cdb0 | 357 | void __init at91_add_device_eth(struct macb_platform_data *data) {} |
789b23bc NF |
358 | #endif |
359 | ||
360 | ||
75305d76 NF |
361 | /* -------------------------------------------------------------------- |
362 | * MMC / SD | |
363 | * -------------------------------------------------------------------- */ | |
364 | ||
365 | #if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE) | |
366 | static u64 mmc_dmamask = DMA_BIT_MASK(32); | |
367 | static struct mci_platform_data mmc0_data, mmc1_data; | |
368 | ||
369 | static struct resource mmc0_resources[] = { | |
370 | [0] = { | |
371 | .start = AT91SAM9G45_BASE_MCI0, | |
372 | .end = AT91SAM9G45_BASE_MCI0 + SZ_16K - 1, | |
373 | .flags = IORESOURCE_MEM, | |
374 | }, | |
375 | [1] = { | |
376 | .start = AT91SAM9G45_ID_MCI0, | |
377 | .end = AT91SAM9G45_ID_MCI0, | |
378 | .flags = IORESOURCE_IRQ, | |
379 | }, | |
380 | }; | |
381 | ||
382 | static struct platform_device at91sam9g45_mmc0_device = { | |
383 | .name = "atmel_mci", | |
384 | .id = 0, | |
385 | .dev = { | |
386 | .dma_mask = &mmc_dmamask, | |
387 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
388 | .platform_data = &mmc0_data, | |
389 | }, | |
390 | .resource = mmc0_resources, | |
391 | .num_resources = ARRAY_SIZE(mmc0_resources), | |
392 | }; | |
393 | ||
394 | static struct resource mmc1_resources[] = { | |
395 | [0] = { | |
396 | .start = AT91SAM9G45_BASE_MCI1, | |
397 | .end = AT91SAM9G45_BASE_MCI1 + SZ_16K - 1, | |
398 | .flags = IORESOURCE_MEM, | |
399 | }, | |
400 | [1] = { | |
401 | .start = AT91SAM9G45_ID_MCI1, | |
402 | .end = AT91SAM9G45_ID_MCI1, | |
403 | .flags = IORESOURCE_IRQ, | |
404 | }, | |
405 | }; | |
406 | ||
407 | static struct platform_device at91sam9g45_mmc1_device = { | |
408 | .name = "atmel_mci", | |
409 | .id = 1, | |
410 | .dev = { | |
411 | .dma_mask = &mmc_dmamask, | |
412 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
413 | .platform_data = &mmc1_data, | |
414 | }, | |
415 | .resource = mmc1_resources, | |
416 | .num_resources = ARRAY_SIZE(mmc1_resources), | |
417 | }; | |
418 | ||
419 | /* Consider only one slot : slot 0 */ | |
420 | void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data) | |
421 | { | |
422 | ||
423 | if (!data) | |
424 | return; | |
425 | ||
426 | /* Must have at least one usable slot */ | |
427 | if (!data->slot[0].bus_width) | |
428 | return; | |
429 | ||
430 | #if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE) | |
431 | { | |
432 | struct at_dma_slave *atslave; | |
433 | struct mci_dma_data *alt_atslave; | |
434 | ||
435 | alt_atslave = kzalloc(sizeof(struct mci_dma_data), GFP_KERNEL); | |
436 | atslave = &alt_atslave->sdata; | |
437 | ||
438 | /* DMA slave channel configuration */ | |
439 | atslave->dma_dev = &at_hdmac_device.dev; | |
440 | atslave->reg_width = AT_DMA_SLAVE_WIDTH_32BIT; | |
441 | atslave->cfg = ATC_FIFOCFG_HALFFIFO | |
442 | | ATC_SRC_H2SEL_HW | ATC_DST_H2SEL_HW; | |
443 | atslave->ctrla = ATC_SCSIZE_16 | ATC_DCSIZE_16; | |
444 | if (mmc_id == 0) /* MCI0 */ | |
445 | atslave->cfg |= ATC_SRC_PER(AT_DMA_ID_MCI0) | |
446 | | ATC_DST_PER(AT_DMA_ID_MCI0); | |
447 | ||
448 | else /* MCI1 */ | |
449 | atslave->cfg |= ATC_SRC_PER(AT_DMA_ID_MCI1) | |
450 | | ATC_DST_PER(AT_DMA_ID_MCI1); | |
451 | ||
452 | data->dma_slave = alt_atslave; | |
453 | } | |
454 | #endif | |
455 | ||
456 | ||
457 | /* input/irq */ | |
cc9f9aef | 458 | if (gpio_is_valid(data->slot[0].detect_pin)) { |
75305d76 NF |
459 | at91_set_gpio_input(data->slot[0].detect_pin, 1); |
460 | at91_set_deglitch(data->slot[0].detect_pin, 1); | |
461 | } | |
cc9f9aef | 462 | if (gpio_is_valid(data->slot[0].wp_pin)) |
75305d76 NF |
463 | at91_set_gpio_input(data->slot[0].wp_pin, 1); |
464 | ||
465 | if (mmc_id == 0) { /* MCI0 */ | |
466 | ||
467 | /* CLK */ | |
468 | at91_set_A_periph(AT91_PIN_PA0, 0); | |
469 | ||
470 | /* CMD */ | |
471 | at91_set_A_periph(AT91_PIN_PA1, 1); | |
472 | ||
473 | /* DAT0, maybe DAT1..DAT3 and maybe DAT4..DAT7 */ | |
474 | at91_set_A_periph(AT91_PIN_PA2, 1); | |
475 | if (data->slot[0].bus_width == 4) { | |
476 | at91_set_A_periph(AT91_PIN_PA3, 1); | |
477 | at91_set_A_periph(AT91_PIN_PA4, 1); | |
478 | at91_set_A_periph(AT91_PIN_PA5, 1); | |
479 | if (data->slot[0].bus_width == 8) { | |
480 | at91_set_A_periph(AT91_PIN_PA6, 1); | |
481 | at91_set_A_periph(AT91_PIN_PA7, 1); | |
482 | at91_set_A_periph(AT91_PIN_PA8, 1); | |
483 | at91_set_A_periph(AT91_PIN_PA9, 1); | |
484 | } | |
485 | } | |
486 | ||
487 | mmc0_data = *data; | |
75305d76 NF |
488 | platform_device_register(&at91sam9g45_mmc0_device); |
489 | ||
490 | } else { /* MCI1 */ | |
491 | ||
492 | /* CLK */ | |
493 | at91_set_A_periph(AT91_PIN_PA31, 0); | |
494 | ||
495 | /* CMD */ | |
496 | at91_set_A_periph(AT91_PIN_PA22, 1); | |
497 | ||
498 | /* DAT0, maybe DAT1..DAT3 and maybe DAT4..DAT7 */ | |
499 | at91_set_A_periph(AT91_PIN_PA23, 1); | |
500 | if (data->slot[0].bus_width == 4) { | |
501 | at91_set_A_periph(AT91_PIN_PA24, 1); | |
502 | at91_set_A_periph(AT91_PIN_PA25, 1); | |
503 | at91_set_A_periph(AT91_PIN_PA26, 1); | |
504 | if (data->slot[0].bus_width == 8) { | |
505 | at91_set_A_periph(AT91_PIN_PA27, 1); | |
506 | at91_set_A_periph(AT91_PIN_PA28, 1); | |
507 | at91_set_A_periph(AT91_PIN_PA29, 1); | |
508 | at91_set_A_periph(AT91_PIN_PA30, 1); | |
509 | } | |
510 | } | |
511 | ||
512 | mmc1_data = *data; | |
75305d76 NF |
513 | platform_device_register(&at91sam9g45_mmc1_device); |
514 | ||
515 | } | |
516 | } | |
517 | #else | |
518 | void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data) {} | |
519 | #endif | |
520 | ||
521 | ||
789b23bc NF |
522 | /* -------------------------------------------------------------------- |
523 | * NAND / SmartMedia | |
524 | * -------------------------------------------------------------------- */ | |
525 | ||
526 | #if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE) | |
527 | static struct atmel_nand_data nand_data; | |
528 | ||
529 | #define NAND_BASE AT91_CHIPSELECT_3 | |
530 | ||
531 | static struct resource nand_resources[] = { | |
532 | [0] = { | |
533 | .start = NAND_BASE, | |
534 | .end = NAND_BASE + SZ_256M - 1, | |
535 | .flags = IORESOURCE_MEM, | |
536 | }, | |
537 | [1] = { | |
d28edd1b JCPV |
538 | .start = AT91SAM9G45_BASE_ECC, |
539 | .end = AT91SAM9G45_BASE_ECC + SZ_512 - 1, | |
789b23bc NF |
540 | .flags = IORESOURCE_MEM, |
541 | } | |
542 | }; | |
543 | ||
544 | static struct platform_device at91sam9g45_nand_device = { | |
545 | .name = "atmel_nand", | |
546 | .id = -1, | |
547 | .dev = { | |
548 | .platform_data = &nand_data, | |
549 | }, | |
550 | .resource = nand_resources, | |
551 | .num_resources = ARRAY_SIZE(nand_resources), | |
552 | }; | |
553 | ||
554 | void __init at91_add_device_nand(struct atmel_nand_data *data) | |
555 | { | |
556 | unsigned long csa; | |
557 | ||
558 | if (!data) | |
559 | return; | |
560 | ||
4342d647 JCPV |
561 | csa = at91_matrix_read(AT91_MATRIX_EBICSA); |
562 | at91_matrix_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA); | |
789b23bc NF |
563 | |
564 | /* enable pin */ | |
cc9f9aef | 565 | if (gpio_is_valid(data->enable_pin)) |
789b23bc NF |
566 | at91_set_gpio_output(data->enable_pin, 1); |
567 | ||
568 | /* ready/busy pin */ | |
cc9f9aef | 569 | if (gpio_is_valid(data->rdy_pin)) |
789b23bc NF |
570 | at91_set_gpio_input(data->rdy_pin, 1); |
571 | ||
572 | /* card detect pin */ | |
cc9f9aef | 573 | if (gpio_is_valid(data->det_pin)) |
789b23bc NF |
574 | at91_set_gpio_input(data->det_pin, 1); |
575 | ||
576 | nand_data = *data; | |
577 | platform_device_register(&at91sam9g45_nand_device); | |
578 | } | |
579 | #else | |
580 | void __init at91_add_device_nand(struct atmel_nand_data *data) {} | |
581 | #endif | |
582 | ||
583 | ||
584 | /* -------------------------------------------------------------------- | |
585 | * TWI (i2c) | |
586 | * -------------------------------------------------------------------- */ | |
587 | ||
588 | /* | |
589 | * Prefer the GPIO code since the TWI controller isn't robust | |
590 | * (gets overruns and underruns under load) and can only issue | |
591 | * repeated STARTs in one scenario (the driver doesn't yet handle them). | |
592 | */ | |
593 | #if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE) | |
594 | static struct i2c_gpio_platform_data pdata_i2c0 = { | |
595 | .sda_pin = AT91_PIN_PA20, | |
596 | .sda_is_open_drain = 1, | |
597 | .scl_pin = AT91_PIN_PA21, | |
598 | .scl_is_open_drain = 1, | |
1d5b4c0f | 599 | .udelay = 5, /* ~100 kHz */ |
789b23bc NF |
600 | }; |
601 | ||
602 | static struct platform_device at91sam9g45_twi0_device = { | |
603 | .name = "i2c-gpio", | |
604 | .id = 0, | |
605 | .dev.platform_data = &pdata_i2c0, | |
606 | }; | |
607 | ||
608 | static struct i2c_gpio_platform_data pdata_i2c1 = { | |
609 | .sda_pin = AT91_PIN_PB10, | |
610 | .sda_is_open_drain = 1, | |
611 | .scl_pin = AT91_PIN_PB11, | |
612 | .scl_is_open_drain = 1, | |
1d5b4c0f | 613 | .udelay = 5, /* ~100 kHz */ |
789b23bc NF |
614 | }; |
615 | ||
616 | static struct platform_device at91sam9g45_twi1_device = { | |
617 | .name = "i2c-gpio", | |
618 | .id = 1, | |
619 | .dev.platform_data = &pdata_i2c1, | |
620 | }; | |
621 | ||
622 | void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices) | |
623 | { | |
624 | i2c_register_board_info(i2c_id, devices, nr_devices); | |
625 | ||
626 | if (i2c_id == 0) { | |
627 | at91_set_GPIO_periph(AT91_PIN_PA20, 1); /* TWD (SDA) */ | |
628 | at91_set_multi_drive(AT91_PIN_PA20, 1); | |
629 | ||
630 | at91_set_GPIO_periph(AT91_PIN_PA21, 1); /* TWCK (SCL) */ | |
631 | at91_set_multi_drive(AT91_PIN_PA21, 1); | |
632 | ||
633 | platform_device_register(&at91sam9g45_twi0_device); | |
634 | } else { | |
635 | at91_set_GPIO_periph(AT91_PIN_PB10, 1); /* TWD (SDA) */ | |
636 | at91_set_multi_drive(AT91_PIN_PB10, 1); | |
637 | ||
638 | at91_set_GPIO_periph(AT91_PIN_PB11, 1); /* TWCK (SCL) */ | |
639 | at91_set_multi_drive(AT91_PIN_PB11, 1); | |
640 | ||
641 | platform_device_register(&at91sam9g45_twi1_device); | |
642 | } | |
643 | } | |
644 | ||
645 | #elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE) | |
646 | static struct resource twi0_resources[] = { | |
647 | [0] = { | |
648 | .start = AT91SAM9G45_BASE_TWI0, | |
649 | .end = AT91SAM9G45_BASE_TWI0 + SZ_16K - 1, | |
650 | .flags = IORESOURCE_MEM, | |
651 | }, | |
652 | [1] = { | |
653 | .start = AT91SAM9G45_ID_TWI0, | |
654 | .end = AT91SAM9G45_ID_TWI0, | |
655 | .flags = IORESOURCE_IRQ, | |
656 | }, | |
657 | }; | |
658 | ||
659 | static struct platform_device at91sam9g45_twi0_device = { | |
660 | .name = "at91_i2c", | |
661 | .id = 0, | |
662 | .resource = twi0_resources, | |
663 | .num_resources = ARRAY_SIZE(twi0_resources), | |
664 | }; | |
665 | ||
666 | static struct resource twi1_resources[] = { | |
667 | [0] = { | |
668 | .start = AT91SAM9G45_BASE_TWI1, | |
669 | .end = AT91SAM9G45_BASE_TWI1 + SZ_16K - 1, | |
670 | .flags = IORESOURCE_MEM, | |
671 | }, | |
672 | [1] = { | |
673 | .start = AT91SAM9G45_ID_TWI1, | |
674 | .end = AT91SAM9G45_ID_TWI1, | |
675 | .flags = IORESOURCE_IRQ, | |
676 | }, | |
677 | }; | |
678 | ||
679 | static struct platform_device at91sam9g45_twi1_device = { | |
680 | .name = "at91_i2c", | |
681 | .id = 1, | |
682 | .resource = twi1_resources, | |
683 | .num_resources = ARRAY_SIZE(twi1_resources), | |
684 | }; | |
685 | ||
686 | void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices) | |
687 | { | |
688 | i2c_register_board_info(i2c_id, devices, nr_devices); | |
689 | ||
690 | /* pins used for TWI interface */ | |
691 | if (i2c_id == 0) { | |
692 | at91_set_A_periph(AT91_PIN_PA20, 0); /* TWD */ | |
693 | at91_set_multi_drive(AT91_PIN_PA20, 1); | |
694 | ||
695 | at91_set_A_periph(AT91_PIN_PA21, 0); /* TWCK */ | |
696 | at91_set_multi_drive(AT91_PIN_PA21, 1); | |
697 | ||
698 | platform_device_register(&at91sam9g45_twi0_device); | |
699 | } else { | |
700 | at91_set_A_periph(AT91_PIN_PB10, 0); /* TWD */ | |
701 | at91_set_multi_drive(AT91_PIN_PB10, 1); | |
702 | ||
703 | at91_set_A_periph(AT91_PIN_PB11, 0); /* TWCK */ | |
704 | at91_set_multi_drive(AT91_PIN_PB11, 1); | |
705 | ||
706 | platform_device_register(&at91sam9g45_twi1_device); | |
707 | } | |
708 | } | |
709 | #else | |
710 | void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices) {} | |
711 | #endif | |
712 | ||
713 | ||
714 | /* -------------------------------------------------------------------- | |
715 | * SPI | |
716 | * -------------------------------------------------------------------- */ | |
717 | ||
718 | #if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE) | |
719 | static u64 spi_dmamask = DMA_BIT_MASK(32); | |
720 | ||
721 | static struct resource spi0_resources[] = { | |
722 | [0] = { | |
723 | .start = AT91SAM9G45_BASE_SPI0, | |
724 | .end = AT91SAM9G45_BASE_SPI0 + SZ_16K - 1, | |
725 | .flags = IORESOURCE_MEM, | |
726 | }, | |
727 | [1] = { | |
728 | .start = AT91SAM9G45_ID_SPI0, | |
729 | .end = AT91SAM9G45_ID_SPI0, | |
730 | .flags = IORESOURCE_IRQ, | |
731 | }, | |
732 | }; | |
733 | ||
734 | static struct platform_device at91sam9g45_spi0_device = { | |
735 | .name = "atmel_spi", | |
736 | .id = 0, | |
737 | .dev = { | |
738 | .dma_mask = &spi_dmamask, | |
739 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
740 | }, | |
741 | .resource = spi0_resources, | |
742 | .num_resources = ARRAY_SIZE(spi0_resources), | |
743 | }; | |
744 | ||
745 | static const unsigned spi0_standard_cs[4] = { AT91_PIN_PB3, AT91_PIN_PB18, AT91_PIN_PB19, AT91_PIN_PD27 }; | |
746 | ||
747 | static struct resource spi1_resources[] = { | |
748 | [0] = { | |
749 | .start = AT91SAM9G45_BASE_SPI1, | |
750 | .end = AT91SAM9G45_BASE_SPI1 + SZ_16K - 1, | |
751 | .flags = IORESOURCE_MEM, | |
752 | }, | |
753 | [1] = { | |
754 | .start = AT91SAM9G45_ID_SPI1, | |
755 | .end = AT91SAM9G45_ID_SPI1, | |
756 | .flags = IORESOURCE_IRQ, | |
757 | }, | |
758 | }; | |
759 | ||
760 | static struct platform_device at91sam9g45_spi1_device = { | |
761 | .name = "atmel_spi", | |
762 | .id = 1, | |
763 | .dev = { | |
764 | .dma_mask = &spi_dmamask, | |
765 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
766 | }, | |
767 | .resource = spi1_resources, | |
768 | .num_resources = ARRAY_SIZE(spi1_resources), | |
769 | }; | |
770 | ||
771 | static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB17, AT91_PIN_PD28, AT91_PIN_PD18, AT91_PIN_PD19 }; | |
772 | ||
773 | void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) | |
774 | { | |
775 | int i; | |
776 | unsigned long cs_pin; | |
777 | short enable_spi0 = 0; | |
778 | short enable_spi1 = 0; | |
779 | ||
780 | /* Choose SPI chip-selects */ | |
781 | for (i = 0; i < nr_devices; i++) { | |
782 | if (devices[i].controller_data) | |
783 | cs_pin = (unsigned long) devices[i].controller_data; | |
784 | else if (devices[i].bus_num == 0) | |
785 | cs_pin = spi0_standard_cs[devices[i].chip_select]; | |
786 | else | |
787 | cs_pin = spi1_standard_cs[devices[i].chip_select]; | |
788 | ||
789 | if (devices[i].bus_num == 0) | |
790 | enable_spi0 = 1; | |
791 | else | |
792 | enable_spi1 = 1; | |
793 | ||
794 | /* enable chip-select pin */ | |
795 | at91_set_gpio_output(cs_pin, 1); | |
796 | ||
797 | /* pass chip-select pin to driver */ | |
798 | devices[i].controller_data = (void *) cs_pin; | |
799 | } | |
800 | ||
801 | spi_register_board_info(devices, nr_devices); | |
802 | ||
803 | /* Configure SPI bus(es) */ | |
804 | if (enable_spi0) { | |
805 | at91_set_A_periph(AT91_PIN_PB0, 0); /* SPI0_MISO */ | |
806 | at91_set_A_periph(AT91_PIN_PB1, 0); /* SPI0_MOSI */ | |
807 | at91_set_A_periph(AT91_PIN_PB2, 0); /* SPI0_SPCK */ | |
808 | ||
789b23bc NF |
809 | platform_device_register(&at91sam9g45_spi0_device); |
810 | } | |
811 | if (enable_spi1) { | |
812 | at91_set_A_periph(AT91_PIN_PB14, 0); /* SPI1_MISO */ | |
813 | at91_set_A_periph(AT91_PIN_PB15, 0); /* SPI1_MOSI */ | |
814 | at91_set_A_periph(AT91_PIN_PB16, 0); /* SPI1_SPCK */ | |
815 | ||
789b23bc NF |
816 | platform_device_register(&at91sam9g45_spi1_device); |
817 | } | |
818 | } | |
819 | #else | |
820 | void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {} | |
821 | #endif | |
822 | ||
823 | ||
378ac65e NF |
824 | /* -------------------------------------------------------------------- |
825 | * AC97 | |
826 | * -------------------------------------------------------------------- */ | |
827 | ||
828 | #if defined(CONFIG_SND_ATMEL_AC97C) || defined(CONFIG_SND_ATMEL_AC97C_MODULE) | |
829 | static u64 ac97_dmamask = DMA_BIT_MASK(32); | |
830 | static struct ac97c_platform_data ac97_data; | |
831 | ||
832 | static struct resource ac97_resources[] = { | |
833 | [0] = { | |
834 | .start = AT91SAM9G45_BASE_AC97C, | |
835 | .end = AT91SAM9G45_BASE_AC97C + SZ_16K - 1, | |
836 | .flags = IORESOURCE_MEM, | |
837 | }, | |
838 | [1] = { | |
839 | .start = AT91SAM9G45_ID_AC97C, | |
840 | .end = AT91SAM9G45_ID_AC97C, | |
841 | .flags = IORESOURCE_IRQ, | |
842 | }, | |
843 | }; | |
844 | ||
845 | static struct platform_device at91sam9g45_ac97_device = { | |
846 | .name = "atmel_ac97c", | |
847 | .id = 0, | |
848 | .dev = { | |
849 | .dma_mask = &ac97_dmamask, | |
850 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
851 | .platform_data = &ac97_data, | |
852 | }, | |
853 | .resource = ac97_resources, | |
854 | .num_resources = ARRAY_SIZE(ac97_resources), | |
855 | }; | |
856 | ||
857 | void __init at91_add_device_ac97(struct ac97c_platform_data *data) | |
858 | { | |
859 | if (!data) | |
860 | return; | |
861 | ||
862 | at91_set_A_periph(AT91_PIN_PD8, 0); /* AC97FS */ | |
863 | at91_set_A_periph(AT91_PIN_PD9, 0); /* AC97CK */ | |
864 | at91_set_A_periph(AT91_PIN_PD7, 0); /* AC97TX */ | |
865 | at91_set_A_periph(AT91_PIN_PD6, 0); /* AC97RX */ | |
866 | ||
867 | /* reset */ | |
cc9f9aef | 868 | if (gpio_is_valid(data->reset_pin)) |
378ac65e NF |
869 | at91_set_gpio_output(data->reset_pin, 0); |
870 | ||
871 | ac97_data = *data; | |
872 | platform_device_register(&at91sam9g45_ac97_device); | |
873 | } | |
874 | #else | |
875 | void __init at91_add_device_ac97(struct ac97c_platform_data *data) {} | |
876 | #endif | |
877 | ||
343754f5 JW |
878 | /* -------------------------------------------------------------------- |
879 | * Image Sensor Interface | |
880 | * -------------------------------------------------------------------- */ | |
881 | #if defined(CONFIG_VIDEO_ATMEL_ISI) || defined(CONFIG_VIDEO_ATMEL_ISI_MODULE) | |
882 | static u64 isi_dmamask = DMA_BIT_MASK(32); | |
883 | static struct isi_platform_data isi_data; | |
884 | ||
885 | struct resource isi_resources[] = { | |
886 | [0] = { | |
887 | .start = AT91SAM9G45_BASE_ISI, | |
888 | .end = AT91SAM9G45_BASE_ISI + SZ_16K - 1, | |
889 | .flags = IORESOURCE_MEM, | |
890 | }, | |
891 | [1] = { | |
892 | .start = AT91SAM9G45_ID_ISI, | |
893 | .end = AT91SAM9G45_ID_ISI, | |
894 | .flags = IORESOURCE_IRQ, | |
895 | }, | |
896 | }; | |
897 | ||
898 | static struct platform_device at91sam9g45_isi_device = { | |
899 | .name = "atmel_isi", | |
900 | .id = 0, | |
901 | .dev = { | |
902 | .dma_mask = &isi_dmamask, | |
903 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
904 | .platform_data = &isi_data, | |
905 | }, | |
906 | .resource = isi_resources, | |
907 | .num_resources = ARRAY_SIZE(isi_resources), | |
908 | }; | |
909 | ||
910 | static struct clk_lookup isi_mck_lookups[] = { | |
911 | CLKDEV_CON_DEV_ID("isi_mck", "atmel_isi.0", NULL), | |
912 | }; | |
913 | ||
914 | void __init at91_add_device_isi(struct isi_platform_data *data, | |
915 | bool use_pck_as_mck) | |
916 | { | |
917 | struct clk *pck; | |
918 | struct clk *parent; | |
919 | ||
920 | if (!data) | |
921 | return; | |
922 | isi_data = *data; | |
923 | ||
924 | at91_set_A_periph(AT91_PIN_PB20, 0); /* ISI_D0 */ | |
925 | at91_set_A_periph(AT91_PIN_PB21, 0); /* ISI_D1 */ | |
926 | at91_set_A_periph(AT91_PIN_PB22, 0); /* ISI_D2 */ | |
927 | at91_set_A_periph(AT91_PIN_PB23, 0); /* ISI_D3 */ | |
928 | at91_set_A_periph(AT91_PIN_PB24, 0); /* ISI_D4 */ | |
929 | at91_set_A_periph(AT91_PIN_PB25, 0); /* ISI_D5 */ | |
930 | at91_set_A_periph(AT91_PIN_PB26, 0); /* ISI_D6 */ | |
931 | at91_set_A_periph(AT91_PIN_PB27, 0); /* ISI_D7 */ | |
932 | at91_set_A_periph(AT91_PIN_PB28, 0); /* ISI_PCK */ | |
933 | at91_set_A_periph(AT91_PIN_PB30, 0); /* ISI_HSYNC */ | |
934 | at91_set_A_periph(AT91_PIN_PB29, 0); /* ISI_VSYNC */ | |
935 | at91_set_B_periph(AT91_PIN_PB8, 0); /* ISI_PD8 */ | |
936 | at91_set_B_periph(AT91_PIN_PB9, 0); /* ISI_PD9 */ | |
937 | at91_set_B_periph(AT91_PIN_PB10, 0); /* ISI_PD10 */ | |
938 | at91_set_B_periph(AT91_PIN_PB11, 0); /* ISI_PD11 */ | |
939 | ||
940 | platform_device_register(&at91sam9g45_isi_device); | |
941 | ||
942 | if (use_pck_as_mck) { | |
943 | at91_set_B_periph(AT91_PIN_PB31, 0); /* ISI_MCK (PCK1) */ | |
944 | ||
945 | pck = clk_get(NULL, "pck1"); | |
946 | parent = clk_get(NULL, "plla"); | |
947 | ||
948 | BUG_ON(IS_ERR(pck) || IS_ERR(parent)); | |
949 | ||
950 | if (clk_set_parent(pck, parent)) { | |
951 | pr_err("Failed to set PCK's parent\n"); | |
952 | } else { | |
953 | /* Register PCK as ISI_MCK */ | |
954 | isi_mck_lookups[0].clk = pck; | |
955 | clkdev_add_table(isi_mck_lookups, | |
956 | ARRAY_SIZE(isi_mck_lookups)); | |
957 | } | |
958 | ||
959 | clk_put(pck); | |
960 | clk_put(parent); | |
961 | } | |
962 | } | |
963 | #else | |
964 | void __init at91_add_device_isi(struct isi_platform_data *data, | |
965 | bool use_pck_as_mck) {} | |
966 | #endif | |
967 | ||
378ac65e | 968 | |
789b23bc NF |
969 | /* -------------------------------------------------------------------- |
970 | * LCD Controller | |
971 | * -------------------------------------------------------------------- */ | |
972 | ||
973 | #if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE) | |
974 | static u64 lcdc_dmamask = DMA_BIT_MASK(32); | |
975 | static struct atmel_lcdfb_info lcdc_data; | |
976 | ||
977 | static struct resource lcdc_resources[] = { | |
978 | [0] = { | |
979 | .start = AT91SAM9G45_LCDC_BASE, | |
980 | .end = AT91SAM9G45_LCDC_BASE + SZ_4K - 1, | |
981 | .flags = IORESOURCE_MEM, | |
982 | }, | |
983 | [1] = { | |
984 | .start = AT91SAM9G45_ID_LCDC, | |
985 | .end = AT91SAM9G45_ID_LCDC, | |
986 | .flags = IORESOURCE_IRQ, | |
987 | }, | |
988 | }; | |
989 | ||
990 | static struct platform_device at91_lcdc_device = { | |
991 | .name = "atmel_lcdfb", | |
992 | .id = 0, | |
993 | .dev = { | |
994 | .dma_mask = &lcdc_dmamask, | |
995 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
996 | .platform_data = &lcdc_data, | |
997 | }, | |
998 | .resource = lcdc_resources, | |
999 | .num_resources = ARRAY_SIZE(lcdc_resources), | |
1000 | }; | |
1001 | ||
1002 | void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) | |
1003 | { | |
1004 | if (!data) | |
1005 | return; | |
1006 | ||
1007 | at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */ | |
1008 | ||
1009 | at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */ | |
1010 | at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */ | |
1011 | at91_set_A_periph(AT91_PIN_PE4, 0); /* LCDHSYNC */ | |
1012 | at91_set_A_periph(AT91_PIN_PE5, 0); /* LCDDOTCK */ | |
1013 | at91_set_A_periph(AT91_PIN_PE6, 0); /* LCDDEN */ | |
1014 | at91_set_A_periph(AT91_PIN_PE7, 0); /* LCDD0 */ | |
1015 | at91_set_A_periph(AT91_PIN_PE8, 0); /* LCDD1 */ | |
1016 | at91_set_A_periph(AT91_PIN_PE9, 0); /* LCDD2 */ | |
1017 | at91_set_A_periph(AT91_PIN_PE10, 0); /* LCDD3 */ | |
1018 | at91_set_A_periph(AT91_PIN_PE11, 0); /* LCDD4 */ | |
1019 | at91_set_A_periph(AT91_PIN_PE12, 0); /* LCDD5 */ | |
1020 | at91_set_A_periph(AT91_PIN_PE13, 0); /* LCDD6 */ | |
1021 | at91_set_A_periph(AT91_PIN_PE14, 0); /* LCDD7 */ | |
1022 | at91_set_A_periph(AT91_PIN_PE15, 0); /* LCDD8 */ | |
1023 | at91_set_A_periph(AT91_PIN_PE16, 0); /* LCDD9 */ | |
1024 | at91_set_A_periph(AT91_PIN_PE17, 0); /* LCDD10 */ | |
1025 | at91_set_A_periph(AT91_PIN_PE18, 0); /* LCDD11 */ | |
1026 | at91_set_A_periph(AT91_PIN_PE19, 0); /* LCDD12 */ | |
1027 | at91_set_A_periph(AT91_PIN_PE20, 0); /* LCDD13 */ | |
1028 | at91_set_A_periph(AT91_PIN_PE21, 0); /* LCDD14 */ | |
1029 | at91_set_A_periph(AT91_PIN_PE22, 0); /* LCDD15 */ | |
1030 | at91_set_A_periph(AT91_PIN_PE23, 0); /* LCDD16 */ | |
1031 | at91_set_A_periph(AT91_PIN_PE24, 0); /* LCDD17 */ | |
1032 | at91_set_A_periph(AT91_PIN_PE25, 0); /* LCDD18 */ | |
1033 | at91_set_A_periph(AT91_PIN_PE26, 0); /* LCDD19 */ | |
1034 | at91_set_A_periph(AT91_PIN_PE27, 0); /* LCDD20 */ | |
1035 | at91_set_A_periph(AT91_PIN_PE28, 0); /* LCDD21 */ | |
1036 | at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */ | |
1037 | at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */ | |
1038 | ||
1039 | lcdc_data = *data; | |
1040 | platform_device_register(&at91_lcdc_device); | |
1041 | } | |
1042 | #else | |
1043 | void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {} | |
1044 | #endif | |
1045 | ||
1046 | ||
1047 | /* -------------------------------------------------------------------- | |
1048 | * Timer/Counter block | |
1049 | * -------------------------------------------------------------------- */ | |
1050 | ||
1051 | #ifdef CONFIG_ATMEL_TCLIB | |
1052 | static struct resource tcb0_resources[] = { | |
1053 | [0] = { | |
1054 | .start = AT91SAM9G45_BASE_TCB0, | |
29831297 | 1055 | .end = AT91SAM9G45_BASE_TCB0 + SZ_256 - 1, |
789b23bc NF |
1056 | .flags = IORESOURCE_MEM, |
1057 | }, | |
1058 | [1] = { | |
1059 | .start = AT91SAM9G45_ID_TCB, | |
1060 | .end = AT91SAM9G45_ID_TCB, | |
1061 | .flags = IORESOURCE_IRQ, | |
1062 | }, | |
1063 | }; | |
1064 | ||
1065 | static struct platform_device at91sam9g45_tcb0_device = { | |
1066 | .name = "atmel_tcb", | |
1067 | .id = 0, | |
1068 | .resource = tcb0_resources, | |
1069 | .num_resources = ARRAY_SIZE(tcb0_resources), | |
1070 | }; | |
1071 | ||
1072 | /* TCB1 begins with TC3 */ | |
1073 | static struct resource tcb1_resources[] = { | |
1074 | [0] = { | |
1075 | .start = AT91SAM9G45_BASE_TCB1, | |
29831297 | 1076 | .end = AT91SAM9G45_BASE_TCB1 + SZ_256 - 1, |
789b23bc NF |
1077 | .flags = IORESOURCE_MEM, |
1078 | }, | |
1079 | [1] = { | |
1080 | .start = AT91SAM9G45_ID_TCB, | |
1081 | .end = AT91SAM9G45_ID_TCB, | |
1082 | .flags = IORESOURCE_IRQ, | |
1083 | }, | |
1084 | }; | |
1085 | ||
1086 | static struct platform_device at91sam9g45_tcb1_device = { | |
1087 | .name = "atmel_tcb", | |
1088 | .id = 1, | |
1089 | .resource = tcb1_resources, | |
1090 | .num_resources = ARRAY_SIZE(tcb1_resources), | |
1091 | }; | |
1092 | ||
1093 | static void __init at91_add_device_tc(void) | |
1094 | { | |
789b23bc | 1095 | platform_device_register(&at91sam9g45_tcb0_device); |
789b23bc NF |
1096 | platform_device_register(&at91sam9g45_tcb1_device); |
1097 | } | |
1098 | #else | |
1099 | static void __init at91_add_device_tc(void) { } | |
1100 | #endif | |
1101 | ||
1102 | ||
1103 | /* -------------------------------------------------------------------- | |
1104 | * RTC | |
1105 | * -------------------------------------------------------------------- */ | |
1106 | ||
1107 | #if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE) | |
d28bdfc5 JCPV |
1108 | static struct resource rtc_resources[] = { |
1109 | [0] = { | |
1110 | .start = AT91SAM9G45_BASE_RTC, | |
1111 | .end = AT91SAM9G45_BASE_RTC + SZ_256 - 1, | |
1112 | .flags = IORESOURCE_MEM, | |
1113 | }, | |
1114 | [1] = { | |
1115 | .start = AT91_ID_SYS, | |
1116 | .end = AT91_ID_SYS, | |
1117 | .flags = IORESOURCE_IRQ, | |
1118 | }, | |
1119 | }; | |
1120 | ||
789b23bc NF |
1121 | static struct platform_device at91sam9g45_rtc_device = { |
1122 | .name = "at91_rtc", | |
1123 | .id = -1, | |
d28bdfc5 JCPV |
1124 | .resource = rtc_resources, |
1125 | .num_resources = ARRAY_SIZE(rtc_resources), | |
789b23bc NF |
1126 | }; |
1127 | ||
1128 | static void __init at91_add_device_rtc(void) | |
1129 | { | |
1130 | platform_device_register(&at91sam9g45_rtc_device); | |
1131 | } | |
1132 | #else | |
1133 | static void __init at91_add_device_rtc(void) {} | |
1134 | #endif | |
1135 | ||
1136 | ||
985f37f8 NF |
1137 | /* -------------------------------------------------------------------- |
1138 | * Touchscreen | |
1139 | * -------------------------------------------------------------------- */ | |
1140 | ||
1141 | #if defined(CONFIG_TOUCHSCREEN_ATMEL_TSADCC) || defined(CONFIG_TOUCHSCREEN_ATMEL_TSADCC_MODULE) | |
1142 | static u64 tsadcc_dmamask = DMA_BIT_MASK(32); | |
1143 | static struct at91_tsadcc_data tsadcc_data; | |
1144 | ||
1145 | static struct resource tsadcc_resources[] = { | |
1146 | [0] = { | |
1147 | .start = AT91SAM9G45_BASE_TSC, | |
1148 | .end = AT91SAM9G45_BASE_TSC + SZ_16K - 1, | |
1149 | .flags = IORESOURCE_MEM, | |
1150 | }, | |
1151 | [1] = { | |
1152 | .start = AT91SAM9G45_ID_TSC, | |
1153 | .end = AT91SAM9G45_ID_TSC, | |
1154 | .flags = IORESOURCE_IRQ, | |
1155 | } | |
1156 | }; | |
1157 | ||
1158 | static struct platform_device at91sam9g45_tsadcc_device = { | |
1159 | .name = "atmel_tsadcc", | |
1160 | .id = -1, | |
1161 | .dev = { | |
1162 | .dma_mask = &tsadcc_dmamask, | |
1163 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
1164 | .platform_data = &tsadcc_data, | |
1165 | }, | |
1166 | .resource = tsadcc_resources, | |
1167 | .num_resources = ARRAY_SIZE(tsadcc_resources), | |
1168 | }; | |
1169 | ||
1170 | void __init at91_add_device_tsadcc(struct at91_tsadcc_data *data) | |
1171 | { | |
1172 | if (!data) | |
1173 | return; | |
1174 | ||
1175 | at91_set_gpio_input(AT91_PIN_PD20, 0); /* AD0_XR */ | |
1176 | at91_set_gpio_input(AT91_PIN_PD21, 0); /* AD1_XL */ | |
1177 | at91_set_gpio_input(AT91_PIN_PD22, 0); /* AD2_YT */ | |
1178 | at91_set_gpio_input(AT91_PIN_PD23, 0); /* AD3_TB */ | |
1179 | ||
1180 | tsadcc_data = *data; | |
1181 | platform_device_register(&at91sam9g45_tsadcc_device); | |
1182 | } | |
1183 | #else | |
1184 | void __init at91_add_device_tsadcc(struct at91_tsadcc_data *data) {} | |
1185 | #endif | |
1186 | ||
1187 | ||
789b23bc NF |
1188 | /* -------------------------------------------------------------------- |
1189 | * RTT | |
1190 | * -------------------------------------------------------------------- */ | |
1191 | ||
1192 | static struct resource rtt_resources[] = { | |
1193 | { | |
eab5fd67 JCPV |
1194 | .start = AT91SAM9G45_BASE_RTT, |
1195 | .end = AT91SAM9G45_BASE_RTT + SZ_16 - 1, | |
789b23bc | 1196 | .flags = IORESOURCE_MEM, |
b3af8b49 JCPV |
1197 | }, { |
1198 | .flags = IORESOURCE_MEM, | |
789b23bc NF |
1199 | } |
1200 | }; | |
1201 | ||
1202 | static struct platform_device at91sam9g45_rtt_device = { | |
1203 | .name = "at91_rtt", | |
1204 | .id = 0, | |
1205 | .resource = rtt_resources, | |
789b23bc NF |
1206 | }; |
1207 | ||
205056a3 JCPV |
1208 | #if IS_ENABLED(CONFIG_RTC_DRV_AT91SAM9) |
1209 | static void __init at91_add_device_rtt_rtc(void) | |
1210 | { | |
1211 | at91sam9g45_rtt_device.name = "rtc-at91sam9"; | |
b3af8b49 JCPV |
1212 | /* |
1213 | * The second resource is needed: | |
1214 | * GPBR will serve as the storage for RTC time offset | |
1215 | */ | |
1216 | at91sam9g45_rtt_device.num_resources = 2; | |
1217 | rtt_resources[1].start = AT91SAM9G45_BASE_GPBR + | |
1218 | 4 * CONFIG_RTC_DRV_AT91SAM9_GPBR; | |
1219 | rtt_resources[1].end = rtt_resources[1].start + 3; | |
205056a3 JCPV |
1220 | } |
1221 | #else | |
b3af8b49 JCPV |
1222 | static void __init at91_add_device_rtt_rtc(void) |
1223 | { | |
1224 | /* Only one resource is needed: RTT not used as RTC */ | |
1225 | at91sam9g45_rtt_device.num_resources = 1; | |
1226 | } | |
205056a3 JCPV |
1227 | #endif |
1228 | ||
789b23bc NF |
1229 | static void __init at91_add_device_rtt(void) |
1230 | { | |
205056a3 | 1231 | at91_add_device_rtt_rtc(); |
789b23bc NF |
1232 | platform_device_register(&at91sam9g45_rtt_device); |
1233 | } | |
1234 | ||
1235 | ||
237a62a1 PK |
1236 | /* -------------------------------------------------------------------- |
1237 | * TRNG | |
1238 | * -------------------------------------------------------------------- */ | |
1239 | ||
1240 | #if defined(CONFIG_HW_RANDOM_ATMEL) || defined(CONFIG_HW_RANDOM_ATMEL_MODULE) | |
1241 | static struct resource trng_resources[] = { | |
1242 | { | |
1243 | .start = AT91SAM9G45_BASE_TRNG, | |
1244 | .end = AT91SAM9G45_BASE_TRNG + SZ_16K - 1, | |
1245 | .flags = IORESOURCE_MEM, | |
1246 | }, | |
1247 | }; | |
1248 | ||
1249 | static struct platform_device at91sam9g45_trng_device = { | |
1250 | .name = "atmel-trng", | |
1251 | .id = -1, | |
1252 | .resource = trng_resources, | |
1253 | .num_resources = ARRAY_SIZE(trng_resources), | |
1254 | }; | |
1255 | ||
1256 | static void __init at91_add_device_trng(void) | |
1257 | { | |
1258 | platform_device_register(&at91sam9g45_trng_device); | |
1259 | } | |
1260 | #else | |
1261 | static void __init at91_add_device_trng(void) {} | |
1262 | #endif | |
1263 | ||
789b23bc NF |
1264 | /* -------------------------------------------------------------------- |
1265 | * Watchdog | |
1266 | * -------------------------------------------------------------------- */ | |
1267 | ||
4726374f | 1268 | #if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE) |
c1c30a29 JCPV |
1269 | static struct resource wdt_resources[] = { |
1270 | { | |
1271 | .start = AT91SAM9G45_BASE_WDT, | |
1272 | .end = AT91SAM9G45_BASE_WDT + SZ_16 - 1, | |
1273 | .flags = IORESOURCE_MEM, | |
1274 | } | |
1275 | }; | |
1276 | ||
789b23bc NF |
1277 | static struct platform_device at91sam9g45_wdt_device = { |
1278 | .name = "at91_wdt", | |
1279 | .id = -1, | |
c1c30a29 JCPV |
1280 | .resource = wdt_resources, |
1281 | .num_resources = ARRAY_SIZE(wdt_resources), | |
789b23bc NF |
1282 | }; |
1283 | ||
1284 | static void __init at91_add_device_watchdog(void) | |
1285 | { | |
1286 | platform_device_register(&at91sam9g45_wdt_device); | |
1287 | } | |
1288 | #else | |
1289 | static void __init at91_add_device_watchdog(void) {} | |
1290 | #endif | |
1291 | ||
1292 | ||
1293 | /* -------------------------------------------------------------------- | |
1294 | * PWM | |
1295 | * --------------------------------------------------------------------*/ | |
1296 | ||
1297 | #if defined(CONFIG_ATMEL_PWM) || defined(CONFIG_ATMEL_PWM_MODULE) | |
1298 | static u32 pwm_mask; | |
1299 | ||
1300 | static struct resource pwm_resources[] = { | |
1301 | [0] = { | |
1302 | .start = AT91SAM9G45_BASE_PWMC, | |
1303 | .end = AT91SAM9G45_BASE_PWMC + SZ_16K - 1, | |
1304 | .flags = IORESOURCE_MEM, | |
1305 | }, | |
1306 | [1] = { | |
1307 | .start = AT91SAM9G45_ID_PWMC, | |
1308 | .end = AT91SAM9G45_ID_PWMC, | |
1309 | .flags = IORESOURCE_IRQ, | |
1310 | }, | |
1311 | }; | |
1312 | ||
1313 | static struct platform_device at91sam9g45_pwm0_device = { | |
1314 | .name = "atmel_pwm", | |
1315 | .id = -1, | |
1316 | .dev = { | |
1317 | .platform_data = &pwm_mask, | |
1318 | }, | |
1319 | .resource = pwm_resources, | |
1320 | .num_resources = ARRAY_SIZE(pwm_resources), | |
1321 | }; | |
1322 | ||
1323 | void __init at91_add_device_pwm(u32 mask) | |
1324 | { | |
1325 | if (mask & (1 << AT91_PWM0)) | |
1326 | at91_set_B_periph(AT91_PIN_PD24, 1); /* enable PWM0 */ | |
1327 | ||
1328 | if (mask & (1 << AT91_PWM1)) | |
1329 | at91_set_B_periph(AT91_PIN_PD31, 1); /* enable PWM1 */ | |
1330 | ||
1331 | if (mask & (1 << AT91_PWM2)) | |
1332 | at91_set_B_periph(AT91_PIN_PD26, 1); /* enable PWM2 */ | |
1333 | ||
1334 | if (mask & (1 << AT91_PWM3)) | |
1335 | at91_set_B_periph(AT91_PIN_PD0, 1); /* enable PWM3 */ | |
1336 | ||
1337 | pwm_mask = mask; | |
1338 | ||
1339 | platform_device_register(&at91sam9g45_pwm0_device); | |
1340 | } | |
1341 | #else | |
1342 | void __init at91_add_device_pwm(u32 mask) {} | |
1343 | #endif | |
1344 | ||
1345 | ||
1346 | /* -------------------------------------------------------------------- | |
1347 | * SSC -- Synchronous Serial Controller | |
1348 | * -------------------------------------------------------------------- */ | |
1349 | ||
1350 | #if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE) | |
1351 | static u64 ssc0_dmamask = DMA_BIT_MASK(32); | |
1352 | ||
1353 | static struct resource ssc0_resources[] = { | |
1354 | [0] = { | |
1355 | .start = AT91SAM9G45_BASE_SSC0, | |
1356 | .end = AT91SAM9G45_BASE_SSC0 + SZ_16K - 1, | |
1357 | .flags = IORESOURCE_MEM, | |
1358 | }, | |
1359 | [1] = { | |
1360 | .start = AT91SAM9G45_ID_SSC0, | |
1361 | .end = AT91SAM9G45_ID_SSC0, | |
1362 | .flags = IORESOURCE_IRQ, | |
1363 | }, | |
1364 | }; | |
1365 | ||
1366 | static struct platform_device at91sam9g45_ssc0_device = { | |
1367 | .name = "ssc", | |
1368 | .id = 0, | |
1369 | .dev = { | |
1370 | .dma_mask = &ssc0_dmamask, | |
1371 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
1372 | }, | |
1373 | .resource = ssc0_resources, | |
1374 | .num_resources = ARRAY_SIZE(ssc0_resources), | |
1375 | }; | |
1376 | ||
1377 | static inline void configure_ssc0_pins(unsigned pins) | |
1378 | { | |
1379 | if (pins & ATMEL_SSC_TF) | |
1380 | at91_set_A_periph(AT91_PIN_PD1, 1); | |
1381 | if (pins & ATMEL_SSC_TK) | |
1382 | at91_set_A_periph(AT91_PIN_PD0, 1); | |
1383 | if (pins & ATMEL_SSC_TD) | |
1384 | at91_set_A_periph(AT91_PIN_PD2, 1); | |
1385 | if (pins & ATMEL_SSC_RD) | |
1386 | at91_set_A_periph(AT91_PIN_PD3, 1); | |
1387 | if (pins & ATMEL_SSC_RK) | |
1388 | at91_set_A_periph(AT91_PIN_PD4, 1); | |
1389 | if (pins & ATMEL_SSC_RF) | |
1390 | at91_set_A_periph(AT91_PIN_PD5, 1); | |
1391 | } | |
1392 | ||
1393 | static u64 ssc1_dmamask = DMA_BIT_MASK(32); | |
1394 | ||
1395 | static struct resource ssc1_resources[] = { | |
1396 | [0] = { | |
1397 | .start = AT91SAM9G45_BASE_SSC1, | |
1398 | .end = AT91SAM9G45_BASE_SSC1 + SZ_16K - 1, | |
1399 | .flags = IORESOURCE_MEM, | |
1400 | }, | |
1401 | [1] = { | |
1402 | .start = AT91SAM9G45_ID_SSC1, | |
1403 | .end = AT91SAM9G45_ID_SSC1, | |
1404 | .flags = IORESOURCE_IRQ, | |
1405 | }, | |
1406 | }; | |
1407 | ||
1408 | static struct platform_device at91sam9g45_ssc1_device = { | |
1409 | .name = "ssc", | |
1410 | .id = 1, | |
1411 | .dev = { | |
1412 | .dma_mask = &ssc1_dmamask, | |
1413 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
1414 | }, | |
1415 | .resource = ssc1_resources, | |
1416 | .num_resources = ARRAY_SIZE(ssc1_resources), | |
1417 | }; | |
1418 | ||
1419 | static inline void configure_ssc1_pins(unsigned pins) | |
1420 | { | |
1421 | if (pins & ATMEL_SSC_TF) | |
1422 | at91_set_A_periph(AT91_PIN_PD14, 1); | |
1423 | if (pins & ATMEL_SSC_TK) | |
1424 | at91_set_A_periph(AT91_PIN_PD12, 1); | |
1425 | if (pins & ATMEL_SSC_TD) | |
1426 | at91_set_A_periph(AT91_PIN_PD10, 1); | |
1427 | if (pins & ATMEL_SSC_RD) | |
1428 | at91_set_A_periph(AT91_PIN_PD11, 1); | |
1429 | if (pins & ATMEL_SSC_RK) | |
1430 | at91_set_A_periph(AT91_PIN_PD13, 1); | |
1431 | if (pins & ATMEL_SSC_RF) | |
1432 | at91_set_A_periph(AT91_PIN_PD15, 1); | |
1433 | } | |
1434 | ||
1435 | /* | |
1436 | * SSC controllers are accessed through library code, instead of any | |
1437 | * kind of all-singing/all-dancing driver. For example one could be | |
1438 | * used by a particular I2S audio codec's driver, while another one | |
1439 | * on the same system might be used by a custom data capture driver. | |
1440 | */ | |
1441 | void __init at91_add_device_ssc(unsigned id, unsigned pins) | |
1442 | { | |
1443 | struct platform_device *pdev; | |
1444 | ||
1445 | /* | |
1446 | * NOTE: caller is responsible for passing information matching | |
1447 | * "pins" to whatever will be using each particular controller. | |
1448 | */ | |
1449 | switch (id) { | |
1450 | case AT91SAM9G45_ID_SSC0: | |
1451 | pdev = &at91sam9g45_ssc0_device; | |
1452 | configure_ssc0_pins(pins); | |
789b23bc NF |
1453 | break; |
1454 | case AT91SAM9G45_ID_SSC1: | |
1455 | pdev = &at91sam9g45_ssc1_device; | |
1456 | configure_ssc1_pins(pins); | |
789b23bc NF |
1457 | break; |
1458 | default: | |
1459 | return; | |
1460 | } | |
1461 | ||
1462 | platform_device_register(pdev); | |
1463 | } | |
1464 | ||
1465 | #else | |
1466 | void __init at91_add_device_ssc(unsigned id, unsigned pins) {} | |
1467 | #endif | |
1468 | ||
1469 | ||
1470 | /* -------------------------------------------------------------------- | |
1471 | * UART | |
1472 | * -------------------------------------------------------------------- */ | |
1473 | ||
1474 | #if defined(CONFIG_SERIAL_ATMEL) | |
1475 | static struct resource dbgu_resources[] = { | |
1476 | [0] = { | |
13079a73 JCPV |
1477 | .start = AT91SAM9G45_BASE_DBGU, |
1478 | .end = AT91SAM9G45_BASE_DBGU + SZ_512 - 1, | |
789b23bc NF |
1479 | .flags = IORESOURCE_MEM, |
1480 | }, | |
1481 | [1] = { | |
1482 | .start = AT91_ID_SYS, | |
1483 | .end = AT91_ID_SYS, | |
1484 | .flags = IORESOURCE_IRQ, | |
1485 | }, | |
1486 | }; | |
1487 | ||
1488 | static struct atmel_uart_data dbgu_data = { | |
1489 | .use_dma_tx = 0, | |
1490 | .use_dma_rx = 0, | |
789b23bc NF |
1491 | }; |
1492 | ||
1493 | static u64 dbgu_dmamask = DMA_BIT_MASK(32); | |
1494 | ||
1495 | static struct platform_device at91sam9g45_dbgu_device = { | |
1496 | .name = "atmel_usart", | |
1497 | .id = 0, | |
1498 | .dev = { | |
1499 | .dma_mask = &dbgu_dmamask, | |
1500 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
1501 | .platform_data = &dbgu_data, | |
1502 | }, | |
1503 | .resource = dbgu_resources, | |
1504 | .num_resources = ARRAY_SIZE(dbgu_resources), | |
1505 | }; | |
1506 | ||
1507 | static inline void configure_dbgu_pins(void) | |
1508 | { | |
1509 | at91_set_A_periph(AT91_PIN_PB12, 0); /* DRXD */ | |
1510 | at91_set_A_periph(AT91_PIN_PB13, 1); /* DTXD */ | |
1511 | } | |
1512 | ||
1513 | static struct resource uart0_resources[] = { | |
1514 | [0] = { | |
1515 | .start = AT91SAM9G45_BASE_US0, | |
1516 | .end = AT91SAM9G45_BASE_US0 + SZ_16K - 1, | |
1517 | .flags = IORESOURCE_MEM, | |
1518 | }, | |
1519 | [1] = { | |
1520 | .start = AT91SAM9G45_ID_US0, | |
1521 | .end = AT91SAM9G45_ID_US0, | |
1522 | .flags = IORESOURCE_IRQ, | |
1523 | }, | |
1524 | }; | |
1525 | ||
1526 | static struct atmel_uart_data uart0_data = { | |
1527 | .use_dma_tx = 1, | |
1528 | .use_dma_rx = 1, | |
1529 | }; | |
1530 | ||
1531 | static u64 uart0_dmamask = DMA_BIT_MASK(32); | |
1532 | ||
1533 | static struct platform_device at91sam9g45_uart0_device = { | |
1534 | .name = "atmel_usart", | |
1535 | .id = 1, | |
1536 | .dev = { | |
1537 | .dma_mask = &uart0_dmamask, | |
1538 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
1539 | .platform_data = &uart0_data, | |
1540 | }, | |
1541 | .resource = uart0_resources, | |
1542 | .num_resources = ARRAY_SIZE(uart0_resources), | |
1543 | }; | |
1544 | ||
1545 | static inline void configure_usart0_pins(unsigned pins) | |
1546 | { | |
1547 | at91_set_A_periph(AT91_PIN_PB19, 1); /* TXD0 */ | |
1548 | at91_set_A_periph(AT91_PIN_PB18, 0); /* RXD0 */ | |
1549 | ||
1550 | if (pins & ATMEL_UART_RTS) | |
1551 | at91_set_B_periph(AT91_PIN_PB17, 0); /* RTS0 */ | |
1552 | if (pins & ATMEL_UART_CTS) | |
1553 | at91_set_B_periph(AT91_PIN_PB15, 0); /* CTS0 */ | |
1554 | } | |
1555 | ||
1556 | static struct resource uart1_resources[] = { | |
1557 | [0] = { | |
1558 | .start = AT91SAM9G45_BASE_US1, | |
1559 | .end = AT91SAM9G45_BASE_US1 + SZ_16K - 1, | |
1560 | .flags = IORESOURCE_MEM, | |
1561 | }, | |
1562 | [1] = { | |
1563 | .start = AT91SAM9G45_ID_US1, | |
1564 | .end = AT91SAM9G45_ID_US1, | |
1565 | .flags = IORESOURCE_IRQ, | |
1566 | }, | |
1567 | }; | |
1568 | ||
1569 | static struct atmel_uart_data uart1_data = { | |
1570 | .use_dma_tx = 1, | |
1571 | .use_dma_rx = 1, | |
1572 | }; | |
1573 | ||
1574 | static u64 uart1_dmamask = DMA_BIT_MASK(32); | |
1575 | ||
1576 | static struct platform_device at91sam9g45_uart1_device = { | |
1577 | .name = "atmel_usart", | |
1578 | .id = 2, | |
1579 | .dev = { | |
1580 | .dma_mask = &uart1_dmamask, | |
1581 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
1582 | .platform_data = &uart1_data, | |
1583 | }, | |
1584 | .resource = uart1_resources, | |
1585 | .num_resources = ARRAY_SIZE(uart1_resources), | |
1586 | }; | |
1587 | ||
1588 | static inline void configure_usart1_pins(unsigned pins) | |
1589 | { | |
1590 | at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD1 */ | |
1591 | at91_set_A_periph(AT91_PIN_PB5, 0); /* RXD1 */ | |
1592 | ||
1593 | if (pins & ATMEL_UART_RTS) | |
1594 | at91_set_A_periph(AT91_PIN_PD16, 0); /* RTS1 */ | |
1595 | if (pins & ATMEL_UART_CTS) | |
1596 | at91_set_A_periph(AT91_PIN_PD17, 0); /* CTS1 */ | |
1597 | } | |
1598 | ||
1599 | static struct resource uart2_resources[] = { | |
1600 | [0] = { | |
1601 | .start = AT91SAM9G45_BASE_US2, | |
1602 | .end = AT91SAM9G45_BASE_US2 + SZ_16K - 1, | |
1603 | .flags = IORESOURCE_MEM, | |
1604 | }, | |
1605 | [1] = { | |
1606 | .start = AT91SAM9G45_ID_US2, | |
1607 | .end = AT91SAM9G45_ID_US2, | |
1608 | .flags = IORESOURCE_IRQ, | |
1609 | }, | |
1610 | }; | |
1611 | ||
1612 | static struct atmel_uart_data uart2_data = { | |
1613 | .use_dma_tx = 1, | |
1614 | .use_dma_rx = 1, | |
1615 | }; | |
1616 | ||
1617 | static u64 uart2_dmamask = DMA_BIT_MASK(32); | |
1618 | ||
1619 | static struct platform_device at91sam9g45_uart2_device = { | |
1620 | .name = "atmel_usart", | |
1621 | .id = 3, | |
1622 | .dev = { | |
1623 | .dma_mask = &uart2_dmamask, | |
1624 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
1625 | .platform_data = &uart2_data, | |
1626 | }, | |
1627 | .resource = uart2_resources, | |
1628 | .num_resources = ARRAY_SIZE(uart2_resources), | |
1629 | }; | |
1630 | ||
1631 | static inline void configure_usart2_pins(unsigned pins) | |
1632 | { | |
1633 | at91_set_A_periph(AT91_PIN_PB6, 1); /* TXD2 */ | |
1634 | at91_set_A_periph(AT91_PIN_PB7, 0); /* RXD2 */ | |
1635 | ||
1636 | if (pins & ATMEL_UART_RTS) | |
1637 | at91_set_B_periph(AT91_PIN_PC9, 0); /* RTS2 */ | |
1638 | if (pins & ATMEL_UART_CTS) | |
1639 | at91_set_B_periph(AT91_PIN_PC11, 0); /* CTS2 */ | |
1640 | } | |
1641 | ||
1642 | static struct resource uart3_resources[] = { | |
1643 | [0] = { | |
1644 | .start = AT91SAM9G45_BASE_US3, | |
1645 | .end = AT91SAM9G45_BASE_US3 + SZ_16K - 1, | |
1646 | .flags = IORESOURCE_MEM, | |
1647 | }, | |
1648 | [1] = { | |
1649 | .start = AT91SAM9G45_ID_US3, | |
1650 | .end = AT91SAM9G45_ID_US3, | |
1651 | .flags = IORESOURCE_IRQ, | |
1652 | }, | |
1653 | }; | |
1654 | ||
1655 | static struct atmel_uart_data uart3_data = { | |
1656 | .use_dma_tx = 1, | |
1657 | .use_dma_rx = 1, | |
1658 | }; | |
1659 | ||
1660 | static u64 uart3_dmamask = DMA_BIT_MASK(32); | |
1661 | ||
1662 | static struct platform_device at91sam9g45_uart3_device = { | |
1663 | .name = "atmel_usart", | |
1664 | .id = 4, | |
1665 | .dev = { | |
1666 | .dma_mask = &uart3_dmamask, | |
1667 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
1668 | .platform_data = &uart3_data, | |
1669 | }, | |
1670 | .resource = uart3_resources, | |
1671 | .num_resources = ARRAY_SIZE(uart3_resources), | |
1672 | }; | |
1673 | ||
1674 | static inline void configure_usart3_pins(unsigned pins) | |
1675 | { | |
1676 | at91_set_A_periph(AT91_PIN_PB8, 1); /* TXD3 */ | |
1677 | at91_set_A_periph(AT91_PIN_PB9, 0); /* RXD3 */ | |
1678 | ||
1679 | if (pins & ATMEL_UART_RTS) | |
1680 | at91_set_B_periph(AT91_PIN_PA23, 0); /* RTS3 */ | |
1681 | if (pins & ATMEL_UART_CTS) | |
1682 | at91_set_B_periph(AT91_PIN_PA24, 0); /* CTS3 */ | |
1683 | } | |
1684 | ||
1685 | static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */ | |
789b23bc NF |
1686 | |
1687 | void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) | |
1688 | { | |
1689 | struct platform_device *pdev; | |
2b348e2f | 1690 | struct atmel_uart_data *pdata; |
789b23bc NF |
1691 | |
1692 | switch (id) { | |
1693 | case 0: /* DBGU */ | |
1694 | pdev = &at91sam9g45_dbgu_device; | |
1695 | configure_dbgu_pins(); | |
789b23bc NF |
1696 | break; |
1697 | case AT91SAM9G45_ID_US0: | |
1698 | pdev = &at91sam9g45_uart0_device; | |
1699 | configure_usart0_pins(pins); | |
789b23bc NF |
1700 | break; |
1701 | case AT91SAM9G45_ID_US1: | |
1702 | pdev = &at91sam9g45_uart1_device; | |
1703 | configure_usart1_pins(pins); | |
789b23bc NF |
1704 | break; |
1705 | case AT91SAM9G45_ID_US2: | |
1706 | pdev = &at91sam9g45_uart2_device; | |
1707 | configure_usart2_pins(pins); | |
789b23bc NF |
1708 | break; |
1709 | case AT91SAM9G45_ID_US3: | |
1710 | pdev = &at91sam9g45_uart3_device; | |
1711 | configure_usart3_pins(pins); | |
789b23bc NF |
1712 | break; |
1713 | default: | |
1714 | return; | |
1715 | } | |
2b348e2f JCPV |
1716 | pdata = pdev->dev.platform_data; |
1717 | pdata->num = portnr; /* update to mapped ID */ | |
789b23bc NF |
1718 | |
1719 | if (portnr < ATMEL_MAX_UART) | |
1720 | at91_uarts[portnr] = pdev; | |
1721 | } | |
1722 | ||
1723 | void __init at91_set_serial_console(unsigned portnr) | |
1724 | { | |
bd602995 | 1725 | if (portnr < ATMEL_MAX_UART) { |
789b23bc | 1726 | atmel_default_console_device = at91_uarts[portnr]; |
5c1f9668 | 1727 | at91sam9g45_set_console_clock(at91_uarts[portnr]->id); |
bd602995 | 1728 | } |
789b23bc NF |
1729 | } |
1730 | ||
1731 | void __init at91_add_device_serial(void) | |
1732 | { | |
1733 | int i; | |
1734 | ||
1735 | for (i = 0; i < ATMEL_MAX_UART; i++) { | |
1736 | if (at91_uarts[i]) | |
1737 | platform_device_register(at91_uarts[i]); | |
1738 | } | |
1739 | ||
1740 | if (!atmel_default_console_device) | |
1741 | printk(KERN_INFO "AT91: No default serial console defined.\n"); | |
1742 | } | |
1743 | #else | |
1744 | void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {} | |
1745 | void __init at91_set_serial_console(unsigned portnr) {} | |
1746 | void __init at91_add_device_serial(void) {} | |
1747 | #endif | |
1748 | ||
1749 | ||
1750 | /* -------------------------------------------------------------------- */ | |
1751 | /* | |
1752 | * These devices are always present and don't need any board-specific | |
1753 | * setup. | |
1754 | */ | |
1755 | static int __init at91_add_standard_devices(void) | |
1756 | { | |
40262b2b | 1757 | at91_add_device_hdmac(); |
789b23bc NF |
1758 | at91_add_device_rtc(); |
1759 | at91_add_device_rtt(); | |
237a62a1 | 1760 | at91_add_device_trng(); |
789b23bc NF |
1761 | at91_add_device_watchdog(); |
1762 | at91_add_device_tc(); | |
1763 | return 0; | |
1764 | } | |
1765 | ||
1766 | arch_initcall(at91_add_standard_devices); |