[deliverable/linux.git] / arch / arm / mach-at91 / at91sam9rl.c

/*
 * arch/arm/mach-at91/at91sam9rl.c
 *
 *  Copyright (C) 2005 SAN People
 *  Copyright (C) 2007 Atmel Corporation
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file COPYING in the main directory of this archive for
 * more details.
 */

#include <linux/module.h>
#include <linux/clk/at91_pmc.h>

#include <asm/proc-fns.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/system_misc.h>
#include <mach/cpu.h>
#include <mach/at91_dbgu.h>
#include <mach/at91sam9rl.h>
#include <mach/hardware.h>

#include "at91_aic.h"
#include "at91_rstc.h"
#include "soc.h"
#include "generic.h"
#include "sam9_smc.h"
#include "pm.h"

/* --------------------------------------------------------------------
 *  Clocks
 * -------------------------------------------------------------------- */
#if defined(CONFIG_OLD_CLK_AT91)
#include "clock.h"

/*
 * The peripheral clocks.
 */
static struct clk pioA_clk = {
	.name		= "pioA_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_PIOA,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk pioB_clk = {
	.name		= "pioB_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_PIOB,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk pioC_clk = {
	.name		= "pioC_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_PIOC,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk pioD_clk = {
	.name		= "pioD_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_PIOD,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart0_clk = {
	.name		= "usart0_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_US0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart1_clk = {
	.name		= "usart1_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_US1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart2_clk = {
	.name		= "usart2_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_US2,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart3_clk = {
	.name		= "usart3_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_US3,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk mmc_clk = {
	.name		= "mci_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_MCI,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk twi0_clk = {
	.name		= "twi0_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_TWI0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk twi1_clk = {
	.name		= "twi1_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_TWI1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk spi_clk = {
	.name		= "spi_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_SPI,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk ssc0_clk = {
	.name		= "ssc0_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_SSC0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk ssc1_clk = {
	.name		= "ssc1_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_SSC1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk tc0_clk = {
	.name		= "tc0_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_TC0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk tc1_clk = {
	.name		= "tc1_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_TC1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk tc2_clk = {
	.name		= "tc2_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_TC2,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk pwm_clk = {
	.name		= "pwm_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_PWMC,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk tsc_clk = {
	.name		= "tsc_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_TSC,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk dma_clk = {
	.name		= "dma_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_DMA,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk udphs_clk = {
	.name		= "udphs_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_UDPHS,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk lcdc_clk = {
	.name		= "lcdc_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_LCDC,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk ac97_clk = {
	.name		= "ac97_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_AC97C,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk adc_op_clk = {
	.name		= "adc_op_clk",
	.type		= CLK_TYPE_PERIPHERAL,
	.rate_hz	= 1000000,
};

static struct clk *periph_clocks[] __initdata = {
	&pioA_clk,
	&pioB_clk,
	&pioC_clk,
	&pioD_clk,
	&usart0_clk,
	&usart1_clk,
	&usart2_clk,
	&usart3_clk,
	&mmc_clk,
	&twi0_clk,
	&twi1_clk,
	&spi_clk,
	&ssc0_clk,
	&ssc1_clk,
	&tc0_clk,
	&tc1_clk,
	&tc2_clk,
	&pwm_clk,
	&tsc_clk,
	&dma_clk,
	&udphs_clk,
	&lcdc_clk,
	&ac97_clk,
	&adc_op_clk,
	// irq0
};

static struct clk_lookup periph_clocks_lookups[] = {
	CLKDEV_CON_DEV_ID("hclk", "at91sam9rl-lcdfb.0", &lcdc_clk),
	CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
	CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
	CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
	CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
	CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
	CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk),
	CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
	CLKDEV_CON_DEV_ID("pclk", "fffc0000.ssc", &ssc0_clk),
	CLKDEV_CON_DEV_ID("pclk", "fffc4000.ssc", &ssc1_clk),
	CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.0", &twi0_clk),
	CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.1", &twi1_clk),
	CLKDEV_CON_DEV_ID(NULL, "at91sam9rl-pwm", &pwm_clk),
	CLKDEV_CON_ID("pioA", &pioA_clk),
	CLKDEV_CON_ID("pioB", &pioB_clk),
	CLKDEV_CON_ID("pioC", &pioC_clk),
	CLKDEV_CON_ID("pioD", &pioD_clk),
	/* more lookup table for DT entries */
	CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
	CLKDEV_CON_DEV_ID("usart", "fffb0000.serial", &usart0_clk),
	CLKDEV_CON_DEV_ID("usart", "ffffb400.serial", &usart1_clk),
	CLKDEV_CON_DEV_ID("usart", "ffffb800.serial", &usart2_clk),
	CLKDEV_CON_DEV_ID("usart", "ffffbc00.serial", &usart3_clk),
	CLKDEV_CON_DEV_ID("t0_clk", "fffa0000.timer", &tc0_clk),
	CLKDEV_CON_DEV_ID("t1_clk", "fffa0000.timer", &tc1_clk),
	CLKDEV_CON_DEV_ID("t2_clk", "fffa0000.timer", &tc2_clk),
	CLKDEV_CON_DEV_ID("mci_clk", "fffa4000.mmc", &mmc_clk),
	CLKDEV_CON_DEV_ID(NULL, "fffa8000.i2c", &twi0_clk),
	CLKDEV_CON_DEV_ID(NULL, "fffac000.i2c", &twi1_clk),
	CLKDEV_CON_DEV_ID(NULL, "fffc8000.pwm", &pwm_clk),
	CLKDEV_CON_DEV_ID(NULL, "ffffc800.pwm", &pwm_clk),
	CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioA_clk),
	CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioB_clk),
	CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioC_clk),
	CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioD_clk),
	CLKDEV_CON_ID("adc_clk", &tsc_clk),
};

static struct clk_lookup usart_clocks_lookups[] = {
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
};

/*
 * The two programmable clocks.
 * You must configure pin multiplexing to bring these signals out.
 */
static struct clk pck0 = {
	.name		= "pck0",
	.pmc_mask	= AT91_PMC_PCK0,
	.type		= CLK_TYPE_PROGRAMMABLE,
	.id		= 0,
};
static struct clk pck1 = {
	.name		= "pck1",
	.pmc_mask	= AT91_PMC_PCK1,
	.type		= CLK_TYPE_PROGRAMMABLE,
	.id		= 1,
};

static void __init at91sam9rl_register_clocks(void)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
		clk_register(periph_clocks[i]);

	clkdev_add_table(periph_clocks_lookups,
			 ARRAY_SIZE(periph_clocks_lookups));
	clkdev_add_table(usart_clocks_lookups,
			 ARRAY_SIZE(usart_clocks_lookups));

	clk_register(&pck0);
	clk_register(&pck1);
}
#endif

/* --------------------------------------------------------------------
 *  GPIO
 * -------------------------------------------------------------------- */

static struct at91_gpio_bank at91sam9rl_gpio[] __initdata = {
	{
		.id		= AT91SAM9RL_ID_PIOA,
		.regbase	= AT91SAM9RL_BASE_PIOA,
	}, {
		.id		= AT91SAM9RL_ID_PIOB,
		.regbase	= AT91SAM9RL_BASE_PIOB,
	}, {
		.id		= AT91SAM9RL_ID_PIOC,
		.regbase	= AT91SAM9RL_BASE_PIOC,
	}, {
		.id		= AT91SAM9RL_ID_PIOD,
		.regbase	= AT91SAM9RL_BASE_PIOD,
	}
};

/* --------------------------------------------------------------------
 *  AT91SAM9RL processor initialization
 * -------------------------------------------------------------------- */

static void __init at91sam9rl_map_io(void)
{
	unsigned long sram_size;

	switch (at91_soc_initdata.cidr & AT91_CIDR_SRAMSIZ) {
		case AT91_CIDR_SRAMSIZ_32K:
			sram_size = 2 * SZ_16K;
			break;
		case AT91_CIDR_SRAMSIZ_16K:
		default:
			sram_size = SZ_16K;
	}

	/* Map SRAM */
	at91_init_sram(0, AT91SAM9RL_SRAM_BASE, sram_size);
}

static void __init at91sam9rl_ioremap_registers(void)
{
	at91_ioremap_shdwc(AT91SAM9RL_BASE_SHDWC);
	at91_ioremap_rstc(AT91SAM9RL_BASE_RSTC);
	at91_ioremap_ramc(0, AT91SAM9RL_BASE_SDRAMC, 512);
	at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT);
	at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC);
	at91_ioremap_matrix(AT91SAM9RL_BASE_MATRIX);
	at91_pm_set_standby(at91sam9_sdram_standby);
}

static void __init at91sam9rl_initialize(void)
{
	arm_pm_idle = at91sam9_idle;
	arm_pm_restart = at91sam9_alt_restart;

	at91_sysirq_mask_rtc(AT91SAM9RL_BASE_RTC);
	at91_sysirq_mask_rtt(AT91SAM9RL_BASE_RTT);

	/* Register GPIO subsystem */
	at91_gpio_init(at91sam9rl_gpio, 4);
}

/* --------------------------------------------------------------------
 *  Interrupt initialization
 * -------------------------------------------------------------------- */

/*
 * The default interrupt priority levels (0 = lowest, 7 = highest).
 */
static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = {
	7,	/* Advanced Interrupt Controller */
	7,	/* System Peripherals */
	1,	/* Parallel IO Controller A */
	1,	/* Parallel IO Controller B */
	1,	/* Parallel IO Controller C */
	1,	/* Parallel IO Controller D */
	5,	/* USART 0 */
	5,	/* USART 1 */
	5,	/* USART 2 */
	5,	/* USART 3 */
	0,	/* Multimedia Card Interface */
	6,	/* Two-Wire Interface 0 */
	6,	/* Two-Wire Interface 1 */
	5,	/* Serial Peripheral Interface */
	4,	/* Serial Synchronous Controller 0 */
	4,	/* Serial Synchronous Controller 1 */
	0,	/* Timer Counter 0 */
	0,	/* Timer Counter 1 */
	0,	/* Timer Counter 2 */
	0,
	0,	/* Touch Screen Controller */
	0,	/* DMA Controller */
	2,	/* USB Device High speed port */
	2,	/* LCD Controller */
	6,	/* AC97 Controller */
	0,
	0,
	0,
	0,
	0,
	0,
	0,	/* Advanced Interrupt Controller */
};

AT91_SOC_START(at91sam9rl)
	.map_io = at91sam9rl_map_io,
	.default_irq_priority = at91sam9rl_default_irq_priority,
	.extern_irq = (1 << AT91SAM9RL_ID_IRQ0),
	.ioremap_registers = at91sam9rl_ioremap_registers,
#if defined(CONFIG_OLD_CLK_AT91)
	.register_clocks = at91sam9rl_register_clocks,
#endif
	.init = at91sam9rl_initialize,
AT91_SOC_END
Commit	Line	Data
877d7720 AV	1	/*
	2	* arch/arm/mach-at91/at91sam9rl.c
	3	*
	4	* Copyright (C) 2005 SAN People
	5	* Copyright (C) 2007 Atmel Corporation
	6	*
	7	* This file is subject to the terms and conditions of the GNU General Public
	8	* License. See the file COPYING in the main directory of this archive for
	9	* more details.
	10	*/
	11
	12	#include <linux/module.h>
2edb90ae	13	#include <linux/clk/at91_pmc.h>
877d7720	14
c9dfafba	15	#include <asm/proc-fns.h>
80b02c17	16	#include <asm/irq.h>
877d7720 AV	17	#include <asm/mach/arch.h>
877d7720 AV	18	#include <asm/mach/map.h>
9f97da78	19	#include <asm/system_misc.h>
a09e64fb	20	#include <mach/cpu.h>
8c3583b6	21	#include <mach/at91_dbgu.h>
a09e64fb	22	#include <mach/at91sam9rl.h>
ac11a1d4	23	#include <mach/hardware.h>
877d7720	24
a510b9ba	25	#include "at91_aic.h"
f0995d08	26	#include "at91_rstc.h"
21d08b9d	27	#include "soc.h"
877d7720	28	#include "generic.h"
faee0cc3	29	#include "sam9_smc.h"
5ad945ea	30	#include "pm.h"
877d7720	31
877d7720 AV	32	/* --------------------------------------------------------------------
	33	* Clocks
	34	* -------------------------------------------------------------------- */
72a3fe97 AB	35	#if defined(CONFIG_OLD_CLK_AT91)
72a3fe97 AB	36	#include "clock.h"
877d7720 AV	37
	38	/*
	39	* The peripheral clocks.
	40	*/
	41	static struct clk pioA_clk = {
	42	.name = "pioA_clk",
	43	.pmc_mask = 1 << AT91SAM9RL_ID_PIOA,
	44	.type = CLK_TYPE_PERIPHERAL,
	45	};
	46	static struct clk pioB_clk = {
	47	.name = "pioB_clk",
	48	.pmc_mask = 1 << AT91SAM9RL_ID_PIOB,
	49	.type = CLK_TYPE_PERIPHERAL,
	50	};
	51	static struct clk pioC_clk = {
	52	.name = "pioC_clk",
	53	.pmc_mask = 1 << AT91SAM9RL_ID_PIOC,
	54	.type = CLK_TYPE_PERIPHERAL,
	55	};
	56	static struct clk pioD_clk = {
	57	.name = "pioD_clk",
	58	.pmc_mask = 1 << AT91SAM9RL_ID_PIOD,
	59	.type = CLK_TYPE_PERIPHERAL,
	60	};
	61	static struct clk usart0_clk = {
	62	.name = "usart0_clk",
	63	.pmc_mask = 1 << AT91SAM9RL_ID_US0,
	64	.type = CLK_TYPE_PERIPHERAL,
	65	};
	66	static struct clk usart1_clk = {
	67	.name = "usart1_clk",
	68	.pmc_mask = 1 << AT91SAM9RL_ID_US1,
	69	.type = CLK_TYPE_PERIPHERAL,
	70	};
	71	static struct clk usart2_clk = {
	72	.name = "usart2_clk",
	73	.pmc_mask = 1 << AT91SAM9RL_ID_US2,
	74	.type = CLK_TYPE_PERIPHERAL,
	75	};
	76	static struct clk usart3_clk = {
	77	.name = "usart3_clk",
	78	.pmc_mask = 1 << AT91SAM9RL_ID_US3,
	79	.type = CLK_TYPE_PERIPHERAL,
	80	};
	81	static struct clk mmc_clk = {
	82	.name = "mci_clk",
	83	.pmc_mask = 1 << AT91SAM9RL_ID_MCI,
	84	.type = CLK_TYPE_PERIPHERAL,
	85	};
	86	static struct clk twi0_clk = {
	87	.name = "twi0_clk",
	88	.pmc_mask = 1 << AT91SAM9RL_ID_TWI0,
	89	.type = CLK_TYPE_PERIPHERAL,
	90	};
	91	static struct clk twi1_clk = {
	92	.name = "twi1_clk",
	93	.pmc_mask = 1 << AT91SAM9RL_ID_TWI1,
	94	.type = CLK_TYPE_PERIPHERAL,
	95	};
	96	static struct clk spi_clk = {
	97	.name = "spi_clk",
	98	.pmc_mask = 1 << AT91SAM9RL_ID_SPI,
	99	.type = CLK_TYPE_PERIPHERAL,
	100	};
101	static struct clk ssc0_clk = {
102	.name = "ssc0_clk",
103	.pmc_mask = 1 << AT91SAM9RL_ID_SSC0,
104	.type = CLK_TYPE_PERIPHERAL,
105	};
106	static struct clk ssc1_clk = {
107	.name = "ssc1_clk",
108	.pmc_mask = 1 << AT91SAM9RL_ID_SSC1,
109	.type = CLK_TYPE_PERIPHERAL,
110	};
111	static struct clk tc0_clk = {
112	.name = "tc0_clk",
113	.pmc_mask = 1 << AT91SAM9RL_ID_TC0,
114	.type = CLK_TYPE_PERIPHERAL,
115	};
116	static struct clk tc1_clk = {
117	.name = "tc1_clk",
118	.pmc_mask = 1 << AT91SAM9RL_ID_TC1,
119	.type = CLK_TYPE_PERIPHERAL,
120	};
121	static struct clk tc2_clk = {
122	.name = "tc2_clk",
123	.pmc_mask = 1 << AT91SAM9RL_ID_TC2,
124	.type = CLK_TYPE_PERIPHERAL,
125	};
bb1ad68b AV	126	static struct clk pwm_clk = {
bb1ad68b AV	127	.name = "pwm_clk",
877d7720 AV	128	.pmc_mask = 1 << AT91SAM9RL_ID_PWMC,
	129	.type = CLK_TYPE_PERIPHERAL,
	130	};
	131	static struct clk tsc_clk = {
	132	.name = "tsc_clk",
	133	.pmc_mask = 1 << AT91SAM9RL_ID_TSC,
	134	.type = CLK_TYPE_PERIPHERAL,
	135	};
	136	static struct clk dma_clk = {
	137	.name = "dma_clk",
	138	.pmc_mask = 1 << AT91SAM9RL_ID_DMA,
	139	.type = CLK_TYPE_PERIPHERAL,
	140	};
	141	static struct clk udphs_clk = {
	142	.name = "udphs_clk",
	143	.pmc_mask = 1 << AT91SAM9RL_ID_UDPHS,
	144	.type = CLK_TYPE_PERIPHERAL,
	145	};
	146	static struct clk lcdc_clk = {
	147	.name = "lcdc_clk",
	148	.pmc_mask = 1 << AT91SAM9RL_ID_LCDC,
	149	.type = CLK_TYPE_PERIPHERAL,
	150	};
	151	static struct clk ac97_clk = {
	152	.name = "ac97_clk",
	153	.pmc_mask = 1 << AT91SAM9RL_ID_AC97C,
	154	.type = CLK_TYPE_PERIPHERAL,
	155	};
b8ba9a40 AB	156	static struct clk adc_op_clk = {
	157	.name = "adc_op_clk",
	158	.type = CLK_TYPE_PERIPHERAL,
	159	.rate_hz = 1000000,
	160	};
877d7720 AV	161
	162	static struct clk *periph_clocks[] __initdata = {
	163	&pioA_clk,
	164	&pioB_clk,
	165	&pioC_clk,
	166	&pioD_clk,
	167	&usart0_clk,
	168	&usart1_clk,
	169	&usart2_clk,
	170	&usart3_clk,
	171	&mmc_clk,
	172	&twi0_clk,
	173	&twi1_clk,
	174	&spi_clk,
	175	&ssc0_clk,
	176	&ssc1_clk,
	177	&tc0_clk,
	178	&tc1_clk,
	179	&tc2_clk,
bb1ad68b	180	&pwm_clk,
877d7720 AV	181	&tsc_clk,
	182	&dma_clk,
	183	&udphs_clk,
	184	&lcdc_clk,
	185	&ac97_clk,
b8ba9a40	186	&adc_op_clk,
877d7720 AV	187	// irq0
	188	};
	189
bd602995	190	static struct clk_lookup periph_clocks_lookups[] = {
bbd44f6b	191	CLKDEV_CON_DEV_ID("hclk", "at91sam9rl-lcdfb.0", &lcdc_clk),
9d87159e JCPV	192	CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
9d87159e JCPV	193	CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
bd602995 JCPV	194	CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
	195	CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
	196	CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
636036d2 BS	197	CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk),
636036d2 BS	198	CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
099343c6 BS	199	CLKDEV_CON_DEV_ID("pclk", "fffc0000.ssc", &ssc0_clk),
099343c6 BS	200	CLKDEV_CON_DEV_ID("pclk", "fffc4000.ssc", &ssc1_clk),
fac368a0 NV	201	CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.0", &twi0_clk),
fac368a0 NV	202	CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.1", &twi1_clk),
60c07f5e	203	CLKDEV_CON_DEV_ID(NULL, "at91sam9rl-pwm", &pwm_clk),
619d4a4b JCPV	204	CLKDEV_CON_ID("pioA", &pioA_clk),
	205	CLKDEV_CON_ID("pioB", &pioB_clk),
	206	CLKDEV_CON_ID("pioC", &pioC_clk),
	207	CLKDEV_CON_ID("pioD", &pioD_clk),
09ab012a AB	208	/* more lookup table for DT entries */
	209	CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
	210	CLKDEV_CON_DEV_ID("usart", "fffb0000.serial", &usart0_clk),
	211	CLKDEV_CON_DEV_ID("usart", "ffffb400.serial", &usart1_clk),
	212	CLKDEV_CON_DEV_ID("usart", "ffffb800.serial", &usart2_clk),
	213	CLKDEV_CON_DEV_ID("usart", "ffffbc00.serial", &usart3_clk),
	214	CLKDEV_CON_DEV_ID("t0_clk", "fffa0000.timer", &tc0_clk),
	215	CLKDEV_CON_DEV_ID("t1_clk", "fffa0000.timer", &tc1_clk),
	216	CLKDEV_CON_DEV_ID("t2_clk", "fffa0000.timer", &tc2_clk),
	217	CLKDEV_CON_DEV_ID("mci_clk", "fffa4000.mmc", &mmc_clk),
	218	CLKDEV_CON_DEV_ID(NULL, "fffa8000.i2c", &twi0_clk),
	219	CLKDEV_CON_DEV_ID(NULL, "fffac000.i2c", &twi1_clk),
050208df	220	CLKDEV_CON_DEV_ID(NULL, "fffc8000.pwm", &pwm_clk),
09ab012a AB	221	CLKDEV_CON_DEV_ID(NULL, "ffffc800.pwm", &pwm_clk),
	222	CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioA_clk),
	223	CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioB_clk),
	224	CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioC_clk),
	225	CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioD_clk),
b8ba9a40	226	CLKDEV_CON_ID("adc_clk", &tsc_clk),
bd602995 JCPV	227	};
	228
	229	static struct clk_lookup usart_clocks_lookups[] = {
	230	CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
	231	CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
	232	CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
	233	CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
	234	CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
	235	};
	236
877d7720 AV	237	/*
	238	* The two programmable clocks.
	239	* You must configure pin multiplexing to bring these signals out.
	240	*/
	241	static struct clk pck0 = {
	242	.name = "pck0",
	243	.pmc_mask = AT91_PMC_PCK0,
	244	.type = CLK_TYPE_PROGRAMMABLE,
	245	.id = 0,
	246	};
	247	static struct clk pck1 = {
	248	.name = "pck1",
	249	.pmc_mask = AT91_PMC_PCK1,
	250	.type = CLK_TYPE_PROGRAMMABLE,
	251	.id = 1,
	252	};
	253
	254	static void __init at91sam9rl_register_clocks(void)
	255	{
	256	int i;
	257
	258	for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
	259	clk_register(periph_clocks[i]);
	260
bd602995 JCPV	261	clkdev_add_table(periph_clocks_lookups,
	262	ARRAY_SIZE(periph_clocks_lookups));
	263	clkdev_add_table(usart_clocks_lookups,
	264	ARRAY_SIZE(usart_clocks_lookups));
	265
877d7720 AV	266	clk_register(&pck0);
	267	clk_register(&pck1);
	268	}
72a3fe97	269	#endif
877d7720 AV	270
	271	/* --------------------------------------------------------------------
	272	* GPIO
	273	* -------------------------------------------------------------------- */
	274
1a2d9156	275	static struct at91_gpio_bank at91sam9rl_gpio[] __initdata = {
877d7720 AV	276	{
877d7720 AV	277	.id = AT91SAM9RL_ID_PIOA,
80e91cb8	278	.regbase = AT91SAM9RL_BASE_PIOA,
877d7720 AV	279	}, {
877d7720 AV	280	.id = AT91SAM9RL_ID_PIOB,
80e91cb8	281	.regbase = AT91SAM9RL_BASE_PIOB,
877d7720 AV	282	}, {
877d7720 AV	283	.id = AT91SAM9RL_ID_PIOC,
80e91cb8	284	.regbase = AT91SAM9RL_BASE_PIOC,
877d7720 AV	285	}, {
877d7720 AV	286	.id = AT91SAM9RL_ID_PIOD,
80e91cb8	287	.regbase = AT91SAM9RL_BASE_PIOD,
877d7720 AV	288	}
	289	};
	290
877d7720 AV	291	/* --------------------------------------------------------------------
	292	* AT91SAM9RL processor initialization
	293	* -------------------------------------------------------------------- */
	294
21d08b9d	295	static void __init at91sam9rl_map_io(void)
877d7720	296	{
8c3583b6	297	unsigned long sram_size;
877d7720	298
8c3583b6	299	switch (at91_soc_initdata.cidr & AT91_CIDR_SRAMSIZ) {
877d7720 AV	300	case AT91_CIDR_SRAMSIZ_32K:
	301	sram_size = 2 * SZ_16K;
	302	break;
	303	case AT91_CIDR_SRAMSIZ_16K:
	304	default:
	305	sram_size = SZ_16K;
	306	}
	307
877d7720	308	/* Map SRAM */
f0051d82	309	at91_init_sram(0, AT91SAM9RL_SRAM_BASE, sram_size);
1b021a3b	310	}
877d7720	311
cfa5a1fe JCPV	312	static void __init at91sam9rl_ioremap_registers(void)
cfa5a1fe JCPV	313	{
f22deee5	314	at91_ioremap_shdwc(AT91SAM9RL_BASE_SHDWC);
e9f68b5c	315	at91_ioremap_rstc(AT91SAM9RL_BASE_RSTC);
f363c407	316	at91_ioremap_ramc(0, AT91SAM9RL_BASE_SDRAMC, 512);
4ab0c599	317	at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT);
faee0cc3	318	at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC);
4342d647	319	at91_ioremap_matrix(AT91SAM9RL_BASE_MATRIX);
6b625891	320	at91_pm_set_standby(at91sam9_sdram_standby);
cfa5a1fe JCPV	321	}
cfa5a1fe JCPV	322
46539374	323	static void __init at91sam9rl_initialize(void)
1b021a3b	324	{
0d781716	325	arm_pm_idle = at91sam9_idle;
1b2073e7	326	arm_pm_restart = at91sam9_alt_restart;
877d7720	327
6de714c2	328	at91_sysirq_mask_rtc(AT91SAM9RL_BASE_RTC);
94c4c79f	329	at91_sysirq_mask_rtt(AT91SAM9RL_BASE_RTT);
6de714c2	330
877d7720 AV	331	/* Register GPIO subsystem */
	332	at91_gpio_init(at91sam9rl_gpio, 4);
	333	}
	334
	335	/* --------------------------------------------------------------------
	336	* Interrupt initialization
	337	* -------------------------------------------------------------------- */
	338
	339	/*
	340	* The default interrupt priority levels (0 = lowest, 7 = highest).
	341	*/
	342	static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = {
	343	7, /* Advanced Interrupt Controller */
	344	7, /* System Peripherals */
	345	1, /* Parallel IO Controller A */
	346	1, /* Parallel IO Controller B */
	347	1, /* Parallel IO Controller C */
	348	1, /* Parallel IO Controller D */
	349	5, /* USART 0 */
	350	5, /* USART 1 */
	351	5, /* USART 2 */
	352	5, /* USART 3 */
	353	0, /* Multimedia Card Interface */
	354	6, /* Two-Wire Interface 0 */
	355	6, /* Two-Wire Interface 1 */
	356	5, /* Serial Peripheral Interface */
	357	4, /* Serial Synchronous Controller 0 */
	358	4, /* Serial Synchronous Controller 1 */
	359	0, /* Timer Counter 0 */
	360	0, /* Timer Counter 1 */
	361	0, /* Timer Counter 2 */
	362	0,
	363	0, /* Touch Screen Controller */
	364	0, /* DMA Controller */
	365	2, /* USB Device High speed port */
	366	2, /* LCD Controller */
	367	6, /* AC97 Controller */
	368	0,
	369	0,
	370	0,
	371	0,
	372	0,
	373	0,
	374	0, /* Advanced Interrupt Controller */
	375	};
	376
84ddb087	377	AT91_SOC_START(at91sam9rl)
21d08b9d	378	.map_io = at91sam9rl_map_io,
92100c12	379	.default_irq_priority = at91sam9rl_default_irq_priority,
546c830c	380	.extern_irq = (1 << AT91SAM9RL_ID_IRQ0),
cfa5a1fe	381	.ioremap_registers = at91sam9rl_ioremap_registers,
72a3fe97	382	#if defined(CONFIG_OLD_CLK_AT91)
51ddec76	383	.register_clocks = at91sam9rl_register_clocks,
72a3fe97	384	#endif
21d08b9d	385	.init = at91sam9rl_initialize,
8d39e0fd	386	AT91_SOC_END