[deliverable/linux.git] / arch / arm / mach-at91 / at91sam9rl.c

/*
 * arch/arm/mach-at91/at91sam9rl.c
 *
 *  Copyright (C) 2005 SAN People
 *  Copyright (C) 2007 Atmel Corporation
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file COPYING in the main directory of this archive for
 * more details.
 */

#include <linux/module.h>

#include <asm/proc-fns.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <mach/cpu.h>
#include <mach/at91_dbgu.h>
#include <mach/at91sam9rl.h>
#include <mach/at91_pmc.h>
#include <mach/at91_rstc.h>

#include "soc.h"
#include "generic.h"
#include "clock.h"
#include "sam9_smc.h"

/* --------------------------------------------------------------------
 *  Clocks
 * -------------------------------------------------------------------- */

/*
 * The peripheral clocks.
 */
static struct clk pioA_clk = {
	.name		= "pioA_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_PIOA,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk pioB_clk = {
	.name		= "pioB_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_PIOB,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk pioC_clk = {
	.name		= "pioC_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_PIOC,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk pioD_clk = {
	.name		= "pioD_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_PIOD,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart0_clk = {
	.name		= "usart0_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_US0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart1_clk = {
	.name		= "usart1_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_US1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart2_clk = {
	.name		= "usart2_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_US2,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart3_clk = {
	.name		= "usart3_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_US3,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk mmc_clk = {
	.name		= "mci_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_MCI,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk twi0_clk = {
	.name		= "twi0_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_TWI0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk twi1_clk = {
	.name		= "twi1_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_TWI1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk spi_clk = {
	.name		= "spi_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_SPI,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk ssc0_clk = {
	.name		= "ssc0_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_SSC0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk ssc1_clk = {
	.name		= "ssc1_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_SSC1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk tc0_clk = {
	.name		= "tc0_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_TC0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk tc1_clk = {
	.name		= "tc1_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_TC1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk tc2_clk = {
	.name		= "tc2_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_TC2,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk pwm_clk = {
	.name		= "pwm_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_PWMC,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk tsc_clk = {
	.name		= "tsc_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_TSC,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk dma_clk = {
	.name		= "dma_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_DMA,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk udphs_clk = {
	.name		= "udphs_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_UDPHS,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk lcdc_clk = {
	.name		= "lcdc_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_LCDC,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk ac97_clk = {
	.name		= "ac97_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_AC97C,
	.type		= CLK_TYPE_PERIPHERAL,
};

static struct clk *periph_clocks[] __initdata = {
	&pioA_clk,
	&pioB_clk,
	&pioC_clk,
	&pioD_clk,
	&usart0_clk,
	&usart1_clk,
	&usart2_clk,
	&usart3_clk,
	&mmc_clk,
	&twi0_clk,
	&twi1_clk,
	&spi_clk,
	&ssc0_clk,
	&ssc1_clk,
	&tc0_clk,
	&tc1_clk,
	&tc2_clk,
	&pwm_clk,
	&tsc_clk,
	&dma_clk,
	&udphs_clk,
	&lcdc_clk,
	&ac97_clk,
	// irq0
};

static struct clk_lookup periph_clocks_lookups[] = {
	CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
	CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
	CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
	CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
	CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
	CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
	CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
	CLKDEV_CON_ID("pioA", &pioA_clk),
	CLKDEV_CON_ID("pioB", &pioB_clk),
	CLKDEV_CON_ID("pioC", &pioC_clk),
	CLKDEV_CON_ID("pioD", &pioD_clk),
};

static struct clk_lookup usart_clocks_lookups[] = {
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
};

/*
 * The two programmable clocks.
 * You must configure pin multiplexing to bring these signals out.
 */
static struct clk pck0 = {
	.name		= "pck0",
	.pmc_mask	= AT91_PMC_PCK0,
	.type		= CLK_TYPE_PROGRAMMABLE,
	.id		= 0,
};
static struct clk pck1 = {
	.name		= "pck1",
	.pmc_mask	= AT91_PMC_PCK1,
	.type		= CLK_TYPE_PROGRAMMABLE,
	.id		= 1,
};

static void __init at91sam9rl_register_clocks(void)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
		clk_register(periph_clocks[i]);

	clkdev_add_table(periph_clocks_lookups,
			 ARRAY_SIZE(periph_clocks_lookups));
	clkdev_add_table(usart_clocks_lookups,
			 ARRAY_SIZE(usart_clocks_lookups));

	clk_register(&pck0);
	clk_register(&pck1);
}

static struct clk_lookup console_clock_lookup;

void __init at91sam9rl_set_console_clock(int id)
{
	if (id >= ARRAY_SIZE(usart_clocks_lookups))
		return;

	console_clock_lookup.con_id = "usart";
	console_clock_lookup.clk = usart_clocks_lookups[id].clk;
	clkdev_add(&console_clock_lookup);
}

/* --------------------------------------------------------------------
 *  GPIO
 * -------------------------------------------------------------------- */

static struct at91_gpio_bank at91sam9rl_gpio[] __initdata = {
	{
		.id		= AT91SAM9RL_ID_PIOA,
		.regbase	= AT91SAM9RL_BASE_PIOA,
	}, {
		.id		= AT91SAM9RL_ID_PIOB,
		.regbase	= AT91SAM9RL_BASE_PIOB,
	}, {
		.id		= AT91SAM9RL_ID_PIOC,
		.regbase	= AT91SAM9RL_BASE_PIOC,
	}, {
		.id		= AT91SAM9RL_ID_PIOD,
		.regbase	= AT91SAM9RL_BASE_PIOD,
	}
};

/* --------------------------------------------------------------------
 *  AT91SAM9RL processor initialization
 * -------------------------------------------------------------------- */

static void __init at91sam9rl_map_io(void)
{
	unsigned long sram_size;

	switch (at91_soc_initdata.cidr & AT91_CIDR_SRAMSIZ) {
		case AT91_CIDR_SRAMSIZ_32K:
			sram_size = 2 * SZ_16K;
			break;
		case AT91_CIDR_SRAMSIZ_16K:
		default:
			sram_size = SZ_16K;
	}

	/* Map SRAM */
	at91_init_sram(0, AT91SAM9RL_SRAM_BASE, sram_size);
}

static void __init at91sam9rl_ioremap_registers(void)
{
	at91_ioremap_shdwc(AT91SAM9RL_BASE_SHDWC);
	at91_ioremap_rstc(AT91SAM9RL_BASE_RSTC);
	at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT);
	at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC);
}

static void at91sam9rl_idle(void)
{
	at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
	cpu_do_idle();
}

static void __init at91sam9rl_initialize(void)
{
	arm_pm_idle = at91sam9rl_idle;
	arm_pm_restart = at91sam9_alt_restart;
	at91_extern_irq = (1 << AT91SAM9RL_ID_IRQ0);

	/* Register GPIO subsystem */
	at91_gpio_init(at91sam9rl_gpio, 4);
}

/* --------------------------------------------------------------------
 *  Interrupt initialization
 * -------------------------------------------------------------------- */

/*
 * The default interrupt priority levels (0 = lowest, 7 = highest).
 */
static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = {
	7,	/* Advanced Interrupt Controller */
	7,	/* System Peripherals */
	1,	/* Parallel IO Controller A */
	1,	/* Parallel IO Controller B */
	1,	/* Parallel IO Controller C */
	1,	/* Parallel IO Controller D */
	5,	/* USART 0 */
	5,	/* USART 1 */
	5,	/* USART 2 */
	5,	/* USART 3 */
	0,	/* Multimedia Card Interface */
	6,	/* Two-Wire Interface 0 */
	6,	/* Two-Wire Interface 1 */
	5,	/* Serial Peripheral Interface */
	4,	/* Serial Synchronous Controller 0 */
	4,	/* Serial Synchronous Controller 1 */
	0,	/* Timer Counter 0 */
	0,	/* Timer Counter 1 */
	0,	/* Timer Counter 2 */
	0,
	0,	/* Touch Screen Controller */
	0,	/* DMA Controller */
	2,	/* USB Device High speed port */
	2,	/* LCD Controller */
	6,	/* AC97 Controller */
	0,
	0,
	0,
	0,
	0,
	0,
	0,	/* Advanced Interrupt Controller */
};

struct at91_init_soc __initdata at91sam9rl_soc = {
	.map_io = at91sam9rl_map_io,
	.default_irq_priority = at91sam9rl_default_irq_priority,
	.ioremap_registers = at91sam9rl_ioremap_registers,
	.register_clocks = at91sam9rl_register_clocks,
	.init = at91sam9rl_initialize,
};
Commit	Line	Data
877d7720 AV	1	/*
	2	* arch/arm/mach-at91/at91sam9rl.c
	3	*
	4	* Copyright (C) 2005 SAN People
	5	* Copyright (C) 2007 Atmel Corporation
	6	*
	7	* This file is subject to the terms and conditions of the GNU General Public
	8	* License. See the file COPYING in the main directory of this archive for
	9	* more details.
	10	*/
	11
	12	#include <linux/module.h>
	13
c9dfafba	14	#include <asm/proc-fns.h>
80b02c17	15	#include <asm/irq.h>
877d7720 AV	16	#include <asm/mach/arch.h>
877d7720 AV	17	#include <asm/mach/map.h>
a09e64fb	18	#include <mach/cpu.h>
8c3583b6	19	#include <mach/at91_dbgu.h>
a09e64fb RK	20	#include <mach/at91sam9rl.h>
	21	#include <mach/at91_pmc.h>
	22	#include <mach/at91_rstc.h>
877d7720	23
21d08b9d	24	#include "soc.h"
877d7720 AV	25	#include "generic.h"
877d7720 AV	26	#include "clock.h"
faee0cc3	27	#include "sam9_smc.h"
877d7720	28
877d7720 AV	29	/* --------------------------------------------------------------------
	30	* Clocks
	31	* -------------------------------------------------------------------- */
	32
	33	/*
	34	* The peripheral clocks.
	35	*/
	36	static struct clk pioA_clk = {
	37	.name = "pioA_clk",
	38	.pmc_mask = 1 << AT91SAM9RL_ID_PIOA,
	39	.type = CLK_TYPE_PERIPHERAL,
	40	};
	41	static struct clk pioB_clk = {
	42	.name = "pioB_clk",
	43	.pmc_mask = 1 << AT91SAM9RL_ID_PIOB,
	44	.type = CLK_TYPE_PERIPHERAL,
	45	};
	46	static struct clk pioC_clk = {
	47	.name = "pioC_clk",
	48	.pmc_mask = 1 << AT91SAM9RL_ID_PIOC,
	49	.type = CLK_TYPE_PERIPHERAL,
	50	};
	51	static struct clk pioD_clk = {
	52	.name = "pioD_clk",
	53	.pmc_mask = 1 << AT91SAM9RL_ID_PIOD,
	54	.type = CLK_TYPE_PERIPHERAL,
	55	};
	56	static struct clk usart0_clk = {
	57	.name = "usart0_clk",
	58	.pmc_mask = 1 << AT91SAM9RL_ID_US0,
	59	.type = CLK_TYPE_PERIPHERAL,
	60	};
	61	static struct clk usart1_clk = {
	62	.name = "usart1_clk",
	63	.pmc_mask = 1 << AT91SAM9RL_ID_US1,
	64	.type = CLK_TYPE_PERIPHERAL,
	65	};
	66	static struct clk usart2_clk = {
	67	.name = "usart2_clk",
	68	.pmc_mask = 1 << AT91SAM9RL_ID_US2,
	69	.type = CLK_TYPE_PERIPHERAL,
	70	};
	71	static struct clk usart3_clk = {
	72	.name = "usart3_clk",
	73	.pmc_mask = 1 << AT91SAM9RL_ID_US3,
	74	.type = CLK_TYPE_PERIPHERAL,
	75	};
	76	static struct clk mmc_clk = {
	77	.name = "mci_clk",
	78	.pmc_mask = 1 << AT91SAM9RL_ID_MCI,
	79	.type = CLK_TYPE_PERIPHERAL,
	80	};
	81	static struct clk twi0_clk = {
	82	.name = "twi0_clk",
	83	.pmc_mask = 1 << AT91SAM9RL_ID_TWI0,
	84	.type = CLK_TYPE_PERIPHERAL,
	85	};
	86	static struct clk twi1_clk = {
	87	.name = "twi1_clk",
	88	.pmc_mask = 1 << AT91SAM9RL_ID_TWI1,
	89	.type = CLK_TYPE_PERIPHERAL,
	90	};
	91	static struct clk spi_clk = {
	92	.name = "spi_clk",
93	.pmc_mask = 1 << AT91SAM9RL_ID_SPI,
94	.type = CLK_TYPE_PERIPHERAL,
95	};
96	static struct clk ssc0_clk = {
97	.name = "ssc0_clk",
98	.pmc_mask = 1 << AT91SAM9RL_ID_SSC0,
99	.type = CLK_TYPE_PERIPHERAL,
100	};
101	static struct clk ssc1_clk = {
102	.name = "ssc1_clk",
103	.pmc_mask = 1 << AT91SAM9RL_ID_SSC1,
104	.type = CLK_TYPE_PERIPHERAL,
105	};
106	static struct clk tc0_clk = {
107	.name = "tc0_clk",
108	.pmc_mask = 1 << AT91SAM9RL_ID_TC0,
109	.type = CLK_TYPE_PERIPHERAL,
110	};
111	static struct clk tc1_clk = {
112	.name = "tc1_clk",
113	.pmc_mask = 1 << AT91SAM9RL_ID_TC1,
114	.type = CLK_TYPE_PERIPHERAL,
115	};
116	static struct clk tc2_clk = {
117	.name = "tc2_clk",
118	.pmc_mask = 1 << AT91SAM9RL_ID_TC2,
119	.type = CLK_TYPE_PERIPHERAL,
120	};
bb1ad68b AV	121	static struct clk pwm_clk = {
bb1ad68b AV	122	.name = "pwm_clk",
877d7720 AV	123	.pmc_mask = 1 << AT91SAM9RL_ID_PWMC,
	124	.type = CLK_TYPE_PERIPHERAL,
	125	};
	126	static struct clk tsc_clk = {
	127	.name = "tsc_clk",
	128	.pmc_mask = 1 << AT91SAM9RL_ID_TSC,
	129	.type = CLK_TYPE_PERIPHERAL,
	130	};
	131	static struct clk dma_clk = {
	132	.name = "dma_clk",
	133	.pmc_mask = 1 << AT91SAM9RL_ID_DMA,
	134	.type = CLK_TYPE_PERIPHERAL,
	135	};
	136	static struct clk udphs_clk = {
	137	.name = "udphs_clk",
	138	.pmc_mask = 1 << AT91SAM9RL_ID_UDPHS,
	139	.type = CLK_TYPE_PERIPHERAL,
	140	};
	141	static struct clk lcdc_clk = {
	142	.name = "lcdc_clk",
	143	.pmc_mask = 1 << AT91SAM9RL_ID_LCDC,
	144	.type = CLK_TYPE_PERIPHERAL,
	145	};
	146	static struct clk ac97_clk = {
	147	.name = "ac97_clk",
	148	.pmc_mask = 1 << AT91SAM9RL_ID_AC97C,
	149	.type = CLK_TYPE_PERIPHERAL,
	150	};
	151
	152	static struct clk *periph_clocks[] __initdata = {
	153	&pioA_clk,
	154	&pioB_clk,
	155	&pioC_clk,
	156	&pioD_clk,
	157	&usart0_clk,
	158	&usart1_clk,
	159	&usart2_clk,
	160	&usart3_clk,
	161	&mmc_clk,
	162	&twi0_clk,
	163	&twi1_clk,
	164	&spi_clk,
	165	&ssc0_clk,
	166	&ssc1_clk,
	167	&tc0_clk,
	168	&tc1_clk,
	169	&tc2_clk,
bb1ad68b	170	&pwm_clk,
877d7720 AV	171	&tsc_clk,
	172	&dma_clk,
	173	&udphs_clk,
	174	&lcdc_clk,
	175	&ac97_clk,
	176	// irq0
	177	};
	178
bd602995	179	static struct clk_lookup periph_clocks_lookups[] = {
9d87159e JCPV	180	CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
9d87159e JCPV	181	CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
bd602995 JCPV	182	CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
	183	CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
	184	CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
	185	CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
	186	CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
619d4a4b JCPV	187	CLKDEV_CON_ID("pioA", &pioA_clk),
	188	CLKDEV_CON_ID("pioB", &pioB_clk),
	189	CLKDEV_CON_ID("pioC", &pioC_clk),
	190	CLKDEV_CON_ID("pioD", &pioD_clk),
bd602995 JCPV	191	};
	192
	193	static struct clk_lookup usart_clocks_lookups[] = {
	194	CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
	195	CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
	196	CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
	197	CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
	198	CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
	199	};
	200
877d7720 AV	201	/*
	202	* The two programmable clocks.
	203	* You must configure pin multiplexing to bring these signals out.
	204	*/
	205	static struct clk pck0 = {
	206	.name = "pck0",
	207	.pmc_mask = AT91_PMC_PCK0,
	208	.type = CLK_TYPE_PROGRAMMABLE,
	209	.id = 0,
	210	};
	211	static struct clk pck1 = {
	212	.name = "pck1",
	213	.pmc_mask = AT91_PMC_PCK1,
	214	.type = CLK_TYPE_PROGRAMMABLE,
	215	.id = 1,
	216	};
	217
	218	static void __init at91sam9rl_register_clocks(void)
	219	{
	220	int i;
	221
	222	for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
	223	clk_register(periph_clocks[i]);
	224
bd602995 JCPV	225	clkdev_add_table(periph_clocks_lookups,
	226	ARRAY_SIZE(periph_clocks_lookups));
	227	clkdev_add_table(usart_clocks_lookups,
	228	ARRAY_SIZE(usart_clocks_lookups));
	229
877d7720 AV	230	clk_register(&pck0);
	231	clk_register(&pck1);
	232	}
	233
bd602995 JCPV	234	static struct clk_lookup console_clock_lookup;
	235
	236	void __init at91sam9rl_set_console_clock(int id)
	237	{
	238	if (id >= ARRAY_SIZE(usart_clocks_lookups))
	239	return;
	240
	241	console_clock_lookup.con_id = "usart";
	242	console_clock_lookup.clk = usart_clocks_lookups[id].clk;
	243	clkdev_add(&console_clock_lookup);
	244	}
	245
877d7720 AV	246	/* --------------------------------------------------------------------
	247	* GPIO
	248	* -------------------------------------------------------------------- */
	249
1a2d9156	250	static struct at91_gpio_bank at91sam9rl_gpio[] __initdata = {
877d7720 AV	251	{
877d7720 AV	252	.id = AT91SAM9RL_ID_PIOA,
80e91cb8	253	.regbase = AT91SAM9RL_BASE_PIOA,
877d7720 AV	254	}, {
877d7720 AV	255	.id = AT91SAM9RL_ID_PIOB,
80e91cb8	256	.regbase = AT91SAM9RL_BASE_PIOB,
877d7720 AV	257	}, {
877d7720 AV	258	.id = AT91SAM9RL_ID_PIOC,
80e91cb8	259	.regbase = AT91SAM9RL_BASE_PIOC,
877d7720 AV	260	}, {
877d7720 AV	261	.id = AT91SAM9RL_ID_PIOD,
80e91cb8	262	.regbase = AT91SAM9RL_BASE_PIOD,
877d7720 AV	263	}
	264	};
	265
877d7720 AV	266	/* --------------------------------------------------------------------
	267	* AT91SAM9RL processor initialization
	268	* -------------------------------------------------------------------- */
	269
21d08b9d	270	static void __init at91sam9rl_map_io(void)
877d7720	271	{
8c3583b6	272	unsigned long sram_size;
877d7720	273
8c3583b6	274	switch (at91_soc_initdata.cidr & AT91_CIDR_SRAMSIZ) {
877d7720 AV	275	case AT91_CIDR_SRAMSIZ_32K:
	276	sram_size = 2 * SZ_16K;
	277	break;
	278	case AT91_CIDR_SRAMSIZ_16K:
	279	default:
	280	sram_size = SZ_16K;
	281	}
	282
877d7720	283	/* Map SRAM */
f0051d82	284	at91_init_sram(0, AT91SAM9RL_SRAM_BASE, sram_size);
1b021a3b	285	}
877d7720	286
cfa5a1fe JCPV	287	static void __init at91sam9rl_ioremap_registers(void)
cfa5a1fe JCPV	288	{
f22deee5	289	at91_ioremap_shdwc(AT91SAM9RL_BASE_SHDWC);
e9f68b5c	290	at91_ioremap_rstc(AT91SAM9RL_BASE_RSTC);
4ab0c599	291	at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT);
faee0cc3	292	at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC);
cfa5a1fe JCPV	293	}
cfa5a1fe JCPV	294
c9dfafba NP	295	static void at91sam9rl_idle(void)
	296	{
	297	at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
	298	cpu_do_idle();
	299	}
	300
46539374	301	static void __init at91sam9rl_initialize(void)
1b021a3b	302	{
c9dfafba	303	arm_pm_idle = at91sam9rl_idle;
1b2073e7	304	arm_pm_restart = at91sam9_alt_restart;
877d7720 AV	305	at91_extern_irq = (1 << AT91SAM9RL_ID_IRQ0);
877d7720 AV	306
877d7720 AV	307	/* Register GPIO subsystem */
	308	at91_gpio_init(at91sam9rl_gpio, 4);
	309	}
	310
	311	/* --------------------------------------------------------------------
	312	* Interrupt initialization
	313	* -------------------------------------------------------------------- */
	314
	315	/*
	316	* The default interrupt priority levels (0 = lowest, 7 = highest).
	317	*/
	318	static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = {
	319	7, /* Advanced Interrupt Controller */
	320	7, /* System Peripherals */
	321	1, /* Parallel IO Controller A */
	322	1, /* Parallel IO Controller B */
	323	1, /* Parallel IO Controller C */
	324	1, /* Parallel IO Controller D */
	325	5, /* USART 0 */
	326	5, /* USART 1 */
	327	5, /* USART 2 */
	328	5, /* USART 3 */
	329	0, /* Multimedia Card Interface */
	330	6, /* Two-Wire Interface 0 */
	331	6, /* Two-Wire Interface 1 */
	332	5, /* Serial Peripheral Interface */
	333	4, /* Serial Synchronous Controller 0 */
	334	4, /* Serial Synchronous Controller 1 */
	335	0, /* Timer Counter 0 */
	336	0, /* Timer Counter 1 */
	337	0, /* Timer Counter 2 */
	338	0,
	339	0, /* Touch Screen Controller */
	340	0, /* DMA Controller */
	341	2, /* USB Device High speed port */
	342	2, /* LCD Controller */
	343	6, /* AC97 Controller */
	344	0,
	345	0,
	346	0,
	347	0,
	348	0,
	349	0,
	350	0, /* Advanced Interrupt Controller */
	351	};
	352
8c3583b6	353	struct at91_init_soc __initdata at91sam9rl_soc = {
21d08b9d	354	.map_io = at91sam9rl_map_io,
92100c12	355	.default_irq_priority = at91sam9rl_default_irq_priority,
cfa5a1fe	356	.ioremap_registers = at91sam9rl_ioremap_registers,
51ddec76	357	.register_clocks = at91sam9rl_register_clocks,
21d08b9d JCPV	358	.init = at91sam9rl_initialize,
21d08b9d JCPV	359	};