[deliverable/linux.git] / arch / arm / mach-at91 / at91sam9rl.c

/*
 * arch/arm/mach-at91/at91sam9rl.c
 *
 *  Copyright (C) 2005 SAN People
 *  Copyright (C) 2007 Atmel Corporation
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file COPYING in the main directory of this archive for
 * more details.
 */

#include <linux/module.h>
#include <linux/clk/at91_pmc.h>

#include <asm/proc-fns.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/system_misc.h>
#include <mach/cpu.h>
#include <mach/at91_dbgu.h>
#include <mach/at91sam9rl.h>

#include "at91_aic.h"
#include "at91_rstc.h"
#include "soc.h"
#include "generic.h"
#include "clock.h"
#include "sam9_smc.h"
#include "pm.h"

/* --------------------------------------------------------------------
 *  Clocks
 * -------------------------------------------------------------------- */

/*
 * The peripheral clocks.
 */
static struct clk pioA_clk = {
	.name		= "pioA_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_PIOA,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk pioB_clk = {
	.name		= "pioB_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_PIOB,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk pioC_clk = {
	.name		= "pioC_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_PIOC,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk pioD_clk = {
	.name		= "pioD_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_PIOD,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart0_clk = {
	.name		= "usart0_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_US0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart1_clk = {
	.name		= "usart1_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_US1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart2_clk = {
	.name		= "usart2_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_US2,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart3_clk = {
	.name		= "usart3_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_US3,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk mmc_clk = {
	.name		= "mci_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_MCI,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk twi0_clk = {
	.name		= "twi0_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_TWI0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk twi1_clk = {
	.name		= "twi1_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_TWI1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk spi_clk = {
	.name		= "spi_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_SPI,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk ssc0_clk = {
	.name		= "ssc0_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_SSC0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk ssc1_clk = {
	.name		= "ssc1_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_SSC1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk tc0_clk = {
	.name		= "tc0_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_TC0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk tc1_clk = {
	.name		= "tc1_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_TC1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk tc2_clk = {
	.name		= "tc2_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_TC2,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk pwm_clk = {
	.name		= "pwm_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_PWMC,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk tsc_clk = {
	.name		= "tsc_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_TSC,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk dma_clk = {
	.name		= "dma_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_DMA,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk udphs_clk = {
	.name		= "udphs_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_UDPHS,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk lcdc_clk = {
	.name		= "lcdc_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_LCDC,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk ac97_clk = {
	.name		= "ac97_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_AC97C,
	.type		= CLK_TYPE_PERIPHERAL,
};

static struct clk *periph_clocks[] __initdata = {
	&pioA_clk,
	&pioB_clk,
	&pioC_clk,
	&pioD_clk,
	&usart0_clk,
	&usart1_clk,
	&usart2_clk,
	&usart3_clk,
	&mmc_clk,
	&twi0_clk,
	&twi1_clk,
	&spi_clk,
	&ssc0_clk,
	&ssc1_clk,
	&tc0_clk,
	&tc1_clk,
	&tc2_clk,
	&pwm_clk,
	&tsc_clk,
	&dma_clk,
	&udphs_clk,
	&lcdc_clk,
	&ac97_clk,
	// irq0
};

static struct clk_lookup periph_clocks_lookups[] = {
	CLKDEV_CON_DEV_ID("hclk", "at91sam9rl-lcdfb.0", &lcdc_clk),
	CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
	CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
	CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
	CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
	CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
	CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk),
	CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
	CLKDEV_CON_DEV_ID("pclk", "fffc0000.ssc", &ssc0_clk),
	CLKDEV_CON_DEV_ID("pclk", "fffc4000.ssc", &ssc1_clk),
	CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.0", &twi0_clk),
	CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.1", &twi1_clk),
	CLKDEV_CON_ID("pioA", &pioA_clk),
	CLKDEV_CON_ID("pioB", &pioB_clk),
	CLKDEV_CON_ID("pioC", &pioC_clk),
	CLKDEV_CON_ID("pioD", &pioD_clk),
	/* more lookup table for DT entries */
	CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
	CLKDEV_CON_DEV_ID("usart", "fffb0000.serial", &usart0_clk),
	CLKDEV_CON_DEV_ID("usart", "ffffb400.serial", &usart1_clk),
	CLKDEV_CON_DEV_ID("usart", "ffffb800.serial", &usart2_clk),
	CLKDEV_CON_DEV_ID("usart", "ffffbc00.serial", &usart3_clk),
	CLKDEV_CON_DEV_ID("t0_clk", "fffa0000.timer", &tc0_clk),
	CLKDEV_CON_DEV_ID("t1_clk", "fffa0000.timer", &tc1_clk),
	CLKDEV_CON_DEV_ID("t2_clk", "fffa0000.timer", &tc2_clk),
	CLKDEV_CON_DEV_ID("mci_clk", "fffa4000.mmc", &mmc_clk),
	CLKDEV_CON_DEV_ID(NULL, "fffa8000.i2c", &twi0_clk),
	CLKDEV_CON_DEV_ID(NULL, "fffac000.i2c", &twi1_clk),
	CLKDEV_CON_DEV_ID(NULL, "ffffc800.pwm", &pwm_clk),
	CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioA_clk),
	CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioB_clk),
	CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioC_clk),
	CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioD_clk),
};

static struct clk_lookup usart_clocks_lookups[] = {
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
};

/*
 * The two programmable clocks.
 * You must configure pin multiplexing to bring these signals out.
 */
static struct clk pck0 = {
	.name		= "pck0",
	.pmc_mask	= AT91_PMC_PCK0,
	.type		= CLK_TYPE_PROGRAMMABLE,
	.id		= 0,
};
static struct clk pck1 = {
	.name		= "pck1",
	.pmc_mask	= AT91_PMC_PCK1,
	.type		= CLK_TYPE_PROGRAMMABLE,
	.id		= 1,
};

static void __init at91sam9rl_register_clocks(void)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
		clk_register(periph_clocks[i]);

	clkdev_add_table(periph_clocks_lookups,
			 ARRAY_SIZE(periph_clocks_lookups));
	clkdev_add_table(usart_clocks_lookups,
			 ARRAY_SIZE(usart_clocks_lookups));

	clk_register(&pck0);
	clk_register(&pck1);
}

/* --------------------------------------------------------------------
 *  GPIO
 * -------------------------------------------------------------------- */

static struct at91_gpio_bank at91sam9rl_gpio[] __initdata = {
	{
		.id		= AT91SAM9RL_ID_PIOA,
		.regbase	= AT91SAM9RL_BASE_PIOA,
	}, {
		.id		= AT91SAM9RL_ID_PIOB,
		.regbase	= AT91SAM9RL_BASE_PIOB,
	}, {
		.id		= AT91SAM9RL_ID_PIOC,
		.regbase	= AT91SAM9RL_BASE_PIOC,
	}, {
		.id		= AT91SAM9RL_ID_PIOD,
		.regbase	= AT91SAM9RL_BASE_PIOD,
	}
};

/* --------------------------------------------------------------------
 *  AT91SAM9RL processor initialization
 * -------------------------------------------------------------------- */

static void __init at91sam9rl_map_io(void)
{
	unsigned long sram_size;

	switch (at91_soc_initdata.cidr & AT91_CIDR_SRAMSIZ) {
		case AT91_CIDR_SRAMSIZ_32K:
			sram_size = 2 * SZ_16K;
			break;
		case AT91_CIDR_SRAMSIZ_16K:
		default:
			sram_size = SZ_16K;
	}

	/* Map SRAM */
	at91_init_sram(0, AT91SAM9RL_SRAM_BASE, sram_size);
}

static void __init at91sam9rl_ioremap_registers(void)
{
	at91_ioremap_shdwc(AT91SAM9RL_BASE_SHDWC);
	at91_ioremap_rstc(AT91SAM9RL_BASE_RSTC);
	at91_ioremap_ramc(0, AT91SAM9RL_BASE_SDRAMC, 512);
	at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT);
	at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC);
	at91_ioremap_matrix(AT91SAM9RL_BASE_MATRIX);
	at91_pm_set_standby(at91sam9_sdram_standby);
}

static void __init at91sam9rl_initialize(void)
{
	arm_pm_idle = at91sam9_idle;
	arm_pm_restart = at91sam9_alt_restart;

	at91_sysirq_mask_rtc(AT91SAM9RL_BASE_RTC);
	at91_sysirq_mask_rtt(AT91SAM9RL_BASE_RTT);

	/* Register GPIO subsystem */
	at91_gpio_init(at91sam9rl_gpio, 4);
}

/* --------------------------------------------------------------------
 *  Interrupt initialization
 * -------------------------------------------------------------------- */

/*
 * The default interrupt priority levels (0 = lowest, 7 = highest).
 */
static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = {
	7,	/* Advanced Interrupt Controller */
	7,	/* System Peripherals */
	1,	/* Parallel IO Controller A */
	1,	/* Parallel IO Controller B */
	1,	/* Parallel IO Controller C */
	1,	/* Parallel IO Controller D */
	5,	/* USART 0 */
	5,	/* USART 1 */
	5,	/* USART 2 */
	5,	/* USART 3 */
	0,	/* Multimedia Card Interface */
	6,	/* Two-Wire Interface 0 */
	6,	/* Two-Wire Interface 1 */
	5,	/* Serial Peripheral Interface */
	4,	/* Serial Synchronous Controller 0 */
	4,	/* Serial Synchronous Controller 1 */
	0,	/* Timer Counter 0 */
	0,	/* Timer Counter 1 */
	0,	/* Timer Counter 2 */
	0,
	0,	/* Touch Screen Controller */
	0,	/* DMA Controller */
	2,	/* USB Device High speed port */
	2,	/* LCD Controller */
	6,	/* AC97 Controller */
	0,
	0,
	0,
	0,
	0,
	0,
	0,	/* Advanced Interrupt Controller */
};

AT91_SOC_START(at91sam9rl)
	.map_io = at91sam9rl_map_io,
	.default_irq_priority = at91sam9rl_default_irq_priority,
	.extern_irq = (1 << AT91SAM9RL_ID_IRQ0),
	.ioremap_registers = at91sam9rl_ioremap_registers,
	.register_clocks = at91sam9rl_register_clocks,
	.init = at91sam9rl_initialize,
AT91_SOC_END
Commit	Line	Data
877d7720 AV	1	/*
	2	* arch/arm/mach-at91/at91sam9rl.c
	3	*
	4	* Copyright (C) 2005 SAN People
	5	* Copyright (C) 2007 Atmel Corporation
	6	*
	7	* This file is subject to the terms and conditions of the GNU General Public
	8	* License. See the file COPYING in the main directory of this archive for
	9	* more details.
	10	*/
	11
	12	#include <linux/module.h>
2edb90ae	13	#include <linux/clk/at91_pmc.h>
877d7720	14
c9dfafba	15	#include <asm/proc-fns.h>
80b02c17	16	#include <asm/irq.h>
877d7720 AV	17	#include <asm/mach/arch.h>
877d7720 AV	18	#include <asm/mach/map.h>
9f97da78	19	#include <asm/system_misc.h>
a09e64fb	20	#include <mach/cpu.h>
8c3583b6	21	#include <mach/at91_dbgu.h>
a09e64fb	22	#include <mach/at91sam9rl.h>
877d7720	23
a510b9ba	24	#include "at91_aic.h"
f0995d08	25	#include "at91_rstc.h"
21d08b9d	26	#include "soc.h"
877d7720 AV	27	#include "generic.h"
877d7720 AV	28	#include "clock.h"
faee0cc3	29	#include "sam9_smc.h"
5ad945ea	30	#include "pm.h"
877d7720	31
877d7720 AV	32	/* --------------------------------------------------------------------
	33	* Clocks
	34	* -------------------------------------------------------------------- */
	35
	36	/*
	37	* The peripheral clocks.
	38	*/
	39	static struct clk pioA_clk = {
	40	.name = "pioA_clk",
	41	.pmc_mask = 1 << AT91SAM9RL_ID_PIOA,
	42	.type = CLK_TYPE_PERIPHERAL,
	43	};
	44	static struct clk pioB_clk = {
	45	.name = "pioB_clk",
	46	.pmc_mask = 1 << AT91SAM9RL_ID_PIOB,
	47	.type = CLK_TYPE_PERIPHERAL,
	48	};
	49	static struct clk pioC_clk = {
	50	.name = "pioC_clk",
	51	.pmc_mask = 1 << AT91SAM9RL_ID_PIOC,
	52	.type = CLK_TYPE_PERIPHERAL,
	53	};
	54	static struct clk pioD_clk = {
	55	.name = "pioD_clk",
	56	.pmc_mask = 1 << AT91SAM9RL_ID_PIOD,
	57	.type = CLK_TYPE_PERIPHERAL,
	58	};
	59	static struct clk usart0_clk = {
	60	.name = "usart0_clk",
	61	.pmc_mask = 1 << AT91SAM9RL_ID_US0,
	62	.type = CLK_TYPE_PERIPHERAL,
	63	};
	64	static struct clk usart1_clk = {
	65	.name = "usart1_clk",
	66	.pmc_mask = 1 << AT91SAM9RL_ID_US1,
	67	.type = CLK_TYPE_PERIPHERAL,
	68	};
	69	static struct clk usart2_clk = {
	70	.name = "usart2_clk",
	71	.pmc_mask = 1 << AT91SAM9RL_ID_US2,
	72	.type = CLK_TYPE_PERIPHERAL,
	73	};
	74	static struct clk usart3_clk = {
	75	.name = "usart3_clk",
	76	.pmc_mask = 1 << AT91SAM9RL_ID_US3,
	77	.type = CLK_TYPE_PERIPHERAL,
	78	};
	79	static struct clk mmc_clk = {
	80	.name = "mci_clk",
	81	.pmc_mask = 1 << AT91SAM9RL_ID_MCI,
	82	.type = CLK_TYPE_PERIPHERAL,
	83	};
	84	static struct clk twi0_clk = {
	85	.name = "twi0_clk",
	86	.pmc_mask = 1 << AT91SAM9RL_ID_TWI0,
	87	.type = CLK_TYPE_PERIPHERAL,
	88	};
	89	static struct clk twi1_clk = {
	90	.name = "twi1_clk",
	91	.pmc_mask = 1 << AT91SAM9RL_ID_TWI1,
	92	.type = CLK_TYPE_PERIPHERAL,
	93	};
	94	static struct clk spi_clk = {
	95	.name = "spi_clk",
96	.pmc_mask = 1 << AT91SAM9RL_ID_SPI,
97	.type = CLK_TYPE_PERIPHERAL,
98	};
99	static struct clk ssc0_clk = {
100	.name = "ssc0_clk",
101	.pmc_mask = 1 << AT91SAM9RL_ID_SSC0,
102	.type = CLK_TYPE_PERIPHERAL,
103	};
104	static struct clk ssc1_clk = {
105	.name = "ssc1_clk",
106	.pmc_mask = 1 << AT91SAM9RL_ID_SSC1,
107	.type = CLK_TYPE_PERIPHERAL,
108	};
109	static struct clk tc0_clk = {
110	.name = "tc0_clk",
111	.pmc_mask = 1 << AT91SAM9RL_ID_TC0,
112	.type = CLK_TYPE_PERIPHERAL,
113	};
114	static struct clk tc1_clk = {
115	.name = "tc1_clk",
116	.pmc_mask = 1 << AT91SAM9RL_ID_TC1,
117	.type = CLK_TYPE_PERIPHERAL,
118	};
119	static struct clk tc2_clk = {
120	.name = "tc2_clk",
121	.pmc_mask = 1 << AT91SAM9RL_ID_TC2,
122	.type = CLK_TYPE_PERIPHERAL,
123	};
bb1ad68b AV	124	static struct clk pwm_clk = {
bb1ad68b AV	125	.name = "pwm_clk",
877d7720 AV	126	.pmc_mask = 1 << AT91SAM9RL_ID_PWMC,
	127	.type = CLK_TYPE_PERIPHERAL,
	128	};
	129	static struct clk tsc_clk = {
	130	.name = "tsc_clk",
	131	.pmc_mask = 1 << AT91SAM9RL_ID_TSC,
	132	.type = CLK_TYPE_PERIPHERAL,
	133	};
	134	static struct clk dma_clk = {
	135	.name = "dma_clk",
	136	.pmc_mask = 1 << AT91SAM9RL_ID_DMA,
	137	.type = CLK_TYPE_PERIPHERAL,
	138	};
	139	static struct clk udphs_clk = {
	140	.name = "udphs_clk",
	141	.pmc_mask = 1 << AT91SAM9RL_ID_UDPHS,
	142	.type = CLK_TYPE_PERIPHERAL,
	143	};
	144	static struct clk lcdc_clk = {
	145	.name = "lcdc_clk",
	146	.pmc_mask = 1 << AT91SAM9RL_ID_LCDC,
	147	.type = CLK_TYPE_PERIPHERAL,
	148	};
	149	static struct clk ac97_clk = {
	150	.name = "ac97_clk",
	151	.pmc_mask = 1 << AT91SAM9RL_ID_AC97C,
	152	.type = CLK_TYPE_PERIPHERAL,
	153	};
	154
	155	static struct clk *periph_clocks[] __initdata = {
	156	&pioA_clk,
	157	&pioB_clk,
	158	&pioC_clk,
	159	&pioD_clk,
	160	&usart0_clk,
	161	&usart1_clk,
	162	&usart2_clk,
	163	&usart3_clk,
	164	&mmc_clk,
	165	&twi0_clk,
	166	&twi1_clk,
	167	&spi_clk,
	168	&ssc0_clk,
	169	&ssc1_clk,
	170	&tc0_clk,
	171	&tc1_clk,
	172	&tc2_clk,
bb1ad68b	173	&pwm_clk,
877d7720 AV	174	&tsc_clk,
	175	&dma_clk,
	176	&udphs_clk,
	177	&lcdc_clk,
	178	&ac97_clk,
	179	// irq0
	180	};
	181
bd602995	182	static struct clk_lookup periph_clocks_lookups[] = {
bbd44f6b	183	CLKDEV_CON_DEV_ID("hclk", "at91sam9rl-lcdfb.0", &lcdc_clk),
9d87159e JCPV	184	CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
9d87159e JCPV	185	CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
bd602995 JCPV	186	CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
	187	CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
	188	CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
636036d2 BS	189	CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk),
636036d2 BS	190	CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
099343c6 BS	191	CLKDEV_CON_DEV_ID("pclk", "fffc0000.ssc", &ssc0_clk),
099343c6 BS	192	CLKDEV_CON_DEV_ID("pclk", "fffc4000.ssc", &ssc1_clk),
fac368a0 NV	193	CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.0", &twi0_clk),
fac368a0 NV	194	CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.1", &twi1_clk),
619d4a4b JCPV	195	CLKDEV_CON_ID("pioA", &pioA_clk),
	196	CLKDEV_CON_ID("pioB", &pioB_clk),
	197	CLKDEV_CON_ID("pioC", &pioC_clk),
	198	CLKDEV_CON_ID("pioD", &pioD_clk),
09ab012a AB	199	/* more lookup table for DT entries */
	200	CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
	201	CLKDEV_CON_DEV_ID("usart", "fffb0000.serial", &usart0_clk),
	202	CLKDEV_CON_DEV_ID("usart", "ffffb400.serial", &usart1_clk),
	203	CLKDEV_CON_DEV_ID("usart", "ffffb800.serial", &usart2_clk),
	204	CLKDEV_CON_DEV_ID("usart", "ffffbc00.serial", &usart3_clk),
	205	CLKDEV_CON_DEV_ID("t0_clk", "fffa0000.timer", &tc0_clk),
	206	CLKDEV_CON_DEV_ID("t1_clk", "fffa0000.timer", &tc1_clk),
	207	CLKDEV_CON_DEV_ID("t2_clk", "fffa0000.timer", &tc2_clk),
	208	CLKDEV_CON_DEV_ID("mci_clk", "fffa4000.mmc", &mmc_clk),
	209	CLKDEV_CON_DEV_ID(NULL, "fffa8000.i2c", &twi0_clk),
	210	CLKDEV_CON_DEV_ID(NULL, "fffac000.i2c", &twi1_clk),
	211	CLKDEV_CON_DEV_ID(NULL, "ffffc800.pwm", &pwm_clk),
	212	CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioA_clk),
	213	CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioB_clk),
	214	CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioC_clk),
	215	CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioD_clk),
bd602995 JCPV	216	};
	217
	218	static struct clk_lookup usart_clocks_lookups[] = {
	219	CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
	220	CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
	221	CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
	222	CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
	223	CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
	224	};
	225
877d7720 AV	226	/*
	227	* The two programmable clocks.
	228	* You must configure pin multiplexing to bring these signals out.
	229	*/
	230	static struct clk pck0 = {
	231	.name = "pck0",
	232	.pmc_mask = AT91_PMC_PCK0,
	233	.type = CLK_TYPE_PROGRAMMABLE,
	234	.id = 0,
	235	};
	236	static struct clk pck1 = {
	237	.name = "pck1",
	238	.pmc_mask = AT91_PMC_PCK1,
	239	.type = CLK_TYPE_PROGRAMMABLE,
	240	.id = 1,
	241	};
	242
	243	static void __init at91sam9rl_register_clocks(void)
	244	{
	245	int i;
	246
	247	for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
	248	clk_register(periph_clocks[i]);
	249
bd602995 JCPV	250	clkdev_add_table(periph_clocks_lookups,
	251	ARRAY_SIZE(periph_clocks_lookups));
	252	clkdev_add_table(usart_clocks_lookups,
	253	ARRAY_SIZE(usart_clocks_lookups));
	254
877d7720 AV	255	clk_register(&pck0);
	256	clk_register(&pck1);
	257	}
	258
	259	/* --------------------------------------------------------------------
	260	* GPIO
	261	* -------------------------------------------------------------------- */
	262
1a2d9156	263	static struct at91_gpio_bank at91sam9rl_gpio[] __initdata = {
877d7720 AV	264	{
877d7720 AV	265	.id = AT91SAM9RL_ID_PIOA,
80e91cb8	266	.regbase = AT91SAM9RL_BASE_PIOA,
877d7720 AV	267	}, {
877d7720 AV	268	.id = AT91SAM9RL_ID_PIOB,
80e91cb8	269	.regbase = AT91SAM9RL_BASE_PIOB,
877d7720 AV	270	}, {
877d7720 AV	271	.id = AT91SAM9RL_ID_PIOC,
80e91cb8	272	.regbase = AT91SAM9RL_BASE_PIOC,
877d7720 AV	273	}, {
877d7720 AV	274	.id = AT91SAM9RL_ID_PIOD,
80e91cb8	275	.regbase = AT91SAM9RL_BASE_PIOD,
877d7720 AV	276	}
	277	};
	278
877d7720 AV	279	/* --------------------------------------------------------------------
	280	* AT91SAM9RL processor initialization
	281	* -------------------------------------------------------------------- */
	282
21d08b9d	283	static void __init at91sam9rl_map_io(void)
877d7720	284	{
8c3583b6	285	unsigned long sram_size;
877d7720	286
8c3583b6	287	switch (at91_soc_initdata.cidr & AT91_CIDR_SRAMSIZ) {
877d7720 AV	288	case AT91_CIDR_SRAMSIZ_32K:
	289	sram_size = 2 * SZ_16K;
	290	break;
	291	case AT91_CIDR_SRAMSIZ_16K:
	292	default:
	293	sram_size = SZ_16K;
	294	}
	295
877d7720	296	/* Map SRAM */
f0051d82	297	at91_init_sram(0, AT91SAM9RL_SRAM_BASE, sram_size);
1b021a3b	298	}
877d7720	299
cfa5a1fe JCPV	300	static void __init at91sam9rl_ioremap_registers(void)
cfa5a1fe JCPV	301	{
f22deee5	302	at91_ioremap_shdwc(AT91SAM9RL_BASE_SHDWC);
e9f68b5c	303	at91_ioremap_rstc(AT91SAM9RL_BASE_RSTC);
f363c407	304	at91_ioremap_ramc(0, AT91SAM9RL_BASE_SDRAMC, 512);
4ab0c599	305	at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT);
faee0cc3	306	at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC);
4342d647	307	at91_ioremap_matrix(AT91SAM9RL_BASE_MATRIX);
6b625891	308	at91_pm_set_standby(at91sam9_sdram_standby);
cfa5a1fe JCPV	309	}
cfa5a1fe JCPV	310
46539374	311	static void __init at91sam9rl_initialize(void)
1b021a3b	312	{
0d781716	313	arm_pm_idle = at91sam9_idle;
1b2073e7	314	arm_pm_restart = at91sam9_alt_restart;
877d7720	315
6de714c2	316	at91_sysirq_mask_rtc(AT91SAM9RL_BASE_RTC);
94c4c79f	317	at91_sysirq_mask_rtt(AT91SAM9RL_BASE_RTT);
6de714c2	318
877d7720 AV	319	/* Register GPIO subsystem */
	320	at91_gpio_init(at91sam9rl_gpio, 4);
	321	}
	322
	323	/* --------------------------------------------------------------------
	324	* Interrupt initialization
	325	* -------------------------------------------------------------------- */
	326
	327	/*
	328	* The default interrupt priority levels (0 = lowest, 7 = highest).
	329	*/
	330	static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = {
	331	7, /* Advanced Interrupt Controller */
	332	7, /* System Peripherals */
	333	1, /* Parallel IO Controller A */
	334	1, /* Parallel IO Controller B */
	335	1, /* Parallel IO Controller C */
	336	1, /* Parallel IO Controller D */
	337	5, /* USART 0 */
	338	5, /* USART 1 */
	339	5, /* USART 2 */
	340	5, /* USART 3 */
	341	0, /* Multimedia Card Interface */
	342	6, /* Two-Wire Interface 0 */
	343	6, /* Two-Wire Interface 1 */
	344	5, /* Serial Peripheral Interface */
	345	4, /* Serial Synchronous Controller 0 */
	346	4, /* Serial Synchronous Controller 1 */
	347	0, /* Timer Counter 0 */
	348	0, /* Timer Counter 1 */
	349	0, /* Timer Counter 2 */
	350	0,
	351	0, /* Touch Screen Controller */
	352	0, /* DMA Controller */
	353	2, /* USB Device High speed port */
	354	2, /* LCD Controller */
	355	6, /* AC97 Controller */
	356	0,
	357	0,
	358	0,
	359	0,
	360	0,
	361	0,
	362	0, /* Advanced Interrupt Controller */
	363	};
	364
84ddb087	365	AT91_SOC_START(at91sam9rl)
21d08b9d	366	.map_io = at91sam9rl_map_io,
92100c12	367	.default_irq_priority = at91sam9rl_default_irq_priority,
546c830c	368	.extern_irq = (1 << AT91SAM9RL_ID_IRQ0),
cfa5a1fe	369	.ioremap_registers = at91sam9rl_ioremap_registers,
51ddec76	370	.register_clocks = at91sam9rl_register_clocks,
21d08b9d	371	.init = at91sam9rl_initialize,
8d39e0fd	372	AT91_SOC_END