[deliverable/linux.git] / arch / arm / mach-at91 / at91sam9rl.c

/*
 * arch/arm/mach-at91/at91sam9rl.c
 *
 *  Copyright (C) 2005 SAN People
 *  Copyright (C) 2007 Atmel Corporation
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file COPYING in the main directory of this archive for
 * more details.
 */

#include <linux/module.h>
#include <linux/pm.h>

#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <mach/cpu.h>
#include <mach/at91_dbgu.h>
#include <mach/at91sam9rl.h>
#include <mach/at91_pmc.h>
#include <mach/at91_rstc.h>
#include <mach/at91_shdwc.h>

#include "soc.h"
#include "generic.h"
#include "clock.h"

static struct map_desc at91sam9rl_sram_desc[] __initdata = {
	{
		.pfn		= __phys_to_pfn(AT91SAM9RL_SRAM_BASE),
		.type		= MT_DEVICE,
	}
};

/* --------------------------------------------------------------------
 *  Clocks
 * -------------------------------------------------------------------- */

/*
 * The peripheral clocks.
 */
static struct clk pioA_clk = {
	.name		= "pioA_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_PIOA,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk pioB_clk = {
	.name		= "pioB_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_PIOB,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk pioC_clk = {
	.name		= "pioC_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_PIOC,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk pioD_clk = {
	.name		= "pioD_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_PIOD,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart0_clk = {
	.name		= "usart0_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_US0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart1_clk = {
	.name		= "usart1_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_US1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart2_clk = {
	.name		= "usart2_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_US2,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart3_clk = {
	.name		= "usart3_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_US3,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk mmc_clk = {
	.name		= "mci_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_MCI,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk twi0_clk = {
	.name		= "twi0_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_TWI0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk twi1_clk = {
	.name		= "twi1_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_TWI1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk spi_clk = {
	.name		= "spi_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_SPI,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk ssc0_clk = {
	.name		= "ssc0_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_SSC0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk ssc1_clk = {
	.name		= "ssc1_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_SSC1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk tc0_clk = {
	.name		= "tc0_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_TC0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk tc1_clk = {
	.name		= "tc1_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_TC1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk tc2_clk = {
	.name		= "tc2_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_TC2,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk pwm_clk = {
	.name		= "pwm_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_PWMC,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk tsc_clk = {
	.name		= "tsc_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_TSC,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk dma_clk = {
	.name		= "dma_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_DMA,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk udphs_clk = {
	.name		= "udphs_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_UDPHS,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk lcdc_clk = {
	.name		= "lcdc_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_LCDC,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk ac97_clk = {
	.name		= "ac97_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_AC97C,
	.type		= CLK_TYPE_PERIPHERAL,
};

static struct clk *periph_clocks[] __initdata = {
	&pioA_clk,
	&pioB_clk,
	&pioC_clk,
	&pioD_clk,
	&usart0_clk,
	&usart1_clk,
	&usart2_clk,
	&usart3_clk,
	&mmc_clk,
	&twi0_clk,
	&twi1_clk,
	&spi_clk,
	&ssc0_clk,
	&ssc1_clk,
	&tc0_clk,
	&tc1_clk,
	&tc2_clk,
	&pwm_clk,
	&tsc_clk,
	&dma_clk,
	&udphs_clk,
	&lcdc_clk,
	&ac97_clk,
	// irq0
};

static struct clk_lookup periph_clocks_lookups[] = {
	CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
	CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
	CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
	CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
	CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
	CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
	CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
};

static struct clk_lookup usart_clocks_lookups[] = {
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
};

/*
 * The two programmable clocks.
 * You must configure pin multiplexing to bring these signals out.
 */
static struct clk pck0 = {
	.name		= "pck0",
	.pmc_mask	= AT91_PMC_PCK0,
	.type		= CLK_TYPE_PROGRAMMABLE,
	.id		= 0,
};
static struct clk pck1 = {
	.name		= "pck1",
	.pmc_mask	= AT91_PMC_PCK1,
	.type		= CLK_TYPE_PROGRAMMABLE,
	.id		= 1,
};

static void __init at91sam9rl_register_clocks(void)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
		clk_register(periph_clocks[i]);

	clkdev_add_table(periph_clocks_lookups,
			 ARRAY_SIZE(periph_clocks_lookups));
	clkdev_add_table(usart_clocks_lookups,
			 ARRAY_SIZE(usart_clocks_lookups));

	clk_register(&pck0);
	clk_register(&pck1);
}

static struct clk_lookup console_clock_lookup;

void __init at91sam9rl_set_console_clock(int id)
{
	if (id >= ARRAY_SIZE(usart_clocks_lookups))
		return;

	console_clock_lookup.con_id = "usart";
	console_clock_lookup.clk = usart_clocks_lookups[id].clk;
	clkdev_add(&console_clock_lookup);
}

/* --------------------------------------------------------------------
 *  GPIO
 * -------------------------------------------------------------------- */

static struct at91_gpio_bank at91sam9rl_gpio[] = {
	{
		.id		= AT91SAM9RL_ID_PIOA,
		.offset		= AT91_PIOA,
		.clock		= &pioA_clk,
	}, {
		.id		= AT91SAM9RL_ID_PIOB,
		.offset		= AT91_PIOB,
		.clock		= &pioB_clk,
	}, {
		.id		= AT91SAM9RL_ID_PIOC,
		.offset		= AT91_PIOC,
		.clock		= &pioC_clk,
	}, {
		.id		= AT91SAM9RL_ID_PIOD,
		.offset		= AT91_PIOD,
		.clock		= &pioD_clk,
	}
};

static void at91sam9rl_poweroff(void)
{
	at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
}


/* --------------------------------------------------------------------
 *  AT91SAM9RL processor initialization
 * -------------------------------------------------------------------- */

static void __init at91sam9rl_map_io(void)
{
	unsigned long sram_size;

	switch (at91_soc_initdata.cidr & AT91_CIDR_SRAMSIZ) {
		case AT91_CIDR_SRAMSIZ_32K:
			sram_size = 2 * SZ_16K;
			break;
		case AT91_CIDR_SRAMSIZ_16K:
		default:
			sram_size = SZ_16K;
	}

	at91sam9rl_sram_desc->virtual = AT91_IO_VIRT_BASE - sram_size;
	at91sam9rl_sram_desc->length = sram_size;

	/* Map SRAM */
	iotable_init(at91sam9rl_sram_desc, ARRAY_SIZE(at91sam9rl_sram_desc));
}

static void __init at91sam9rl_initialize(unsigned long main_clock)
{
	at91_arch_reset = at91sam9_alt_reset;
	pm_power_off = at91sam9rl_poweroff;
	at91_extern_irq = (1 << AT91SAM9RL_ID_IRQ0);

	/* Init clock subsystem */
	at91_clock_init(main_clock);

	/* Register the processor-specific clocks */
	at91sam9rl_register_clocks();

	/* Register GPIO subsystem */
	at91_gpio_init(at91sam9rl_gpio, 4);
}

/* --------------------------------------------------------------------
 *  Interrupt initialization
 * -------------------------------------------------------------------- */

/*
 * The default interrupt priority levels (0 = lowest, 7 = highest).
 */
static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = {
	7,	/* Advanced Interrupt Controller */
	7,	/* System Peripherals */
	1,	/* Parallel IO Controller A */
	1,	/* Parallel IO Controller B */
	1,	/* Parallel IO Controller C */
	1,	/* Parallel IO Controller D */
	5,	/* USART 0 */
	5,	/* USART 1 */
	5,	/* USART 2 */
	5,	/* USART 3 */
	0,	/* Multimedia Card Interface */
	6,	/* Two-Wire Interface 0 */
	6,	/* Two-Wire Interface 1 */
	5,	/* Serial Peripheral Interface */
	4,	/* Serial Synchronous Controller 0 */
	4,	/* Serial Synchronous Controller 1 */
	0,	/* Timer Counter 0 */
	0,	/* Timer Counter 1 */
	0,	/* Timer Counter 2 */
	0,
	0,	/* Touch Screen Controller */
	0,	/* DMA Controller */
	2,	/* USB Device High speed port */
	2,	/* LCD Controller */
	6,	/* AC97 Controller */
	0,
	0,
	0,
	0,
	0,
	0,
	0,	/* Advanced Interrupt Controller */
};

struct at91_init_soc __initdata at91sam9rl_soc = {
	.map_io = at91sam9rl_map_io,
	.default_irq_priority = at91sam9rl_default_irq_priority,
	.init = at91sam9rl_initialize,
};
Commit	Line	Data
877d7720 AV	1	/*
	2	* arch/arm/mach-at91/at91sam9rl.c
	3	*
	4	* Copyright (C) 2005 SAN People
	5	* Copyright (C) 2007 Atmel Corporation
	6	*
	7	* This file is subject to the terms and conditions of the GNU General Public
	8	* License. See the file COPYING in the main directory of this archive for
	9	* more details.
	10	*/
	11
	12	#include <linux/module.h>
3ef2fb42	13	#include <linux/pm.h>
877d7720	14
80b02c17	15	#include <asm/irq.h>
877d7720 AV	16	#include <asm/mach/arch.h>
877d7720 AV	17	#include <asm/mach/map.h>
a09e64fb	18	#include <mach/cpu.h>
8c3583b6	19	#include <mach/at91_dbgu.h>
a09e64fb RK	20	#include <mach/at91sam9rl.h>
	21	#include <mach/at91_pmc.h>
	22	#include <mach/at91_rstc.h>
	23	#include <mach/at91_shdwc.h>
877d7720	24
21d08b9d	25	#include "soc.h"
877d7720 AV	26	#include "generic.h"
	27	#include "clock.h"
	28
877d7720 AV	29	static struct map_desc at91sam9rl_sram_desc[] __initdata = {
	30	{
	31	.pfn = __phys_to_pfn(AT91SAM9RL_SRAM_BASE),
	32	.type = MT_DEVICE,
	33	}
	34	};
	35
	36	/* --------------------------------------------------------------------
	37	* Clocks
	38	* -------------------------------------------------------------------- */
	39
	40	/*
	41	* The peripheral clocks.
	42	*/
	43	static struct clk pioA_clk = {
	44	.name = "pioA_clk",
	45	.pmc_mask = 1 << AT91SAM9RL_ID_PIOA,
	46	.type = CLK_TYPE_PERIPHERAL,
	47	};
	48	static struct clk pioB_clk = {
	49	.name = "pioB_clk",
	50	.pmc_mask = 1 << AT91SAM9RL_ID_PIOB,
	51	.type = CLK_TYPE_PERIPHERAL,
	52	};
	53	static struct clk pioC_clk = {
	54	.name = "pioC_clk",
	55	.pmc_mask = 1 << AT91SAM9RL_ID_PIOC,
	56	.type = CLK_TYPE_PERIPHERAL,
	57	};
	58	static struct clk pioD_clk = {
	59	.name = "pioD_clk",
	60	.pmc_mask = 1 << AT91SAM9RL_ID_PIOD,
	61	.type = CLK_TYPE_PERIPHERAL,
	62	};
	63	static struct clk usart0_clk = {
	64	.name = "usart0_clk",
	65	.pmc_mask = 1 << AT91SAM9RL_ID_US0,
	66	.type = CLK_TYPE_PERIPHERAL,
	67	};
	68	static struct clk usart1_clk = {
	69	.name = "usart1_clk",
	70	.pmc_mask = 1 << AT91SAM9RL_ID_US1,
	71	.type = CLK_TYPE_PERIPHERAL,
	72	};
	73	static struct clk usart2_clk = {
	74	.name = "usart2_clk",
	75	.pmc_mask = 1 << AT91SAM9RL_ID_US2,
	76	.type = CLK_TYPE_PERIPHERAL,
	77	};
	78	static struct clk usart3_clk = {
	79	.name = "usart3_clk",
	80	.pmc_mask = 1 << AT91SAM9RL_ID_US3,
	81	.type = CLK_TYPE_PERIPHERAL,
	82	};
	83	static struct clk mmc_clk = {
	84	.name = "mci_clk",
	85	.pmc_mask = 1 << AT91SAM9RL_ID_MCI,
	86	.type = CLK_TYPE_PERIPHERAL,
	87	};
	88	static struct clk twi0_clk = {
	89	.name = "twi0_clk",
	90	.pmc_mask = 1 << AT91SAM9RL_ID_TWI0,
	91	.type = CLK_TYPE_PERIPHERAL,
	92	};
93	static struct clk twi1_clk = {
94	.name = "twi1_clk",
95	.pmc_mask = 1 << AT91SAM9RL_ID_TWI1,
96	.type = CLK_TYPE_PERIPHERAL,
97	};
98	static struct clk spi_clk = {
99	.name = "spi_clk",
100	.pmc_mask = 1 << AT91SAM9RL_ID_SPI,
101	.type = CLK_TYPE_PERIPHERAL,
102	};
103	static struct clk ssc0_clk = {
104	.name = "ssc0_clk",
105	.pmc_mask = 1 << AT91SAM9RL_ID_SSC0,
106	.type = CLK_TYPE_PERIPHERAL,
107	};
108	static struct clk ssc1_clk = {
109	.name = "ssc1_clk",
110	.pmc_mask = 1 << AT91SAM9RL_ID_SSC1,
111	.type = CLK_TYPE_PERIPHERAL,
112	};
113	static struct clk tc0_clk = {
114	.name = "tc0_clk",
115	.pmc_mask = 1 << AT91SAM9RL_ID_TC0,
116	.type = CLK_TYPE_PERIPHERAL,
117	};
118	static struct clk tc1_clk = {
119	.name = "tc1_clk",
120	.pmc_mask = 1 << AT91SAM9RL_ID_TC1,
121	.type = CLK_TYPE_PERIPHERAL,
122	};
123	static struct clk tc2_clk = {
124	.name = "tc2_clk",
125	.pmc_mask = 1 << AT91SAM9RL_ID_TC2,
126	.type = CLK_TYPE_PERIPHERAL,
127	};
bb1ad68b AV	128	static struct clk pwm_clk = {
bb1ad68b AV	129	.name = "pwm_clk",
877d7720 AV	130	.pmc_mask = 1 << AT91SAM9RL_ID_PWMC,
	131	.type = CLK_TYPE_PERIPHERAL,
	132	};
	133	static struct clk tsc_clk = {
	134	.name = "tsc_clk",
	135	.pmc_mask = 1 << AT91SAM9RL_ID_TSC,
	136	.type = CLK_TYPE_PERIPHERAL,
	137	};
	138	static struct clk dma_clk = {
	139	.name = "dma_clk",
	140	.pmc_mask = 1 << AT91SAM9RL_ID_DMA,
	141	.type = CLK_TYPE_PERIPHERAL,
	142	};
	143	static struct clk udphs_clk = {
	144	.name = "udphs_clk",
	145	.pmc_mask = 1 << AT91SAM9RL_ID_UDPHS,
	146	.type = CLK_TYPE_PERIPHERAL,
	147	};
	148	static struct clk lcdc_clk = {
	149	.name = "lcdc_clk",
	150	.pmc_mask = 1 << AT91SAM9RL_ID_LCDC,
	151	.type = CLK_TYPE_PERIPHERAL,
	152	};
	153	static struct clk ac97_clk = {
	154	.name = "ac97_clk",
	155	.pmc_mask = 1 << AT91SAM9RL_ID_AC97C,
	156	.type = CLK_TYPE_PERIPHERAL,
	157	};
	158
	159	static struct clk *periph_clocks[] __initdata = {
	160	&pioA_clk,
	161	&pioB_clk,
	162	&pioC_clk,
	163	&pioD_clk,
	164	&usart0_clk,
	165	&usart1_clk,
	166	&usart2_clk,
	167	&usart3_clk,
	168	&mmc_clk,
	169	&twi0_clk,
	170	&twi1_clk,
	171	&spi_clk,
	172	&ssc0_clk,
	173	&ssc1_clk,
	174	&tc0_clk,
	175	&tc1_clk,
	176	&tc2_clk,
bb1ad68b	177	&pwm_clk,
877d7720 AV	178	&tsc_clk,
	179	&dma_clk,
	180	&udphs_clk,
	181	&lcdc_clk,
	182	&ac97_clk,
	183	// irq0
	184	};
	185
bd602995	186	static struct clk_lookup periph_clocks_lookups[] = {
9d87159e JCPV	187	CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
9d87159e JCPV	188	CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
bd602995 JCPV	189	CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
	190	CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
	191	CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
	192	CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
	193	CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
	194	};
	195
	196	static struct clk_lookup usart_clocks_lookups[] = {
	197	CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
	198	CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
	199	CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
	200	CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
	201	CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
	202	};
	203
877d7720 AV	204	/*
	205	* The two programmable clocks.
	206	* You must configure pin multiplexing to bring these signals out.
	207	*/
	208	static struct clk pck0 = {
	209	.name = "pck0",
	210	.pmc_mask = AT91_PMC_PCK0,
	211	.type = CLK_TYPE_PROGRAMMABLE,
	212	.id = 0,
	213	};
	214	static struct clk pck1 = {
	215	.name = "pck1",
	216	.pmc_mask = AT91_PMC_PCK1,
	217	.type = CLK_TYPE_PROGRAMMABLE,
	218	.id = 1,
	219	};
	220
	221	static void __init at91sam9rl_register_clocks(void)
	222	{
	223	int i;
	224
	225	for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
	226	clk_register(periph_clocks[i]);
	227
bd602995 JCPV	228	clkdev_add_table(periph_clocks_lookups,
	229	ARRAY_SIZE(periph_clocks_lookups));
	230	clkdev_add_table(usart_clocks_lookups,
	231	ARRAY_SIZE(usart_clocks_lookups));
	232
877d7720 AV	233	clk_register(&pck0);
	234	clk_register(&pck1);
	235	}
	236
bd602995 JCPV	237	static struct clk_lookup console_clock_lookup;
	238
	239	void __init at91sam9rl_set_console_clock(int id)
	240	{
	241	if (id >= ARRAY_SIZE(usart_clocks_lookups))
	242	return;
	243
	244	console_clock_lookup.con_id = "usart";
	245	console_clock_lookup.clk = usart_clocks_lookups[id].clk;
	246	clkdev_add(&console_clock_lookup);
	247	}
	248
877d7720 AV	249	/* --------------------------------------------------------------------
	250	* GPIO
	251	* -------------------------------------------------------------------- */
	252
	253	static struct at91_gpio_bank at91sam9rl_gpio[] = {
	254	{
	255	.id = AT91SAM9RL_ID_PIOA,
	256	.offset = AT91_PIOA,
	257	.clock = &pioA_clk,
	258	}, {
	259	.id = AT91SAM9RL_ID_PIOB,
	260	.offset = AT91_PIOB,
	261	.clock = &pioB_clk,
	262	}, {
	263	.id = AT91SAM9RL_ID_PIOC,
	264	.offset = AT91_PIOC,
	265	.clock = &pioC_clk,
	266	}, {
	267	.id = AT91SAM9RL_ID_PIOD,
	268	.offset = AT91_PIOD,
	269	.clock = &pioD_clk,
	270	}
	271	};
	272
3ef2fb42 AV	273	static void at91sam9rl_poweroff(void)
	274	{
	275	at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY \| AT91_SHDW_SHDW);
	276	}
	277
877d7720 AV	278
	279	/* --------------------------------------------------------------------
	280	* AT91SAM9RL processor initialization
	281	* -------------------------------------------------------------------- */
	282
21d08b9d	283	static void __init at91sam9rl_map_io(void)
877d7720	284	{
8c3583b6	285	unsigned long sram_size;
877d7720	286
8c3583b6	287	switch (at91_soc_initdata.cidr & AT91_CIDR_SRAMSIZ) {
877d7720 AV	288	case AT91_CIDR_SRAMSIZ_32K:
	289	sram_size = 2 * SZ_16K;
	290	break;
	291	case AT91_CIDR_SRAMSIZ_16K:
	292	default:
	293	sram_size = SZ_16K;
	294	}
	295
	296	at91sam9rl_sram_desc->virtual = AT91_IO_VIRT_BASE - sram_size;
	297	at91sam9rl_sram_desc->length = sram_size;
	298
	299	/* Map SRAM */
	300	iotable_init(at91sam9rl_sram_desc, ARRAY_SIZE(at91sam9rl_sram_desc));
1b021a3b	301	}
877d7720	302
21d08b9d	303	static void __init at91sam9rl_initialize(unsigned long main_clock)
1b021a3b	304	{
bb413db5	305	at91_arch_reset = at91sam9_alt_reset;
3ef2fb42	306	pm_power_off = at91sam9rl_poweroff;
877d7720 AV	307	at91_extern_irq = (1 << AT91SAM9RL_ID_IRQ0);
	308
	309	/* Init clock subsystem */
	310	at91_clock_init(main_clock);
	311
	312	/* Register the processor-specific clocks */
	313	at91sam9rl_register_clocks();
	314
	315	/* Register GPIO subsystem */
	316	at91_gpio_init(at91sam9rl_gpio, 4);
	317	}
	318
	319	/* --------------------------------------------------------------------
	320	* Interrupt initialization
	321	* -------------------------------------------------------------------- */
	322
	323	/*
	324	* The default interrupt priority levels (0 = lowest, 7 = highest).
	325	*/
	326	static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = {
	327	7, /* Advanced Interrupt Controller */
	328	7, /* System Peripherals */
	329	1, /* Parallel IO Controller A */
	330	1, /* Parallel IO Controller B */
	331	1, /* Parallel IO Controller C */
	332	1, /* Parallel IO Controller D */
	333	5, /* USART 0 */
	334	5, /* USART 1 */
	335	5, /* USART 2 */
	336	5, /* USART 3 */
	337	0, /* Multimedia Card Interface */
	338	6, /* Two-Wire Interface 0 */
	339	6, /* Two-Wire Interface 1 */
	340	5, /* Serial Peripheral Interface */
	341	4, /* Serial Synchronous Controller 0 */
	342	4, /* Serial Synchronous Controller 1 */
	343	0, /* Timer Counter 0 */
	344	0, /* Timer Counter 1 */
	345	0, /* Timer Counter 2 */
	346	0,
	347	0, /* Touch Screen Controller */
	348	0, /* DMA Controller */
	349	2, /* USB Device High speed port */
	350	2, /* LCD Controller */
	351	6, /* AC97 Controller */
	352	0,
	353	0,
	354	0,
	355	0,
	356	0,
	357	0,
	358	0, /* Advanced Interrupt Controller */
	359	};
	360
8c3583b6	361	struct at91_init_soc __initdata at91sam9rl_soc = {
21d08b9d	362	.map_io = at91sam9rl_map_io,
92100c12	363	.default_irq_priority = at91sam9rl_default_irq_priority,
21d08b9d JCPV	364	.init = at91sam9rl_initialize,
21d08b9d JCPV	365	};