[deliverable/linux.git] / arch / arm / mach-at91 / at91sam9rl.c

/*
 * arch/arm/mach-at91/at91sam9rl.c
 *
 *  Copyright (C) 2005 SAN People
 *  Copyright (C) 2007 Atmel Corporation
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file COPYING in the main directory of this archive for
 * more details.
 */

#include <linux/module.h>
#include <linux/clk/at91_pmc.h>

#include <asm/proc-fns.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/system_misc.h>
#include <mach/cpu.h>
#include <mach/at91_dbgu.h>
#include <mach/at91sam9rl.h>

#include "at91_aic.h"
#include "at91_rstc.h"
#include "soc.h"
#include "generic.h"
#include "sam9_smc.h"
#include "pm.h"

/* --------------------------------------------------------------------
 *  Clocks
 * -------------------------------------------------------------------- */
#if defined(CONFIG_OLD_CLK_AT91)
#include "clock.h"

/*
 * The peripheral clocks.
 */
static struct clk pioA_clk = {
	.name		= "pioA_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_PIOA,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk pioB_clk = {
	.name		= "pioB_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_PIOB,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk pioC_clk = {
	.name		= "pioC_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_PIOC,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk pioD_clk = {
	.name		= "pioD_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_PIOD,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart0_clk = {
	.name		= "usart0_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_US0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart1_clk = {
	.name		= "usart1_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_US1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart2_clk = {
	.name		= "usart2_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_US2,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart3_clk = {
	.name		= "usart3_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_US3,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk mmc_clk = {
	.name		= "mci_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_MCI,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk twi0_clk = {
	.name		= "twi0_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_TWI0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk twi1_clk = {
	.name		= "twi1_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_TWI1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk spi_clk = {
	.name		= "spi_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_SPI,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk ssc0_clk = {
	.name		= "ssc0_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_SSC0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk ssc1_clk = {
	.name		= "ssc1_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_SSC1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk tc0_clk = {
	.name		= "tc0_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_TC0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk tc1_clk = {
	.name		= "tc1_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_TC1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk tc2_clk = {
	.name		= "tc2_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_TC2,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk pwm_clk = {
	.name		= "pwm_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_PWMC,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk tsc_clk = {
	.name		= "tsc_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_TSC,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk dma_clk = {
	.name		= "dma_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_DMA,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk udphs_clk = {
	.name		= "udphs_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_UDPHS,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk lcdc_clk = {
	.name		= "lcdc_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_LCDC,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk ac97_clk = {
	.name		= "ac97_clk",
	.pmc_mask	= 1 << AT91SAM9RL_ID_AC97C,
	.type		= CLK_TYPE_PERIPHERAL,
};

static struct clk *periph_clocks[] __initdata = {
	&pioA_clk,
	&pioB_clk,
	&pioC_clk,
	&pioD_clk,
	&usart0_clk,
	&usart1_clk,
	&usart2_clk,
	&usart3_clk,
	&mmc_clk,
	&twi0_clk,
	&twi1_clk,
	&spi_clk,
	&ssc0_clk,
	&ssc1_clk,
	&tc0_clk,
	&tc1_clk,
	&tc2_clk,
	&pwm_clk,
	&tsc_clk,
	&dma_clk,
	&udphs_clk,
	&lcdc_clk,
	&ac97_clk,
	// irq0
};

static struct clk_lookup periph_clocks_lookups[] = {
	CLKDEV_CON_DEV_ID("hclk", "at91sam9rl-lcdfb.0", &lcdc_clk),
	CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
	CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
	CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
	CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
	CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
	CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk),
	CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
	CLKDEV_CON_DEV_ID("pclk", "fffc0000.ssc", &ssc0_clk),
	CLKDEV_CON_DEV_ID("pclk", "fffc4000.ssc", &ssc1_clk),
	CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.0", &twi0_clk),
	CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.1", &twi1_clk),
	CLKDEV_CON_ID("pioA", &pioA_clk),
	CLKDEV_CON_ID("pioB", &pioB_clk),
	CLKDEV_CON_ID("pioC", &pioC_clk),
	CLKDEV_CON_ID("pioD", &pioD_clk),
	/* more lookup table for DT entries */
	CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
	CLKDEV_CON_DEV_ID("usart", "fffb0000.serial", &usart0_clk),
	CLKDEV_CON_DEV_ID("usart", "ffffb400.serial", &usart1_clk),
	CLKDEV_CON_DEV_ID("usart", "ffffb800.serial", &usart2_clk),
	CLKDEV_CON_DEV_ID("usart", "ffffbc00.serial", &usart3_clk),
	CLKDEV_CON_DEV_ID("t0_clk", "fffa0000.timer", &tc0_clk),
	CLKDEV_CON_DEV_ID("t1_clk", "fffa0000.timer", &tc1_clk),
	CLKDEV_CON_DEV_ID("t2_clk", "fffa0000.timer", &tc2_clk),
	CLKDEV_CON_DEV_ID("mci_clk", "fffa4000.mmc", &mmc_clk),
	CLKDEV_CON_DEV_ID(NULL, "fffa8000.i2c", &twi0_clk),
	CLKDEV_CON_DEV_ID(NULL, "fffac000.i2c", &twi1_clk),
	CLKDEV_CON_DEV_ID(NULL, "ffffc800.pwm", &pwm_clk),
	CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioA_clk),
	CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioB_clk),
	CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioC_clk),
	CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioD_clk),
};

static struct clk_lookup usart_clocks_lookups[] = {
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
	CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
};

/*
 * The two programmable clocks.
 * You must configure pin multiplexing to bring these signals out.
 */
static struct clk pck0 = {
	.name		= "pck0",
	.pmc_mask	= AT91_PMC_PCK0,
	.type		= CLK_TYPE_PROGRAMMABLE,
	.id		= 0,
};
static struct clk pck1 = {
	.name		= "pck1",
	.pmc_mask	= AT91_PMC_PCK1,
	.type		= CLK_TYPE_PROGRAMMABLE,
	.id		= 1,
};

static void __init at91sam9rl_register_clocks(void)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
		clk_register(periph_clocks[i]);

	clkdev_add_table(periph_clocks_lookups,
			 ARRAY_SIZE(periph_clocks_lookups));
	clkdev_add_table(usart_clocks_lookups,
			 ARRAY_SIZE(usart_clocks_lookups));

	clk_register(&pck0);
	clk_register(&pck1);
}
#endif

/* --------------------------------------------------------------------
 *  GPIO
 * -------------------------------------------------------------------- */

static struct at91_gpio_bank at91sam9rl_gpio[] __initdata = {
	{
		.id		= AT91SAM9RL_ID_PIOA,
		.regbase	= AT91SAM9RL_BASE_PIOA,
	}, {
		.id		= AT91SAM9RL_ID_PIOB,
		.regbase	= AT91SAM9RL_BASE_PIOB,
	}, {
		.id		= AT91SAM9RL_ID_PIOC,
		.regbase	= AT91SAM9RL_BASE_PIOC,
	}, {
		.id		= AT91SAM9RL_ID_PIOD,
		.regbase	= AT91SAM9RL_BASE_PIOD,
	}
};

/* --------------------------------------------------------------------
 *  AT91SAM9RL processor initialization
 * -------------------------------------------------------------------- */

static void __init at91sam9rl_map_io(void)
{
	unsigned long sram_size;

	switch (at91_soc_initdata.cidr & AT91_CIDR_SRAMSIZ) {
		case AT91_CIDR_SRAMSIZ_32K:
			sram_size = 2 * SZ_16K;
			break;
		case AT91_CIDR_SRAMSIZ_16K:
		default:
			sram_size = SZ_16K;
	}

	/* Map SRAM */
	at91_init_sram(0, AT91SAM9RL_SRAM_BASE, sram_size);
}

static void __init at91sam9rl_ioremap_registers(void)
{
	at91_ioremap_shdwc(AT91SAM9RL_BASE_SHDWC);
	at91_ioremap_rstc(AT91SAM9RL_BASE_RSTC);
	at91_ioremap_ramc(0, AT91SAM9RL_BASE_SDRAMC, 512);
	at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT);
	at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC);
	at91_ioremap_matrix(AT91SAM9RL_BASE_MATRIX);
	at91_pm_set_standby(at91sam9_sdram_standby);
}

static void __init at91sam9rl_initialize(void)
{
	arm_pm_idle = at91sam9_idle;
	arm_pm_restart = at91sam9_alt_restart;

	at91_sysirq_mask_rtc(AT91SAM9RL_BASE_RTC);
	at91_sysirq_mask_rtt(AT91SAM9RL_BASE_RTT);

	/* Register GPIO subsystem */
	at91_gpio_init(at91sam9rl_gpio, 4);
}

/* --------------------------------------------------------------------
 *  Interrupt initialization
 * -------------------------------------------------------------------- */

/*
 * The default interrupt priority levels (0 = lowest, 7 = highest).
 */
static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = {
	7,	/* Advanced Interrupt Controller */
	7,	/* System Peripherals */
	1,	/* Parallel IO Controller A */
	1,	/* Parallel IO Controller B */
	1,	/* Parallel IO Controller C */
	1,	/* Parallel IO Controller D */
	5,	/* USART 0 */
	5,	/* USART 1 */
	5,	/* USART 2 */
	5,	/* USART 3 */
	0,	/* Multimedia Card Interface */
	6,	/* Two-Wire Interface 0 */
	6,	/* Two-Wire Interface 1 */
	5,	/* Serial Peripheral Interface */
	4,	/* Serial Synchronous Controller 0 */
	4,	/* Serial Synchronous Controller 1 */
	0,	/* Timer Counter 0 */
	0,	/* Timer Counter 1 */
	0,	/* Timer Counter 2 */
	0,
	0,	/* Touch Screen Controller */
	0,	/* DMA Controller */
	2,	/* USB Device High speed port */
	2,	/* LCD Controller */
	6,	/* AC97 Controller */
	0,
	0,
	0,
	0,
	0,
	0,
	0,	/* Advanced Interrupt Controller */
};

AT91_SOC_START(at91sam9rl)
	.map_io = at91sam9rl_map_io,
	.default_irq_priority = at91sam9rl_default_irq_priority,
	.extern_irq = (1 << AT91SAM9RL_ID_IRQ0),
	.ioremap_registers = at91sam9rl_ioremap_registers,
#if defined(CONFIG_OLD_CLK_AT91)
	.register_clocks = at91sam9rl_register_clocks,
#endif
	.init = at91sam9rl_initialize,
AT91_SOC_END
Commit	Line	Data
877d7720 AV	1	/*
	2	* arch/arm/mach-at91/at91sam9rl.c
	3	*
	4	* Copyright (C) 2005 SAN People
	5	* Copyright (C) 2007 Atmel Corporation
	6	*
	7	* This file is subject to the terms and conditions of the GNU General Public
	8	* License. See the file COPYING in the main directory of this archive for
	9	* more details.
	10	*/
	11
	12	#include <linux/module.h>
2edb90ae	13	#include <linux/clk/at91_pmc.h>
877d7720	14
c9dfafba	15	#include <asm/proc-fns.h>
80b02c17	16	#include <asm/irq.h>
877d7720 AV	17	#include <asm/mach/arch.h>
877d7720 AV	18	#include <asm/mach/map.h>
9f97da78	19	#include <asm/system_misc.h>
a09e64fb	20	#include <mach/cpu.h>
8c3583b6	21	#include <mach/at91_dbgu.h>
a09e64fb	22	#include <mach/at91sam9rl.h>
877d7720	23
a510b9ba	24	#include "at91_aic.h"
f0995d08	25	#include "at91_rstc.h"
21d08b9d	26	#include "soc.h"
877d7720	27	#include "generic.h"
faee0cc3	28	#include "sam9_smc.h"
5ad945ea	29	#include "pm.h"
877d7720	30
877d7720 AV	31	/* --------------------------------------------------------------------
	32	* Clocks
	33	* -------------------------------------------------------------------- */
72a3fe97 AB	34	#if defined(CONFIG_OLD_CLK_AT91)
72a3fe97 AB	35	#include "clock.h"
877d7720 AV	36
	37	/*
	38	* The peripheral clocks.
	39	*/
	40	static struct clk pioA_clk = {
	41	.name = "pioA_clk",
	42	.pmc_mask = 1 << AT91SAM9RL_ID_PIOA,
	43	.type = CLK_TYPE_PERIPHERAL,
	44	};
	45	static struct clk pioB_clk = {
	46	.name = "pioB_clk",
	47	.pmc_mask = 1 << AT91SAM9RL_ID_PIOB,
	48	.type = CLK_TYPE_PERIPHERAL,
	49	};
	50	static struct clk pioC_clk = {
	51	.name = "pioC_clk",
	52	.pmc_mask = 1 << AT91SAM9RL_ID_PIOC,
	53	.type = CLK_TYPE_PERIPHERAL,
	54	};
	55	static struct clk pioD_clk = {
	56	.name = "pioD_clk",
	57	.pmc_mask = 1 << AT91SAM9RL_ID_PIOD,
	58	.type = CLK_TYPE_PERIPHERAL,
	59	};
	60	static struct clk usart0_clk = {
	61	.name = "usart0_clk",
	62	.pmc_mask = 1 << AT91SAM9RL_ID_US0,
	63	.type = CLK_TYPE_PERIPHERAL,
	64	};
	65	static struct clk usart1_clk = {
	66	.name = "usart1_clk",
	67	.pmc_mask = 1 << AT91SAM9RL_ID_US1,
	68	.type = CLK_TYPE_PERIPHERAL,
	69	};
	70	static struct clk usart2_clk = {
	71	.name = "usart2_clk",
	72	.pmc_mask = 1 << AT91SAM9RL_ID_US2,
	73	.type = CLK_TYPE_PERIPHERAL,
	74	};
	75	static struct clk usart3_clk = {
	76	.name = "usart3_clk",
	77	.pmc_mask = 1 << AT91SAM9RL_ID_US3,
	78	.type = CLK_TYPE_PERIPHERAL,
	79	};
	80	static struct clk mmc_clk = {
	81	.name = "mci_clk",
	82	.pmc_mask = 1 << AT91SAM9RL_ID_MCI,
	83	.type = CLK_TYPE_PERIPHERAL,
	84	};
	85	static struct clk twi0_clk = {
	86	.name = "twi0_clk",
	87	.pmc_mask = 1 << AT91SAM9RL_ID_TWI0,
	88	.type = CLK_TYPE_PERIPHERAL,
	89	};
	90	static struct clk twi1_clk = {
	91	.name = "twi1_clk",
	92	.pmc_mask = 1 << AT91SAM9RL_ID_TWI1,
	93	.type = CLK_TYPE_PERIPHERAL,
	94	};
	95	static struct clk spi_clk = {
	96	.name = "spi_clk",
	97	.pmc_mask = 1 << AT91SAM9RL_ID_SPI,
	98	.type = CLK_TYPE_PERIPHERAL,
	99	};
100	static struct clk ssc0_clk = {
101	.name = "ssc0_clk",
102	.pmc_mask = 1 << AT91SAM9RL_ID_SSC0,
103	.type = CLK_TYPE_PERIPHERAL,
104	};
105	static struct clk ssc1_clk = {
106	.name = "ssc1_clk",
107	.pmc_mask = 1 << AT91SAM9RL_ID_SSC1,
108	.type = CLK_TYPE_PERIPHERAL,
109	};
110	static struct clk tc0_clk = {
111	.name = "tc0_clk",
112	.pmc_mask = 1 << AT91SAM9RL_ID_TC0,
113	.type = CLK_TYPE_PERIPHERAL,
114	};
115	static struct clk tc1_clk = {
116	.name = "tc1_clk",
117	.pmc_mask = 1 << AT91SAM9RL_ID_TC1,
118	.type = CLK_TYPE_PERIPHERAL,
119	};
120	static struct clk tc2_clk = {
121	.name = "tc2_clk",
122	.pmc_mask = 1 << AT91SAM9RL_ID_TC2,
123	.type = CLK_TYPE_PERIPHERAL,
124	};
bb1ad68b AV	125	static struct clk pwm_clk = {
bb1ad68b AV	126	.name = "pwm_clk",
877d7720 AV	127	.pmc_mask = 1 << AT91SAM9RL_ID_PWMC,
	128	.type = CLK_TYPE_PERIPHERAL,
	129	};
	130	static struct clk tsc_clk = {
	131	.name = "tsc_clk",
	132	.pmc_mask = 1 << AT91SAM9RL_ID_TSC,
	133	.type = CLK_TYPE_PERIPHERAL,
	134	};
	135	static struct clk dma_clk = {
	136	.name = "dma_clk",
	137	.pmc_mask = 1 << AT91SAM9RL_ID_DMA,
	138	.type = CLK_TYPE_PERIPHERAL,
	139	};
	140	static struct clk udphs_clk = {
	141	.name = "udphs_clk",
	142	.pmc_mask = 1 << AT91SAM9RL_ID_UDPHS,
	143	.type = CLK_TYPE_PERIPHERAL,
	144	};
	145	static struct clk lcdc_clk = {
	146	.name = "lcdc_clk",
	147	.pmc_mask = 1 << AT91SAM9RL_ID_LCDC,
	148	.type = CLK_TYPE_PERIPHERAL,
	149	};
	150	static struct clk ac97_clk = {
	151	.name = "ac97_clk",
	152	.pmc_mask = 1 << AT91SAM9RL_ID_AC97C,
	153	.type = CLK_TYPE_PERIPHERAL,
	154	};
	155
	156	static struct clk *periph_clocks[] __initdata = {
	157	&pioA_clk,
	158	&pioB_clk,
	159	&pioC_clk,
	160	&pioD_clk,
	161	&usart0_clk,
	162	&usart1_clk,
	163	&usart2_clk,
	164	&usart3_clk,
	165	&mmc_clk,
	166	&twi0_clk,
	167	&twi1_clk,
	168	&spi_clk,
	169	&ssc0_clk,
	170	&ssc1_clk,
	171	&tc0_clk,
	172	&tc1_clk,
	173	&tc2_clk,
bb1ad68b	174	&pwm_clk,
877d7720 AV	175	&tsc_clk,
	176	&dma_clk,
	177	&udphs_clk,
	178	&lcdc_clk,
	179	&ac97_clk,
	180	// irq0
	181	};
	182
bd602995	183	static struct clk_lookup periph_clocks_lookups[] = {
bbd44f6b	184	CLKDEV_CON_DEV_ID("hclk", "at91sam9rl-lcdfb.0", &lcdc_clk),
9d87159e JCPV	185	CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
9d87159e JCPV	186	CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
bd602995 JCPV	187	CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
	188	CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
	189	CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
636036d2 BS	190	CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk),
636036d2 BS	191	CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
099343c6 BS	192	CLKDEV_CON_DEV_ID("pclk", "fffc0000.ssc", &ssc0_clk),
099343c6 BS	193	CLKDEV_CON_DEV_ID("pclk", "fffc4000.ssc", &ssc1_clk),
fac368a0 NV	194	CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.0", &twi0_clk),
fac368a0 NV	195	CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.1", &twi1_clk),
619d4a4b JCPV	196	CLKDEV_CON_ID("pioA", &pioA_clk),
	197	CLKDEV_CON_ID("pioB", &pioB_clk),
	198	CLKDEV_CON_ID("pioC", &pioC_clk),
	199	CLKDEV_CON_ID("pioD", &pioD_clk),
09ab012a AB	200	/* more lookup table for DT entries */
	201	CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
	202	CLKDEV_CON_DEV_ID("usart", "fffb0000.serial", &usart0_clk),
	203	CLKDEV_CON_DEV_ID("usart", "ffffb400.serial", &usart1_clk),
	204	CLKDEV_CON_DEV_ID("usart", "ffffb800.serial", &usart2_clk),
	205	CLKDEV_CON_DEV_ID("usart", "ffffbc00.serial", &usart3_clk),
	206	CLKDEV_CON_DEV_ID("t0_clk", "fffa0000.timer", &tc0_clk),
	207	CLKDEV_CON_DEV_ID("t1_clk", "fffa0000.timer", &tc1_clk),
	208	CLKDEV_CON_DEV_ID("t2_clk", "fffa0000.timer", &tc2_clk),
	209	CLKDEV_CON_DEV_ID("mci_clk", "fffa4000.mmc", &mmc_clk),
	210	CLKDEV_CON_DEV_ID(NULL, "fffa8000.i2c", &twi0_clk),
	211	CLKDEV_CON_DEV_ID(NULL, "fffac000.i2c", &twi1_clk),
	212	CLKDEV_CON_DEV_ID(NULL, "ffffc800.pwm", &pwm_clk),
	213	CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioA_clk),
	214	CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioB_clk),
	215	CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioC_clk),
	216	CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioD_clk),
bd602995 JCPV	217	};
	218
	219	static struct clk_lookup usart_clocks_lookups[] = {
	220	CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
	221	CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
	222	CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
	223	CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
	224	CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
	225	};
	226
877d7720 AV	227	/*
	228	* The two programmable clocks.
	229	* You must configure pin multiplexing to bring these signals out.
	230	*/
	231	static struct clk pck0 = {
	232	.name = "pck0",
	233	.pmc_mask = AT91_PMC_PCK0,
	234	.type = CLK_TYPE_PROGRAMMABLE,
	235	.id = 0,
	236	};
	237	static struct clk pck1 = {
	238	.name = "pck1",
	239	.pmc_mask = AT91_PMC_PCK1,
	240	.type = CLK_TYPE_PROGRAMMABLE,
	241	.id = 1,
	242	};
	243
	244	static void __init at91sam9rl_register_clocks(void)
	245	{
	246	int i;
	247
	248	for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
	249	clk_register(periph_clocks[i]);
	250
bd602995 JCPV	251	clkdev_add_table(periph_clocks_lookups,
	252	ARRAY_SIZE(periph_clocks_lookups));
	253	clkdev_add_table(usart_clocks_lookups,
	254	ARRAY_SIZE(usart_clocks_lookups));
	255
877d7720 AV	256	clk_register(&pck0);
	257	clk_register(&pck1);
	258	}
72a3fe97	259	#endif
877d7720 AV	260
	261	/* --------------------------------------------------------------------
	262	* GPIO
	263	* -------------------------------------------------------------------- */
	264
1a2d9156	265	static struct at91_gpio_bank at91sam9rl_gpio[] __initdata = {
877d7720 AV	266	{
877d7720 AV	267	.id = AT91SAM9RL_ID_PIOA,
80e91cb8	268	.regbase = AT91SAM9RL_BASE_PIOA,
877d7720 AV	269	}, {
877d7720 AV	270	.id = AT91SAM9RL_ID_PIOB,
80e91cb8	271	.regbase = AT91SAM9RL_BASE_PIOB,
877d7720 AV	272	}, {
877d7720 AV	273	.id = AT91SAM9RL_ID_PIOC,
80e91cb8	274	.regbase = AT91SAM9RL_BASE_PIOC,
877d7720 AV	275	}, {
877d7720 AV	276	.id = AT91SAM9RL_ID_PIOD,
80e91cb8	277	.regbase = AT91SAM9RL_BASE_PIOD,
877d7720 AV	278	}
	279	};
	280
877d7720 AV	281	/* --------------------------------------------------------------------
	282	* AT91SAM9RL processor initialization
	283	* -------------------------------------------------------------------- */
	284
21d08b9d	285	static void __init at91sam9rl_map_io(void)
877d7720	286	{
8c3583b6	287	unsigned long sram_size;
877d7720	288
8c3583b6	289	switch (at91_soc_initdata.cidr & AT91_CIDR_SRAMSIZ) {
877d7720 AV	290	case AT91_CIDR_SRAMSIZ_32K:
	291	sram_size = 2 * SZ_16K;
	292	break;
	293	case AT91_CIDR_SRAMSIZ_16K:
	294	default:
	295	sram_size = SZ_16K;
	296	}
	297
877d7720	298	/* Map SRAM */
f0051d82	299	at91_init_sram(0, AT91SAM9RL_SRAM_BASE, sram_size);
1b021a3b	300	}
877d7720	301
cfa5a1fe JCPV	302	static void __init at91sam9rl_ioremap_registers(void)
cfa5a1fe JCPV	303	{
f22deee5	304	at91_ioremap_shdwc(AT91SAM9RL_BASE_SHDWC);
e9f68b5c	305	at91_ioremap_rstc(AT91SAM9RL_BASE_RSTC);
f363c407	306	at91_ioremap_ramc(0, AT91SAM9RL_BASE_SDRAMC, 512);
4ab0c599	307	at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT);
faee0cc3	308	at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC);
4342d647	309	at91_ioremap_matrix(AT91SAM9RL_BASE_MATRIX);
6b625891	310	at91_pm_set_standby(at91sam9_sdram_standby);
cfa5a1fe JCPV	311	}
cfa5a1fe JCPV	312
46539374	313	static void __init at91sam9rl_initialize(void)
1b021a3b	314	{
0d781716	315	arm_pm_idle = at91sam9_idle;
1b2073e7	316	arm_pm_restart = at91sam9_alt_restart;
877d7720	317
6de714c2	318	at91_sysirq_mask_rtc(AT91SAM9RL_BASE_RTC);
94c4c79f	319	at91_sysirq_mask_rtt(AT91SAM9RL_BASE_RTT);
6de714c2	320
877d7720 AV	321	/* Register GPIO subsystem */
	322	at91_gpio_init(at91sam9rl_gpio, 4);
	323	}
	324
	325	/* --------------------------------------------------------------------
	326	* Interrupt initialization
	327	* -------------------------------------------------------------------- */
	328
	329	/*
	330	* The default interrupt priority levels (0 = lowest, 7 = highest).
	331	*/
	332	static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = {
	333	7, /* Advanced Interrupt Controller */
	334	7, /* System Peripherals */
	335	1, /* Parallel IO Controller A */
	336	1, /* Parallel IO Controller B */
	337	1, /* Parallel IO Controller C */
	338	1, /* Parallel IO Controller D */
	339	5, /* USART 0 */
	340	5, /* USART 1 */
	341	5, /* USART 2 */
	342	5, /* USART 3 */
	343	0, /* Multimedia Card Interface */
	344	6, /* Two-Wire Interface 0 */
	345	6, /* Two-Wire Interface 1 */
	346	5, /* Serial Peripheral Interface */
	347	4, /* Serial Synchronous Controller 0 */
	348	4, /* Serial Synchronous Controller 1 */
	349	0, /* Timer Counter 0 */
	350	0, /* Timer Counter 1 */
	351	0, /* Timer Counter 2 */
	352	0,
	353	0, /* Touch Screen Controller */
	354	0, /* DMA Controller */
	355	2, /* USB Device High speed port */
	356	2, /* LCD Controller */
	357	6, /* AC97 Controller */
	358	0,
	359	0,
	360	0,
	361	0,
	362	0,
	363	0,
	364	0, /* Advanced Interrupt Controller */
	365	};
	366
84ddb087	367	AT91_SOC_START(at91sam9rl)
21d08b9d	368	.map_io = at91sam9rl_map_io,
92100c12	369	.default_irq_priority = at91sam9rl_default_irq_priority,
546c830c	370	.extern_irq = (1 << AT91SAM9RL_ID_IRQ0),
cfa5a1fe	371	.ioremap_registers = at91sam9rl_ioremap_registers,
72a3fe97	372	#if defined(CONFIG_OLD_CLK_AT91)
51ddec76	373	.register_clocks = at91sam9rl_register_clocks,
72a3fe97	374	#endif
21d08b9d	375	.init = at91sam9rl_initialize,
8d39e0fd	376	AT91_SOC_END