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[MTD] [NAND] rename at91_nand -> atmel_nand: internal symbols
[deliverable/linux.git] / arch / arm / mach-at91 / at91sam9rl_devices.c
CommitLineData
877d7720
AV		 1/*
2 * Copyright (C) 2007 Atmel Corporation
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file COPYING in the main directory of this archive for
6 * more details.
7 */
8
9#include <asm/mach/arch.h>
10#include <asm/mach/map.h>
11
c6686ff9 12#include <linux/dma-mapping.h>
877d7720 13#include <linux/platform_device.h>
f230d3f5 14#include <linux/i2c-gpio.h>
877d7720 15
f230d3f5 16#include <linux/fb.h>
877d7720
AV		 17#include <video/atmel_lcdc.h>
18
19#include <asm/arch/board.h>
20#include <asm/arch/gpio.h>
21#include <asm/arch/at91sam9rl.h>
22#include <asm/arch/at91sam9rl_matrix.h>
b78eabde 23#include <asm/arch/at91sam9_smc.h>
877d7720
AV		 24
25#include "generic.h"
26
877d7720
AV		 27
28/* --------------------------------------------------------------------
29 * MMC / SD
30 * -------------------------------------------------------------------- */
31
32#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
c6686ff9 33static u64 mmc_dmamask = DMA_BIT_MASK(32);
877d7720
AV		 34static struct at91_mmc_data mmc_data;
35
36static struct resource mmc_resources[] = {
37 [0] = {
38 .start = AT91SAM9RL_BASE_MCI,
39 .end = AT91SAM9RL_BASE_MCI + SZ_16K - 1,
40 .flags = IORESOURCE_MEM,
41 },
42 [1] = {
43 .start = AT91SAM9RL_ID_MCI,
44 .end = AT91SAM9RL_ID_MCI,
45 .flags = IORESOURCE_IRQ,
46 },
47};
48
49static struct platform_device at91sam9rl_mmc_device = {
50 .name = "at91_mci",
51 .id = -1,
52 .dev = {
53 .dma_mask = &mmc_dmamask,
c6686ff9 54 .coherent_dma_mask = DMA_BIT_MASK(32),
877d7720
AV		 55 .platform_data = &mmc_data,
56 },
57 .resource = mmc_resources,
58 .num_resources = ARRAY_SIZE(mmc_resources),
59};
60
61void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
62{
63 if (!data)
64 return;
65
66 /* input/irq */
67 if (data->det_pin) {
68 at91_set_gpio_input(data->det_pin, 1);
69 at91_set_deglitch(data->det_pin, 1);
70 }
71 if (data->wp_pin)
72 at91_set_gpio_input(data->wp_pin, 1);
73 if (data->vcc_pin)
74 at91_set_gpio_output(data->vcc_pin, 0);
75
76 /* CLK */
77 at91_set_A_periph(AT91_PIN_PA2, 0);
78
79 /* CMD */
80 at91_set_A_periph(AT91_PIN_PA1, 1);
81
82 /* DAT0, maybe DAT1..DAT3 */
83 at91_set_A_periph(AT91_PIN_PA0, 1);
84 if (data->wire4) {
85 at91_set_A_periph(AT91_PIN_PA3, 1);
86 at91_set_A_periph(AT91_PIN_PA4, 1);
87 at91_set_A_periph(AT91_PIN_PA5, 1);
88 }
89
90 mmc_data = *data;
91 platform_device_register(&at91sam9rl_mmc_device);
92}
93#else
94void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
95#endif
96
97
98/* --------------------------------------------------------------------
99 * NAND / SmartMedia
100 * -------------------------------------------------------------------- */
101
102#if defined(CONFIG_MTD_NAND_AT91) || defined(CONFIG_MTD_NAND_AT91_MODULE)
3c3796cc 103static struct atmel_nand_data nand_data;
877d7720
AV		 104
105#define NAND_BASE AT91_CHIPSELECT_3
106
107static struct resource nand_resources[] = {
d7a2415f 108 [0] = {
877d7720
AV		 109 .start = NAND_BASE,
110 .end = NAND_BASE + SZ_256M - 1,
111 .flags = IORESOURCE_MEM,
d7a2415f
AV		 112 },
113 [1] = {
114 .start = AT91_BASE_SYS + AT91_ECC,
115 .end = AT91_BASE_SYS + AT91_ECC + SZ_512 - 1,
116 .flags = IORESOURCE_MEM,
877d7720
AV		 117 }
118};
119
3c3796cc
HS		 120static struct platform_device atmel_nand_device = {
121 .name = "atmel_nand",
877d7720
AV		 122 .id = -1,
123 .dev = {
124 .platform_data = &nand_data,
125 },
126 .resource = nand_resources,
127 .num_resources = ARRAY_SIZE(nand_resources),
128};
129
3c3796cc 130void __init at91_add_device_nand(struct atmel_nand_data *data)
877d7720
AV		 131{
132 unsigned long csa;
133
134 if (!data)
135 return;
136
137 csa = at91_sys_read(AT91_MATRIX_EBICSA);
138 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
139
140 /* set the bus interface characteristics */
141 at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0)
142 | AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
143
144 at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(2) | AT91_SMC_NCS_WRPULSE_(5)
145 | AT91_SMC_NRDPULSE_(2) | AT91_SMC_NCS_RDPULSE_(5));
146
147 at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7));
148
149 at91_sys_write(AT91_SMC_MODE(3), AT91_SMC_DBW_8 | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(1));
150
151 /* enable pin */
152 if (data->enable_pin)
153 at91_set_gpio_output(data->enable_pin, 1);
154
155 /* ready/busy pin */
156 if (data->rdy_pin)
157 at91_set_gpio_input(data->rdy_pin, 1);
158
159 /* card detect pin */
160 if (data->det_pin)
161 at91_set_gpio_input(data->det_pin, 1);
162
163 at91_set_A_periph(AT91_PIN_PB4, 0); /* NANDOE */
164 at91_set_A_periph(AT91_PIN_PB5, 0); /* NANDWE */
165
166 nand_data = *data;
3c3796cc 167 platform_device_register(&atmel_nand_device);
877d7720
AV		 168}
169
170#else
3c3796cc 171void __init at91_add_device_nand(struct atmel_nand_data *data) {}
877d7720
AV		 172#endif
173
174
175/* --------------------------------------------------------------------
176 * TWI (i2c)
177 * -------------------------------------------------------------------- */
178
f230d3f5
AV		 179/*
180 * Prefer the GPIO code since the TWI controller isn't robust
181 * (gets overruns and underruns under load) and can only issue
182 * repeated STARTs in one scenario (the driver doesn't yet handle them).
183 */
184#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
185
186static struct i2c_gpio_platform_data pdata = {
187 .sda_pin = AT91_PIN_PA23,
188 .sda_is_open_drain = 1,
189 .scl_pin = AT91_PIN_PA24,
190 .scl_is_open_drain = 1,
191 .udelay = 2, /* ~100 kHz */
192};
193
194static struct platform_device at91sam9rl_twi_device = {
195 .name = "i2c-gpio",
196 .id = -1,
197 .dev.platform_data = &pdata,
198};
199
200void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
201{
202 at91_set_GPIO_periph(AT91_PIN_PA23, 1); /* TWD (SDA) */
203 at91_set_multi_drive(AT91_PIN_PA23, 1);
204
205 at91_set_GPIO_periph(AT91_PIN_PA24, 1); /* TWCK (SCL) */
206 at91_set_multi_drive(AT91_PIN_PA24, 1);
207
208 i2c_register_board_info(0, devices, nr_devices);
209 platform_device_register(&at91sam9rl_twi_device);
210}
211
212#elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
877d7720
AV		 213
214static struct resource twi_resources[] = {
215 [0] = {
216 .start = AT91SAM9RL_BASE_TWI0,
217 .end = AT91SAM9RL_BASE_TWI0 + SZ_16K - 1,
218 .flags = IORESOURCE_MEM,
219 },
220 [1] = {
221 .start = AT91SAM9RL_ID_TWI0,
222 .end = AT91SAM9RL_ID_TWI0,
223 .flags = IORESOURCE_IRQ,
224 },
225};
226
227static struct platform_device at91sam9rl_twi_device = {
228 .name = "at91_i2c",
229 .id = -1,
230 .resource = twi_resources,
231 .num_resources = ARRAY_SIZE(twi_resources),
232};
233
f230d3f5 234void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
877d7720
AV		 235{
236 /* pins used for TWI interface */
237 at91_set_A_periph(AT91_PIN_PA23, 0); /* TWD */
238 at91_set_multi_drive(AT91_PIN_PA23, 1);
239
240 at91_set_A_periph(AT91_PIN_PA24, 0); /* TWCK */
241 at91_set_multi_drive(AT91_PIN_PA24, 1);
242
f230d3f5 243 i2c_register_board_info(0, devices, nr_devices);
877d7720
AV		 244 platform_device_register(&at91sam9rl_twi_device);
245}
246#else
f230d3f5 247void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
877d7720
AV		 248#endif
249
250
251/* --------------------------------------------------------------------
252 * SPI
253 * -------------------------------------------------------------------- */
254
255#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
c6686ff9 256static u64 spi_dmamask = DMA_BIT_MASK(32);
877d7720
AV		 257
258static struct resource spi_resources[] = {
259 [0] = {
260 .start = AT91SAM9RL_BASE_SPI,
261 .end = AT91SAM9RL_BASE_SPI + SZ_16K - 1,
262 .flags = IORESOURCE_MEM,
263 },
264 [1] = {
265 .start = AT91SAM9RL_ID_SPI,
266 .end = AT91SAM9RL_ID_SPI,
267 .flags = IORESOURCE_IRQ,
268 },
269};
270
271static struct platform_device at91sam9rl_spi_device = {
272 .name = "atmel_spi",
273 .id = 0,
274 .dev = {
275 .dma_mask = &spi_dmamask,
c6686ff9 276 .coherent_dma_mask = DMA_BIT_MASK(32),
877d7720
AV		 277 },
278 .resource = spi_resources,
279 .num_resources = ARRAY_SIZE(spi_resources),
280};
281
282static const unsigned spi_standard_cs[4] = { AT91_PIN_PA28, AT91_PIN_PB7, AT91_PIN_PD8, AT91_PIN_PD9 };
283
284
285void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
286{
287 int i;
288 unsigned long cs_pin;
289
290 at91_set_A_periph(AT91_PIN_PA25, 0); /* MISO */
291 at91_set_A_periph(AT91_PIN_PA26, 0); /* MOSI */
292 at91_set_A_periph(AT91_PIN_PA27, 0); /* SPCK */
293
294 /* Enable SPI chip-selects */
295 for (i = 0; i < nr_devices; i++) {
296 if (devices[i].controller_data)
297 cs_pin = (unsigned long) devices[i].controller_data;
298 else
299 cs_pin = spi_standard_cs[devices[i].chip_select];
300
301 /* enable chip-select pin */
302 at91_set_gpio_output(cs_pin, 1);
303
304 /* pass chip-select pin to driver */
305 devices[i].controller_data = (void *) cs_pin;
306 }
307
308 spi_register_board_info(devices, nr_devices);
309 platform_device_register(&at91sam9rl_spi_device);
310}
311#else
312void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
313#endif
314
315
316/* --------------------------------------------------------------------
317 * LCD Controller
318 * -------------------------------------------------------------------- */
319
320#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
c6686ff9 321static u64 lcdc_dmamask = DMA_BIT_MASK(32);
877d7720
AV		 322static struct atmel_lcdfb_info lcdc_data;
323
324static struct resource lcdc_resources[] = {
325 [0] = {
326 .start = AT91SAM9RL_LCDC_BASE,
327 .end = AT91SAM9RL_LCDC_BASE + SZ_4K - 1,
328 .flags = IORESOURCE_MEM,
329 },
330 [1] = {
331 .start = AT91SAM9RL_ID_LCDC,
332 .end = AT91SAM9RL_ID_LCDC,
333 .flags = IORESOURCE_IRQ,
334 },
335#if defined(CONFIG_FB_INTSRAM)
336 [2] = {
337 .start = AT91SAM9RL_SRAM_BASE,
338 .end = AT91SAM9RL_SRAM_BASE + AT91SAM9RL_SRAM_SIZE - 1,
339 .flags = IORESOURCE_MEM,
340 },
341#endif
342};
343
344static struct platform_device at91_lcdc_device = {
345 .name = "atmel_lcdfb",
346 .id = 0,
347 .dev = {
348 .dma_mask = &lcdc_dmamask,
c6686ff9 349 .coherent_dma_mask = DMA_BIT_MASK(32),
877d7720
AV		 350 .platform_data = &lcdc_data,
351 },
352 .resource = lcdc_resources,
353 .num_resources = ARRAY_SIZE(lcdc_resources),
354};
355
356void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
357{
358 if (!data) {
359 return;
360 }
361
362 at91_set_B_periph(AT91_PIN_PC1, 0); /* LCDPWR */
363 at91_set_A_periph(AT91_PIN_PC5, 0); /* LCDHSYNC */
364 at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDDOTCK */
365 at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDDEN */
366 at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDCC */
367 at91_set_B_periph(AT91_PIN_PC9, 0); /* LCDD3 */
368 at91_set_B_periph(AT91_PIN_PC10, 0); /* LCDD4 */
369 at91_set_B_periph(AT91_PIN_PC11, 0); /* LCDD5 */
370 at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD6 */
371 at91_set_B_periph(AT91_PIN_PC13, 0); /* LCDD7 */
372 at91_set_B_periph(AT91_PIN_PC15, 0); /* LCDD11 */
373 at91_set_B_periph(AT91_PIN_PC16, 0); /* LCDD12 */
374 at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD13 */
375 at91_set_B_periph(AT91_PIN_PC18, 0); /* LCDD14 */
376 at91_set_B_periph(AT91_PIN_PC19, 0); /* LCDD15 */
377 at91_set_B_periph(AT91_PIN_PC20, 0); /* LCDD18 */
378 at91_set_B_periph(AT91_PIN_PC21, 0); /* LCDD19 */
379 at91_set_B_periph(AT91_PIN_PC22, 0); /* LCDD20 */
380 at91_set_B_periph(AT91_PIN_PC23, 0); /* LCDD21 */
381 at91_set_B_periph(AT91_PIN_PC24, 0); /* LCDD22 */
382 at91_set_B_periph(AT91_PIN_PC25, 0); /* LCDD23 */
383
01d3a5e7
HS		 384#ifdef CONFIG_FB_INTSRAM
385 {
386 void __iomem *fb;
387 struct resource *fb_res = &lcdc_resources[2];
388 size_t fb_len = fb_res->end - fb_res->start + 1;
389
390 fb = ioremap_writecombine(fb_res->start, fb_len);
391 if (fb) {
392 memset(fb, 0, fb_len);
393 iounmap(fb, fb_len);
394 }
395 }
396#endif
397
877d7720
AV		 398 lcdc_data = *data;
399 platform_device_register(&at91_lcdc_device);
400}
401#else
402void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
403#endif
404
405
e5f40bfa
AV		 406/* --------------------------------------------------------------------
407 * Timer/Counter block
408 * -------------------------------------------------------------------- */
409
410#ifdef CONFIG_ATMEL_TCLIB
411
412static struct resource tcb_resources[] = {
413 [0] = {
414 .start = AT91SAM9RL_BASE_TCB0,
415 .end = AT91SAM9RL_BASE_TCB0 + SZ_16K - 1,
416 .flags = IORESOURCE_MEM,
417 },
418 [1] = {
419 .start = AT91SAM9RL_ID_TC0,
420 .end = AT91SAM9RL_ID_TC0,
421 .flags = IORESOURCE_IRQ,
422 },
423 [2] = {
424 .start = AT91SAM9RL_ID_TC1,
425 .end = AT91SAM9RL_ID_TC1,
426 .flags = IORESOURCE_IRQ,
427 },
428 [3] = {
429 .start = AT91SAM9RL_ID_TC2,
430 .end = AT91SAM9RL_ID_TC2,
431 .flags = IORESOURCE_IRQ,
432 },
433};
434
435static struct platform_device at91sam9rl_tcb_device = {
436 .name = "atmel_tcb",
437 .id = 0,
438 .resource = tcb_resources,
439 .num_resources = ARRAY_SIZE(tcb_resources),
440};
441
442static void __init at91_add_device_tc(void)
443{
444 /* this chip has a separate clock and irq for each TC channel */
445 at91_clock_associate("tc0_clk", &at91sam9rl_tcb_device.dev, "t0_clk");
446 at91_clock_associate("tc1_clk", &at91sam9rl_tcb_device.dev, "t1_clk");
447 at91_clock_associate("tc2_clk", &at91sam9rl_tcb_device.dev, "t2_clk");
448 platform_device_register(&at91sam9rl_tcb_device);
449}
450#else
451static void __init at91_add_device_tc(void) { }
452#endif
453
454
884f5a6a
AV		 455/* --------------------------------------------------------------------
456 * RTC
457 * -------------------------------------------------------------------- */
458
459#if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE)
460static struct platform_device at91sam9rl_rtc_device = {
461 .name = "at91_rtc",
462 .id = -1,
463 .num_resources = 0,
464};
465
466static void __init at91_add_device_rtc(void)
467{
468 platform_device_register(&at91sam9rl_rtc_device);
469}
470#else
471static void __init at91_add_device_rtc(void) {}
472#endif
473
474
475/* --------------------------------------------------------------------
476 * RTT
477 * -------------------------------------------------------------------- */
478
479static struct resource rtt_resources[] = {
480 {
481 .start = AT91_BASE_SYS + AT91_RTT,
482 .end = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1,
483 .flags = IORESOURCE_MEM,
484 }
485};
486
487static struct platform_device at91sam9rl_rtt_device = {
488 .name = "at91_rtt",
4fd9212c 489 .id = 0,
884f5a6a
AV		 490 .resource = rtt_resources,
491 .num_resources = ARRAY_SIZE(rtt_resources),
492};
493
494static void __init at91_add_device_rtt(void)
495{
496 platform_device_register(&at91sam9rl_rtt_device);
497}
498
499
500/* --------------------------------------------------------------------
501 * Watchdog
502 * -------------------------------------------------------------------- */
503
504#if defined(CONFIG_AT91SAM9_WATCHDOG) || defined(CONFIG_AT91SAM9_WATCHDOG_MODULE)
505static struct platform_device at91sam9rl_wdt_device = {
506 .name = "at91_wdt",
507 .id = -1,
508 .num_resources = 0,
509};
510
511static void __init at91_add_device_watchdog(void)
512{
513 platform_device_register(&at91sam9rl_wdt_device);
514}
515#else
516static void __init at91_add_device_watchdog(void) {}
517#endif
518
519
bfbc3266
AV		 520/* --------------------------------------------------------------------
521 * SSC -- Synchronous Serial Controller
522 * -------------------------------------------------------------------- */
523
524#if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
525static u64 ssc0_dmamask = DMA_BIT_MASK(32);
526
527static struct resource ssc0_resources[] = {
528 [0] = {
529 .start = AT91SAM9RL_BASE_SSC0,
530 .end = AT91SAM9RL_BASE_SSC0 + SZ_16K - 1,
531 .flags = IORESOURCE_MEM,
532 },
533 [1] = {
534 .start = AT91SAM9RL_ID_SSC0,
535 .end = AT91SAM9RL_ID_SSC0,
536 .flags = IORESOURCE_IRQ,
537 },
538};
539
540static struct platform_device at91sam9rl_ssc0_device = {
541 .name = "ssc",
542 .id = 0,
543 .dev = {
544 .dma_mask = &ssc0_dmamask,
545 .coherent_dma_mask = DMA_BIT_MASK(32),
546 },
547 .resource = ssc0_resources,
548 .num_resources = ARRAY_SIZE(ssc0_resources),
549};
550
551static inline void configure_ssc0_pins(unsigned pins)
552{
553 if (pins & ATMEL_SSC_TF)
554 at91_set_A_periph(AT91_PIN_PC0, 1);
555 if (pins & ATMEL_SSC_TK)
556 at91_set_A_periph(AT91_PIN_PC1, 1);
557 if (pins & ATMEL_SSC_TD)
558 at91_set_A_periph(AT91_PIN_PA15, 1);
559 if (pins & ATMEL_SSC_RD)
560 at91_set_A_periph(AT91_PIN_PA16, 1);
561 if (pins & ATMEL_SSC_RK)
562 at91_set_B_periph(AT91_PIN_PA10, 1);
563 if (pins & ATMEL_SSC_RF)
564 at91_set_B_periph(AT91_PIN_PA22, 1);
565}
566
567static u64 ssc1_dmamask = DMA_BIT_MASK(32);
568
569static struct resource ssc1_resources[] = {
570 [0] = {
571 .start = AT91SAM9RL_BASE_SSC1,
572 .end = AT91SAM9RL_BASE_SSC1 + SZ_16K - 1,
573 .flags = IORESOURCE_MEM,
574 },
575 [1] = {
576 .start = AT91SAM9RL_ID_SSC1,
577 .end = AT91SAM9RL_ID_SSC1,
578 .flags = IORESOURCE_IRQ,
579 },
580};
581
582static struct platform_device at91sam9rl_ssc1_device = {
583 .name = "ssc",
584 .id = 1,
585 .dev = {
586 .dma_mask = &ssc1_dmamask,
587 .coherent_dma_mask = DMA_BIT_MASK(32),
588 },
589 .resource = ssc1_resources,
590 .num_resources = ARRAY_SIZE(ssc1_resources),
591};
592
593static inline void configure_ssc1_pins(unsigned pins)
594{
595 if (pins & ATMEL_SSC_TF)
596 at91_set_B_periph(AT91_PIN_PA29, 1);
597 if (pins & ATMEL_SSC_TK)
598 at91_set_B_periph(AT91_PIN_PA30, 1);
599 if (pins & ATMEL_SSC_TD)
600 at91_set_B_periph(AT91_PIN_PA13, 1);
601 if (pins & ATMEL_SSC_RD)
602 at91_set_B_periph(AT91_PIN_PA14, 1);
603 if (pins & ATMEL_SSC_RK)
604 at91_set_B_periph(AT91_PIN_PA9, 1);
605 if (pins & ATMEL_SSC_RF)
606 at91_set_B_periph(AT91_PIN_PA8, 1);
607}
608
609/*
bfbc3266
AV		 610 * SSC controllers are accessed through library code, instead of any
611 * kind of all-singing/all-dancing driver. For example one could be
612 * used by a particular I2S audio codec's driver, while another one
613 * on the same system might be used by a custom data capture driver.
614 */
615void __init at91_add_device_ssc(unsigned id, unsigned pins)
616{
617 struct platform_device *pdev;
618
619 /*
620 * NOTE: caller is responsible for passing information matching
621 * "pins" to whatever will be using each particular controller.
622 */
623 switch (id) {
624 case AT91SAM9RL_ID_SSC0:
625 pdev = &at91sam9rl_ssc0_device;
626 configure_ssc0_pins(pins);
627 at91_clock_associate("ssc0_clk", &pdev->dev, "pclk");
628 break;
629 case AT91SAM9RL_ID_SSC1:
630 pdev = &at91sam9rl_ssc1_device;
631 configure_ssc1_pins(pins);
632 at91_clock_associate("ssc1_clk", &pdev->dev, "pclk");
633 break;
634 default:
635 return;
636 }
637
638 platform_device_register(pdev);
639}
640
641#else
642void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
643#endif
644
645
877d7720
AV		 646/* --------------------------------------------------------------------
647 * UART
648 * -------------------------------------------------------------------- */
649
650#if defined(CONFIG_SERIAL_ATMEL)
651static struct resource dbgu_resources[] = {
652 [0] = {
653 .start = AT91_VA_BASE_SYS + AT91_DBGU,
654 .end = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
655 .flags = IORESOURCE_MEM,
656 },
657 [1] = {
658 .start = AT91_ID_SYS,
659 .end = AT91_ID_SYS,
660 .flags = IORESOURCE_IRQ,
661 },
662};
663
664static struct atmel_uart_data dbgu_data = {
665 .use_dma_tx = 0,
666 .use_dma_rx = 0, /* DBGU not capable of receive DMA */
667 .regs = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
668};
669
c6686ff9
AV		 670static u64 dbgu_dmamask = DMA_BIT_MASK(32);
671
877d7720
AV		 672static struct platform_device at91sam9rl_dbgu_device = {
673 .name = "atmel_usart",
674 .id = 0,
675 .dev = {
c6686ff9
AV		 676 .dma_mask = &dbgu_dmamask,
677 .coherent_dma_mask = DMA_BIT_MASK(32),
678 .platform_data = &dbgu_data,
877d7720
AV		 679 },
680 .resource = dbgu_resources,
681 .num_resources = ARRAY_SIZE(dbgu_resources),
682};
683
684static inline void configure_dbgu_pins(void)
685{
686 at91_set_A_periph(AT91_PIN_PA21, 0); /* DRXD */
687 at91_set_A_periph(AT91_PIN_PA22, 1); /* DTXD */
688}
689
690static struct resource uart0_resources[] = {
691 [0] = {
692 .start = AT91SAM9RL_BASE_US0,
693 .end = AT91SAM9RL_BASE_US0 + SZ_16K - 1,
694 .flags = IORESOURCE_MEM,
695 },
696 [1] = {
697 .start = AT91SAM9RL_ID_US0,
698 .end = AT91SAM9RL_ID_US0,
699 .flags = IORESOURCE_IRQ,
700 },
701};
702
703static struct atmel_uart_data uart0_data = {
704 .use_dma_tx = 1,
705 .use_dma_rx = 1,
706};
707
c6686ff9
AV		 708static u64 uart0_dmamask = DMA_BIT_MASK(32);
709
877d7720
AV		 710static struct platform_device at91sam9rl_uart0_device = {
711 .name = "atmel_usart",
712 .id = 1,
713 .dev = {
c6686ff9
AV		 714 .dma_mask = &uart0_dmamask,
715 .coherent_dma_mask = DMA_BIT_MASK(32),
716 .platform_data = &uart0_data,
877d7720
AV		 717 },
718 .resource = uart0_resources,
719 .num_resources = ARRAY_SIZE(uart0_resources),
720};
721
c8f385a6 722static inline void configure_usart0_pins(unsigned pins)
877d7720
AV		 723{
724 at91_set_A_periph(AT91_PIN_PA6, 1); /* TXD0 */
725 at91_set_A_periph(AT91_PIN_PA7, 0); /* RXD0 */
c8f385a6
AV		 726
727 if (pins & ATMEL_UART_RTS)
728 at91_set_A_periph(AT91_PIN_PA9, 0); /* RTS0 */
729 if (pins & ATMEL_UART_CTS)
730 at91_set_A_periph(AT91_PIN_PA10, 0); /* CTS0 */
731 if (pins & ATMEL_UART_DSR)
732 at91_set_A_periph(AT91_PIN_PD14, 0); /* DSR0 */
733 if (pins & ATMEL_UART_DTR)
734 at91_set_A_periph(AT91_PIN_PD15, 0); /* DTR0 */
735 if (pins & ATMEL_UART_DCD)
736 at91_set_A_periph(AT91_PIN_PD16, 0); /* DCD0 */
737 if (pins & ATMEL_UART_RI)
738 at91_set_A_periph(AT91_PIN_PD17, 0); /* RI0 */
877d7720
AV		 739}
740
741static struct resource uart1_resources[] = {
742 [0] = {
743 .start = AT91SAM9RL_BASE_US1,
744 .end = AT91SAM9RL_BASE_US1 + SZ_16K - 1,
745 .flags = IORESOURCE_MEM,
746 },
747 [1] = {
748 .start = AT91SAM9RL_ID_US1,
749 .end = AT91SAM9RL_ID_US1,
750 .flags = IORESOURCE_IRQ,
751 },
752};
753
754static struct atmel_uart_data uart1_data = {
755 .use_dma_tx = 1,
756 .use_dma_rx = 1,
757};
758
c6686ff9
AV		 759static u64 uart1_dmamask = DMA_BIT_MASK(32);
760
877d7720
AV		 761static struct platform_device at91sam9rl_uart1_device = {
762 .name = "atmel_usart",
763 .id = 2,
764 .dev = {
c6686ff9
AV		 765 .dma_mask = &uart1_dmamask,
766 .coherent_dma_mask = DMA_BIT_MASK(32),
767 .platform_data = &uart1_data,
877d7720
AV		 768 },
769 .resource = uart1_resources,
770 .num_resources = ARRAY_SIZE(uart1_resources),
771};
772
c8f385a6 773static inline void configure_usart1_pins(unsigned pins)
877d7720
AV		 774{
775 at91_set_A_periph(AT91_PIN_PA11, 1); /* TXD1 */
776 at91_set_A_periph(AT91_PIN_PA12, 0); /* RXD1 */
c8f385a6
AV		 777
778 if (pins & ATMEL_UART_RTS)
779 at91_set_B_periph(AT91_PIN_PA18, 0); /* RTS1 */
780 if (pins & ATMEL_UART_CTS)
781 at91_set_B_periph(AT91_PIN_PA19, 0); /* CTS1 */
877d7720
AV		 782}
783
784static struct resource uart2_resources[] = {
785 [0] = {
786 .start = AT91SAM9RL_BASE_US2,
787 .end = AT91SAM9RL_BASE_US2 + SZ_16K - 1,
788 .flags = IORESOURCE_MEM,
789 },
790 [1] = {
791 .start = AT91SAM9RL_ID_US2,
792 .end = AT91SAM9RL_ID_US2,
793 .flags = IORESOURCE_IRQ,
794 },
795};
796
797static struct atmel_uart_data uart2_data = {
798 .use_dma_tx = 1,
799 .use_dma_rx = 1,
800};
801
c6686ff9
AV		 802static u64 uart2_dmamask = DMA_BIT_MASK(32);
803
877d7720
AV		 804static struct platform_device at91sam9rl_uart2_device = {
805 .name = "atmel_usart",
806 .id = 3,
807 .dev = {
c6686ff9
AV		 808 .dma_mask = &uart2_dmamask,
809 .coherent_dma_mask = DMA_BIT_MASK(32),
810 .platform_data = &uart2_data,
877d7720
AV		 811 },
812 .resource = uart2_resources,
813 .num_resources = ARRAY_SIZE(uart2_resources),
814};
815
c8f385a6 816static inline void configure_usart2_pins(unsigned pins)
877d7720
AV		 817{
818 at91_set_A_periph(AT91_PIN_PA13, 1); /* TXD2 */
819 at91_set_A_periph(AT91_PIN_PA14, 0); /* RXD2 */
c8f385a6
AV		 820
821 if (pins & ATMEL_UART_RTS)
822 at91_set_A_periph(AT91_PIN_PA29, 0); /* RTS2 */
823 if (pins & ATMEL_UART_CTS)
824 at91_set_A_periph(AT91_PIN_PA30, 0); /* CTS2 */
877d7720
AV		 825}
826
827static struct resource uart3_resources[] = {
828 [0] = {
829 .start = AT91SAM9RL_BASE_US3,
830 .end = AT91SAM9RL_BASE_US3 + SZ_16K - 1,
831 .flags = IORESOURCE_MEM,
832 },
833 [1] = {
834 .start = AT91SAM9RL_ID_US3,
835 .end = AT91SAM9RL_ID_US3,
836 .flags = IORESOURCE_IRQ,
837 },
838};
839
840static struct atmel_uart_data uart3_data = {
841 .use_dma_tx = 1,
842 .use_dma_rx = 1,
843};
844
c6686ff9
AV		 845static u64 uart3_dmamask = DMA_BIT_MASK(32);
846
877d7720
AV		 847static struct platform_device at91sam9rl_uart3_device = {
848 .name = "atmel_usart",
849 .id = 4,
850 .dev = {
c6686ff9
AV		 851 .dma_mask = &uart3_dmamask,
852 .coherent_dma_mask = DMA_BIT_MASK(32),
853 .platform_data = &uart3_data,
877d7720
AV		 854 },
855 .resource = uart3_resources,
856 .num_resources = ARRAY_SIZE(uart3_resources),
857};
858
c8f385a6 859static inline void configure_usart3_pins(unsigned pins)
877d7720
AV		 860{
861 at91_set_A_periph(AT91_PIN_PB0, 1); /* TXD3 */
862 at91_set_A_periph(AT91_PIN_PB1, 0); /* RXD3 */
c8f385a6
AV		 863
864 if (pins & ATMEL_UART_RTS)
865 at91_set_B_periph(AT91_PIN_PD4, 0); /* RTS3 */
866 if (pins & ATMEL_UART_CTS)
867 at91_set_B_periph(AT91_PIN_PD3, 0); /* CTS3 */
877d7720
AV		 868}
869
11aadac4 870static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
877d7720
AV		 871struct platform_device *atmel_default_console_device; /* the serial console device */
872
c8f385a6
AV		 873void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
874{
875 struct platform_device *pdev;
876
877 switch (id) {
878 case 0: /* DBGU */
879 pdev = &at91sam9rl_dbgu_device;
880 configure_dbgu_pins();
881 at91_clock_associate("mck", &pdev->dev, "usart");
882 break;
883 case AT91SAM9RL_ID_US0:
884 pdev = &at91sam9rl_uart0_device;
885 configure_usart0_pins(pins);
886 at91_clock_associate("usart0_clk", &pdev->dev, "usart");
887 break;
888 case AT91SAM9RL_ID_US1:
889 pdev = &at91sam9rl_uart1_device;
890 configure_usart1_pins(pins);
891 at91_clock_associate("usart1_clk", &pdev->dev, "usart");
892 break;
893 case AT91SAM9RL_ID_US2:
894 pdev = &at91sam9rl_uart2_device;
895 configure_usart2_pins(pins);
896 at91_clock_associate("usart2_clk", &pdev->dev, "usart");
897 break;
898 case AT91SAM9RL_ID_US3:
899 pdev = &at91sam9rl_uart3_device;
900 configure_usart3_pins(pins);
901 at91_clock_associate("usart3_clk", &pdev->dev, "usart");
902 break;
903 default:
904 return;
905 }
906 pdev->id = portnr; /* update to mapped ID */
907
908 if (portnr < ATMEL_MAX_UART)
909 at91_uarts[portnr] = pdev;
910}
911
912void __init at91_set_serial_console(unsigned portnr)
913{
914 if (portnr < ATMEL_MAX_UART)
915 atmel_default_console_device = at91_uarts[portnr];
c8f385a6
AV		 916}
917
877d7720
AV		 918void __init at91_add_device_serial(void)
919{
920 int i;
921
922 for (i = 0; i < ATMEL_MAX_UART; i++) {
923 if (at91_uarts[i])
924 platform_device_register(at91_uarts[i]);
925 }
11aadac4
AV		 926
927 if (!atmel_default_console_device)
928 printk(KERN_INFO "AT91: No default serial console defined.\n");
877d7720
AV		 929}
930#else
c8f385a6
AV		 931void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
932void __init at91_set_serial_console(unsigned portnr) {}
877d7720
AV		 933void __init at91_add_device_serial(void) {}
934#endif
935
936
937/* -------------------------------------------------------------------- */
938
939/*
940 * These devices are always present and don't need any board-specific
941 * setup.
942 */
943static int __init at91_add_standard_devices(void)
944{
884f5a6a
AV		 945 at91_add_device_rtc();
946 at91_add_device_rtt();
947 at91_add_device_watchdog();
e5f40bfa 948 at91_add_device_tc();
877d7720
AV		 949 return 0;
950}
951
952arch_initcall(at91_add_standard_devices);
Linux kernel - Deliverables
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