[deliverable/linux.git] / arch / arm / mach-at91 / at91sam9x5.c

/*
 *  Chip-specific setup code for the AT91SAM9x5 family
 *
 *  Copyright (C) 2010-2012 Atmel Corporation.
 *
 * Licensed under GPLv2 or later.
 */

#include <linux/module.h>
#include <linux/dma-mapping.h>

#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <mach/at91sam9x5.h>
#include <mach/at91_pmc.h>
#include <mach/cpu.h>

#include "board.h"
#include "soc.h"
#include "generic.h"
#include "clock.h"
#include "sam9_smc.h"

/* --------------------------------------------------------------------
 *  Clocks
 * -------------------------------------------------------------------- */

/*
 * The peripheral clocks.
 */
static struct clk pioAB_clk = {
	.name		= "pioAB_clk",
	.pmc_mask	= 1 << AT91SAM9X5_ID_PIOAB,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk pioCD_clk = {
	.name		= "pioCD_clk",
	.pmc_mask	= 1 << AT91SAM9X5_ID_PIOCD,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk smd_clk = {
	.name		= "smd_clk",
	.pmc_mask	= 1 << AT91SAM9X5_ID_SMD,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart0_clk = {
	.name		= "usart0_clk",
	.pmc_mask	= 1 << AT91SAM9X5_ID_USART0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart1_clk = {
	.name		= "usart1_clk",
	.pmc_mask	= 1 << AT91SAM9X5_ID_USART1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk usart2_clk = {
	.name		= "usart2_clk",
	.pmc_mask	= 1 << AT91SAM9X5_ID_USART2,
	.type		= CLK_TYPE_PERIPHERAL,
};
/* USART3 clock - Only for sam9g25/sam9x25 */
static struct clk usart3_clk = {
	.name		= "usart3_clk",
	.pmc_mask	= 1 << AT91SAM9X5_ID_USART3,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk twi0_clk = {
	.name		= "twi0_clk",
	.pmc_mask	= 1 << AT91SAM9X5_ID_TWI0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk twi1_clk = {
	.name		= "twi1_clk",
	.pmc_mask	= 1 << AT91SAM9X5_ID_TWI1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk twi2_clk = {
	.name		= "twi2_clk",
	.pmc_mask	= 1 << AT91SAM9X5_ID_TWI2,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk mmc0_clk = {
	.name		= "mci0_clk",
	.pmc_mask	= 1 << AT91SAM9X5_ID_MCI0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk spi0_clk = {
	.name		= "spi0_clk",
	.pmc_mask	= 1 << AT91SAM9X5_ID_SPI0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk spi1_clk = {
	.name		= "spi1_clk",
	.pmc_mask	= 1 << AT91SAM9X5_ID_SPI1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk uart0_clk = {
	.name		= "uart0_clk",
	.pmc_mask	= 1 << AT91SAM9X5_ID_UART0,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk uart1_clk = {
	.name		= "uart1_clk",
	.pmc_mask	= 1 << AT91SAM9X5_ID_UART1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk tcb0_clk = {
	.name		= "tcb0_clk",
	.pmc_mask	= 1 << AT91SAM9X5_ID_TCB,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk pwm_clk = {
	.name		= "pwm_clk",
	.pmc_mask	= 1 << AT91SAM9X5_ID_PWM,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk adc_clk = {
	.name		= "adc_clk",
	.pmc_mask	= 1 << AT91SAM9X5_ID_ADC,
	.type	= CLK_TYPE_PERIPHERAL,
};
static struct clk adc_op_clk = {
	.name		= "adc_op_clk",
	.type		= CLK_TYPE_PERIPHERAL,
	.rate_hz	= 5000000,
};
static struct clk dma0_clk = {
	.name		= "dma0_clk",
	.pmc_mask	= 1 << AT91SAM9X5_ID_DMA0,
	.type	= CLK_TYPE_PERIPHERAL,
};
static struct clk dma1_clk = {
	.name		= "dma1_clk",
	.pmc_mask	= 1 << AT91SAM9X5_ID_DMA1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk uhphs_clk = {
	.name		= "uhphs",
	.pmc_mask	= 1 << AT91SAM9X5_ID_UHPHS,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk udphs_clk = {
	.name		= "udphs_clk",
	.pmc_mask	= 1 << AT91SAM9X5_ID_UDPHS,
	.type		= CLK_TYPE_PERIPHERAL,
};
/* emac0 clock - Only for sam9g25/sam9x25/sam9g35/sam9x35 */
static struct clk macb0_clk = {
	.name		= "pclk",
	.pmc_mask	= 1 << AT91SAM9X5_ID_EMAC0,
	.type		= CLK_TYPE_PERIPHERAL,
};
/* lcd clock - Only for sam9g15/sam9g35/sam9x35 */
static struct clk lcdc_clk = {
	.name		= "lcdc_clk",
	.pmc_mask	= 1 << AT91SAM9X5_ID_LCDC,
	.type		= CLK_TYPE_PERIPHERAL,
};
/* isi clock - Only for sam9g25 */
static struct clk isi_clk = {
	.name		= "isi_clk",
	.pmc_mask	= 1 << AT91SAM9X5_ID_ISI,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk mmc1_clk = {
	.name		= "mci1_clk",
	.pmc_mask	= 1 << AT91SAM9X5_ID_MCI1,
	.type		= CLK_TYPE_PERIPHERAL,
};
/* emac1 clock - Only for sam9x25 */
static struct clk macb1_clk = {
	.name		= "pclk",
	.pmc_mask	= 1 << AT91SAM9X5_ID_EMAC1,
	.type		= CLK_TYPE_PERIPHERAL,
};
static struct clk ssc_clk = {
	.name		= "ssc_clk",
	.pmc_mask	= 1 << AT91SAM9X5_ID_SSC,
	.type		= CLK_TYPE_PERIPHERAL,
};
/* can0 clock - Only for sam9x35 */
static struct clk can0_clk = {
	.name		= "can0_clk",
	.pmc_mask	= 1 << AT91SAM9X5_ID_CAN0,
	.type		= CLK_TYPE_PERIPHERAL,
};
/* can1 clock - Only for sam9x35 */
static struct clk can1_clk = {
	.name		= "can1_clk",
	.pmc_mask	= 1 << AT91SAM9X5_ID_CAN1,
	.type		= CLK_TYPE_PERIPHERAL,
};

static struct clk *periph_clocks[] __initdata = {
	&pioAB_clk,
	&pioCD_clk,
	&smd_clk,
	&usart0_clk,
	&usart1_clk,
	&usart2_clk,
	&twi0_clk,
	&twi1_clk,
	&twi2_clk,
	&mmc0_clk,
	&spi0_clk,
	&spi1_clk,
	&uart0_clk,
	&uart1_clk,
	&tcb0_clk,
	&pwm_clk,
	&adc_clk,
	&adc_op_clk,
	&dma0_clk,
	&dma1_clk,
	&uhphs_clk,
	&udphs_clk,
	&mmc1_clk,
	&ssc_clk,
	// irq0
};

static struct clk_lookup periph_clocks_lookups[] = {
	/* lookup table for DT entries */
	CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
	CLKDEV_CON_DEV_ID("usart", "f801c000.serial", &usart0_clk),
	CLKDEV_CON_DEV_ID("usart", "f8020000.serial", &usart1_clk),
	CLKDEV_CON_DEV_ID("usart", "f8024000.serial", &usart2_clk),
	CLKDEV_CON_DEV_ID("usart", "f8028000.serial", &usart3_clk),
	CLKDEV_CON_DEV_ID("usart", "f8040000.serial", &uart0_clk),
	CLKDEV_CON_DEV_ID("usart", "f8044000.serial", &uart1_clk),
	CLKDEV_CON_DEV_ID("t0_clk", "f8008000.timer", &tcb0_clk),
	CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb0_clk),
	CLKDEV_CON_DEV_ID("mci_clk", "f0008000.mmc", &mmc0_clk),
	CLKDEV_CON_DEV_ID("mci_clk", "f000c000.mmc", &mmc1_clk),
	CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma0_clk),
	CLKDEV_CON_DEV_ID("dma_clk", "ffffee00.dma-controller", &dma1_clk),
	CLKDEV_CON_DEV_ID("pclk", "f0010000.ssc", &ssc_clk),
	CLKDEV_CON_DEV_ID(NULL, "f8010000.i2c", &twi0_clk),
	CLKDEV_CON_DEV_ID(NULL, "f8014000.i2c", &twi1_clk),
	CLKDEV_CON_DEV_ID(NULL, "f8018000.i2c", &twi2_clk),
	CLKDEV_CON_DEV_ID("spi_clk", "f0000000.spi", &spi0_clk),
	CLKDEV_CON_DEV_ID("spi_clk", "f0004000.spi", &spi1_clk),
	CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioAB_clk),
	CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioAB_clk),
	CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioCD_clk),
	CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioCD_clk),
	/* additional fake clock for macb_hclk */
	CLKDEV_CON_DEV_ID("hclk", "f802c000.ethernet", &macb0_clk),
	CLKDEV_CON_DEV_ID("hclk", "f8030000.ethernet", &macb1_clk),
	CLKDEV_CON_DEV_ID("hclk", "600000.ohci", &uhphs_clk),
	CLKDEV_CON_DEV_ID("ohci_clk", "600000.ohci", &uhphs_clk),
	CLKDEV_CON_DEV_ID("ehci_clk", "700000.ehci", &uhphs_clk),
	CLKDEV_CON_DEV_ID("hclk", "500000.gadget", &utmi_clk),
	CLKDEV_CON_DEV_ID("pclk", "500000.gadget", &udphs_clk),
};

/*
 * The two programmable clocks.
 * You must configure pin multiplexing to bring these signals out.
 */
static struct clk pck0 = {
	.name		= "pck0",
	.pmc_mask	= AT91_PMC_PCK0,
	.type		= CLK_TYPE_PROGRAMMABLE,
	.id		= 0,
};
static struct clk pck1 = {
	.name		= "pck1",
	.pmc_mask	= AT91_PMC_PCK1,
	.type		= CLK_TYPE_PROGRAMMABLE,
	.id		= 1,
};

static void __init at91sam9x5_register_clocks(void)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
		clk_register(periph_clocks[i]);

	clkdev_add_table(periph_clocks_lookups,
			 ARRAY_SIZE(periph_clocks_lookups));

	if (cpu_is_at91sam9g25()
	|| cpu_is_at91sam9x25())
		clk_register(&usart3_clk);

	if (cpu_is_at91sam9g25()
	|| cpu_is_at91sam9x25()
	|| cpu_is_at91sam9g35()
	|| cpu_is_at91sam9x35())
		clk_register(&macb0_clk);

	if (cpu_is_at91sam9g15()
	|| cpu_is_at91sam9g35()
	|| cpu_is_at91sam9x35())
		clk_register(&lcdc_clk);

	if (cpu_is_at91sam9g25())
		clk_register(&isi_clk);

	if (cpu_is_at91sam9x25())
		clk_register(&macb1_clk);

	if (cpu_is_at91sam9x25()
	|| cpu_is_at91sam9x35()) {
		clk_register(&can0_clk);
		clk_register(&can1_clk);
	}

	clk_register(&pck0);
	clk_register(&pck1);
}

/* --------------------------------------------------------------------
 *  AT91SAM9x5 processor initialization
 * -------------------------------------------------------------------- */

static void __init at91sam9x5_map_io(void)
{
	at91_init_sram(0, AT91SAM9X5_SRAM_BASE, AT91SAM9X5_SRAM_SIZE);
}

/* --------------------------------------------------------------------
 *  Interrupt initialization
 * -------------------------------------------------------------------- */

AT91_SOC_START(at91sam9x5)
	.map_io = at91sam9x5_map_io,
	.register_clocks = at91sam9x5_register_clocks,
AT91_SOC_END
Commit	Line	Data
2b9ccf3c DL	1	/*
	2	* Chip-specific setup code for the AT91SAM9x5 family
	3	*
	4	* Copyright (C) 2010-2012 Atmel Corporation.
	5	*
	6	* Licensed under GPLv2 or later.
	7	*/
	8
	9	#include <linux/module.h>
	10	#include <linux/dma-mapping.h>
	11
	12	#include <asm/irq.h>
	13	#include <asm/mach/arch.h>
	14	#include <asm/mach/map.h>
	15	#include <mach/at91sam9x5.h>
	16	#include <mach/at91_pmc.h>
	17	#include <mach/cpu.h>
2b9ccf3c	18
43d2f532	19	#include "board.h"
2b9ccf3c DL	20	#include "soc.h"
	21	#include "generic.h"
	22	#include "clock.h"
	23	#include "sam9_smc.h"
	24
	25	/* --------------------------------------------------------------------
	26	* Clocks
	27	* -------------------------------------------------------------------- */
	28
	29	/*
	30	* The peripheral clocks.
	31	*/
	32	static struct clk pioAB_clk = {
	33	.name = "pioAB_clk",
	34	.pmc_mask = 1 << AT91SAM9X5_ID_PIOAB,
	35	.type = CLK_TYPE_PERIPHERAL,
	36	};
	37	static struct clk pioCD_clk = {
	38	.name = "pioCD_clk",
	39	.pmc_mask = 1 << AT91SAM9X5_ID_PIOCD,
	40	.type = CLK_TYPE_PERIPHERAL,
	41	};
	42	static struct clk smd_clk = {
	43	.name = "smd_clk",
	44	.pmc_mask = 1 << AT91SAM9X5_ID_SMD,
	45	.type = CLK_TYPE_PERIPHERAL,
	46	};
	47	static struct clk usart0_clk = {
	48	.name = "usart0_clk",
	49	.pmc_mask = 1 << AT91SAM9X5_ID_USART0,
	50	.type = CLK_TYPE_PERIPHERAL,
	51	};
	52	static struct clk usart1_clk = {
	53	.name = "usart1_clk",
	54	.pmc_mask = 1 << AT91SAM9X5_ID_USART1,
	55	.type = CLK_TYPE_PERIPHERAL,
	56	};
	57	static struct clk usart2_clk = {
	58	.name = "usart2_clk",
	59	.pmc_mask = 1 << AT91SAM9X5_ID_USART2,
	60	.type = CLK_TYPE_PERIPHERAL,
	61	};
	62	/* USART3 clock - Only for sam9g25/sam9x25 */
	63	static struct clk usart3_clk = {
	64	.name = "usart3_clk",
	65	.pmc_mask = 1 << AT91SAM9X5_ID_USART3,
	66	.type = CLK_TYPE_PERIPHERAL,
	67	};
	68	static struct clk twi0_clk = {
	69	.name = "twi0_clk",
	70	.pmc_mask = 1 << AT91SAM9X5_ID_TWI0,
	71	.type = CLK_TYPE_PERIPHERAL,
	72	};
	73	static struct clk twi1_clk = {
	74	.name = "twi1_clk",
	75	.pmc_mask = 1 << AT91SAM9X5_ID_TWI1,
	76	.type = CLK_TYPE_PERIPHERAL,
	77	};
	78	static struct clk twi2_clk = {
	79	.name = "twi2_clk",
	80	.pmc_mask = 1 << AT91SAM9X5_ID_TWI2,
	81	.type = CLK_TYPE_PERIPHERAL,
	82	};
	83	static struct clk mmc0_clk = {
84	.name = "mci0_clk",
85	.pmc_mask = 1 << AT91SAM9X5_ID_MCI0,
86	.type = CLK_TYPE_PERIPHERAL,
87	};
88	static struct clk spi0_clk = {
89	.name = "spi0_clk",
90	.pmc_mask = 1 << AT91SAM9X5_ID_SPI0,
91	.type = CLK_TYPE_PERIPHERAL,
92	};
93	static struct clk spi1_clk = {
94	.name = "spi1_clk",
95	.pmc_mask = 1 << AT91SAM9X5_ID_SPI1,
96	.type = CLK_TYPE_PERIPHERAL,
97	};
98	static struct clk uart0_clk = {
99	.name = "uart0_clk",
100	.pmc_mask = 1 << AT91SAM9X5_ID_UART0,
101	.type = CLK_TYPE_PERIPHERAL,
102	};
103	static struct clk uart1_clk = {
104	.name = "uart1_clk",
105	.pmc_mask = 1 << AT91SAM9X5_ID_UART1,
106	.type = CLK_TYPE_PERIPHERAL,
107	};
108	static struct clk tcb0_clk = {
109	.name = "tcb0_clk",
110	.pmc_mask = 1 << AT91SAM9X5_ID_TCB,
111	.type = CLK_TYPE_PERIPHERAL,
112	};
113	static struct clk pwm_clk = {
114	.name = "pwm_clk",
115	.pmc_mask = 1 << AT91SAM9X5_ID_PWM,
116	.type = CLK_TYPE_PERIPHERAL,
117	};
118	static struct clk adc_clk = {
119	.name = "adc_clk",
120	.pmc_mask = 1 << AT91SAM9X5_ID_ADC,
121	.type = CLK_TYPE_PERIPHERAL,
122	};
5d449e4b MR	123	static struct clk adc_op_clk = {
	124	.name = "adc_op_clk",
	125	.type = CLK_TYPE_PERIPHERAL,
	126	.rate_hz = 5000000,
	127	};
2b9ccf3c DL	128	static struct clk dma0_clk = {
	129	.name = "dma0_clk",
	130	.pmc_mask = 1 << AT91SAM9X5_ID_DMA0,
	131	.type = CLK_TYPE_PERIPHERAL,
	132	};
	133	static struct clk dma1_clk = {
	134	.name = "dma1_clk",
	135	.pmc_mask = 1 << AT91SAM9X5_ID_DMA1,
	136	.type = CLK_TYPE_PERIPHERAL,
	137	};
	138	static struct clk uhphs_clk = {
6a062459	139	.name = "uhphs",
2b9ccf3c DL	140	.pmc_mask = 1 << AT91SAM9X5_ID_UHPHS,
	141	.type = CLK_TYPE_PERIPHERAL,
	142	};
	143	static struct clk udphs_clk = {
	144	.name = "udphs_clk",
	145	.pmc_mask = 1 << AT91SAM9X5_ID_UDPHS,
	146	.type = CLK_TYPE_PERIPHERAL,
	147	};
	148	/* emac0 clock - Only for sam9g25/sam9x25/sam9g35/sam9x35 */
	149	static struct clk macb0_clk = {
	150	.name = "pclk",
	151	.pmc_mask = 1 << AT91SAM9X5_ID_EMAC0,
	152	.type = CLK_TYPE_PERIPHERAL,
	153	};
	154	/* lcd clock - Only for sam9g15/sam9g35/sam9x35 */
	155	static struct clk lcdc_clk = {
	156	.name = "lcdc_clk",
	157	.pmc_mask = 1 << AT91SAM9X5_ID_LCDC,
	158	.type = CLK_TYPE_PERIPHERAL,
	159	};
	160	/* isi clock - Only for sam9g25 */
	161	static struct clk isi_clk = {
	162	.name = "isi_clk",
	163	.pmc_mask = 1 << AT91SAM9X5_ID_ISI,
	164	.type = CLK_TYPE_PERIPHERAL,
	165	};
	166	static struct clk mmc1_clk = {
	167	.name = "mci1_clk",
	168	.pmc_mask = 1 << AT91SAM9X5_ID_MCI1,
	169	.type = CLK_TYPE_PERIPHERAL,
	170	};
	171	/* emac1 clock - Only for sam9x25 */
	172	static struct clk macb1_clk = {
	173	.name = "pclk",
	174	.pmc_mask = 1 << AT91SAM9X5_ID_EMAC1,
	175	.type = CLK_TYPE_PERIPHERAL,
	176	};
	177	static struct clk ssc_clk = {
	178	.name = "ssc_clk",
	179	.pmc_mask = 1 << AT91SAM9X5_ID_SSC,
	180	.type = CLK_TYPE_PERIPHERAL,
	181	};
	182	/* can0 clock - Only for sam9x35 */
	183	static struct clk can0_clk = {
	184	.name = "can0_clk",
	185	.pmc_mask = 1 << AT91SAM9X5_ID_CAN0,
	186	.type = CLK_TYPE_PERIPHERAL,
	187	};
	188	/* can1 clock - Only for sam9x35 */
	189	static struct clk can1_clk = {
	190	.name = "can1_clk",
	191	.pmc_mask = 1 << AT91SAM9X5_ID_CAN1,
	192	.type = CLK_TYPE_PERIPHERAL,
	193	};
	194
	195	static struct clk *periph_clocks[] __initdata = {
	196	&pioAB_clk,
	197	&pioCD_clk,
	198	&smd_clk,
	199	&usart0_clk,
	200	&usart1_clk,
	201	&usart2_clk,
	202	&twi0_clk,
	203	&twi1_clk,
204	&twi2_clk,
205	&mmc0_clk,
206	&spi0_clk,
207	&spi1_clk,
208	&uart0_clk,
209	&uart1_clk,
210	&tcb0_clk,
211	&pwm_clk,
212	&adc_clk,
5d449e4b	213	&adc_op_clk,
2b9ccf3c DL	214	&dma0_clk,
	215	&dma1_clk,
	216	&uhphs_clk,
	217	&udphs_clk,
	218	&mmc1_clk,
	219	&ssc_clk,
	220	// irq0
	221	};
	222
	223	static struct clk_lookup periph_clocks_lookups[] = {
	224	/* lookup table for DT entries */
	225	CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
	226	CLKDEV_CON_DEV_ID("usart", "f801c000.serial", &usart0_clk),
	227	CLKDEV_CON_DEV_ID("usart", "f8020000.serial", &usart1_clk),
	228	CLKDEV_CON_DEV_ID("usart", "f8024000.serial", &usart2_clk),
	229	CLKDEV_CON_DEV_ID("usart", "f8028000.serial", &usart3_clk),
b524f389 BB	230	CLKDEV_CON_DEV_ID("usart", "f8040000.serial", &uart0_clk),
b524f389 BB	231	CLKDEV_CON_DEV_ID("usart", "f8044000.serial", &uart1_clk),
2b9ccf3c DL	232	CLKDEV_CON_DEV_ID("t0_clk", "f8008000.timer", &tcb0_clk),
2b9ccf3c DL	233	CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb0_clk),
23e3b24f LD	234	CLKDEV_CON_DEV_ID("mci_clk", "f0008000.mmc", &mmc0_clk),
23e3b24f LD	235	CLKDEV_CON_DEV_ID("mci_clk", "f000c000.mmc", &mmc1_clk),
7bd95239 NF	236	CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma0_clk),
7bd95239 NF	237	CLKDEV_CON_DEV_ID("dma_clk", "ffffee00.dma-controller", &dma1_clk),
099343c6	238	CLKDEV_CON_DEV_ID("pclk", "f0010000.ssc", &ssc_clk),
f7d19b90 LD	239	CLKDEV_CON_DEV_ID(NULL, "f8010000.i2c", &twi0_clk),
	240	CLKDEV_CON_DEV_ID(NULL, "f8014000.i2c", &twi1_clk),
	241	CLKDEV_CON_DEV_ID(NULL, "f8018000.i2c", &twi2_clk),
f0db66a5 RG	242	CLKDEV_CON_DEV_ID("spi_clk", "f0000000.spi", &spi0_clk),
f0db66a5 RG	243	CLKDEV_CON_DEV_ID("spi_clk", "f0004000.spi", &spi1_clk),
5314ec8e JCPV	244	CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioAB_clk),
	245	CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioAB_clk),
	246	CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioCD_clk),
	247	CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioCD_clk),
2b9ccf3c DL	248	/* additional fake clock for macb_hclk */
	249	CLKDEV_CON_DEV_ID("hclk", "f802c000.ethernet", &macb0_clk),
	250	CLKDEV_CON_DEV_ID("hclk", "f8030000.ethernet", &macb1_clk),
6a062459 JCPV	251	CLKDEV_CON_DEV_ID("hclk", "600000.ohci", &uhphs_clk),
6a062459 JCPV	252	CLKDEV_CON_DEV_ID("ohci_clk", "600000.ohci", &uhphs_clk),
62c5553a	253	CLKDEV_CON_DEV_ID("ehci_clk", "700000.ehci", &uhphs_clk),
aecca65c JCPV	254	CLKDEV_CON_DEV_ID("hclk", "500000.gadget", &utmi_clk),
aecca65c JCPV	255	CLKDEV_CON_DEV_ID("pclk", "500000.gadget", &udphs_clk),
2b9ccf3c DL	256	};
	257
	258	/*
	259	* The two programmable clocks.
	260	* You must configure pin multiplexing to bring these signals out.
	261	*/
	262	static struct clk pck0 = {
	263	.name = "pck0",
	264	.pmc_mask = AT91_PMC_PCK0,
	265	.type = CLK_TYPE_PROGRAMMABLE,
	266	.id = 0,
	267	};
	268	static struct clk pck1 = {
	269	.name = "pck1",
	270	.pmc_mask = AT91_PMC_PCK1,
	271	.type = CLK_TYPE_PROGRAMMABLE,
	272	.id = 1,
	273	};
	274
	275	static void __init at91sam9x5_register_clocks(void)
	276	{
	277	int i;
	278
	279	for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
	280	clk_register(periph_clocks[i]);
	281
	282	clkdev_add_table(periph_clocks_lookups,
	283	ARRAY_SIZE(periph_clocks_lookups));
	284
	285	if (cpu_is_at91sam9g25()
	286	\|\| cpu_is_at91sam9x25())
	287	clk_register(&usart3_clk);
	288
	289	if (cpu_is_at91sam9g25()
	290	\|\| cpu_is_at91sam9x25()
	291	\|\| cpu_is_at91sam9g35()
	292	\|\| cpu_is_at91sam9x35())
	293	clk_register(&macb0_clk);
	294
	295	if (cpu_is_at91sam9g15()
	296	\|\| cpu_is_at91sam9g35()
	297	\|\| cpu_is_at91sam9x35())
	298	clk_register(&lcdc_clk);
	299
	300	if (cpu_is_at91sam9g25())
	301	clk_register(&isi_clk);
	302
	303	if (cpu_is_at91sam9x25())
	304	clk_register(&macb1_clk);
	305
	306	if (cpu_is_at91sam9x25()
	307	\|\| cpu_is_at91sam9x35()) {
	308	clk_register(&can0_clk);
	309	clk_register(&can1_clk);
	310	}
	311
	312	clk_register(&pck0);
	313	clk_register(&pck1);
	314	}
	315
	316	/* --------------------------------------------------------------------
	317	* AT91SAM9x5 processor initialization
	318	* -------------------------------------------------------------------- */
	319
320	static void __init at91sam9x5_map_io(void)
321	{
322	at91_init_sram(0, AT91SAM9X5_SRAM_BASE, AT91SAM9X5_SRAM_SIZE);
323	}
324
2b9ccf3c DL	325	/* --------------------------------------------------------------------
	326	* Interrupt initialization
	327	* -------------------------------------------------------------------- */
2b9ccf3c	328
84ddb087	329	AT91_SOC_START(at91sam9x5)
2b9ccf3c	330	.map_io = at91sam9x5_map_io,
2b9ccf3c	331	.register_clocks = at91sam9x5_register_clocks,
8d39e0fd	332	AT91_SOC_END