projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 49fe2ba3 NF |
1 | /* |
| 2 | * Setup code for AT91SAM Evaluation Kits with Device Tree support | |
| 3 | * | |
| 4 | * Covers: * AT91SAM9G45-EKES board | |
| 5 | * * AT91SAM9M10-EKES board | |
| 6 | * * AT91SAM9M10G45-EK board | |
| 7 | * | |
| 8 | * Copyright (C) 2011 Atmel, | |
| 9 | * 2011 Nicolas Ferre <nicolas.ferre@atmel.com> | |
| 10 | * | |
| 11 | * Licensed under GPLv2 or later. | |
| 12 | */ | |
| 13 | ||
| 14 | #include <linux/types.h> | |
| 15 | #include <linux/init.h> | |
| 16 | #include <linux/module.h> | |
| 17 | #include <linux/gpio.h> | |
| 18 | #include <linux/irqdomain.h> | |
| 19 | #include <linux/of_irq.h> | |
| 20 | #include <linux/of_platform.h> | |
| 21 | ||
| 22 | #include <mach/hardware.h> | |
| 23 | #include <mach/board.h> | |
| 24 | #include <mach/system_rev.h> | |
| 25 | #include <mach/at91sam9_smc.h> | |
| 26 | ||
| 27 | #include <asm/setup.h> | |
| 28 | #include <asm/irq.h> | |
| 29 | #include <asm/mach/arch.h> | |
| 30 | #include <asm/mach/map.h> | |
| 31 | #include <asm/mach/irq.h> | |
| 32 | ||
| 33 | #include "sam9_smc.h" | |
| 34 | #include "generic.h" | |
| 35 | ||
| 36 | ||
| 37 | static void __init ek_init_early(void) | |
| 38 | { | |
| 39 | /* Initialize processor: 12.000 MHz crystal */ | |
| 40 | at91_initialize(12000000); | |
| 49fe2ba3 NF |
41 | } |
| 42 | ||
| 43 | /* det_pin is not connected */ | |
| 44 | static struct atmel_nand_data __initdata ek_nand_data = { | |
| 45 | .ale = 21, | |
| 46 | .cle = 22, | |
| 63b4c296 | 47 | .det_pin = -EINVAL, |
| 49fe2ba3 NF |
48 | .rdy_pin = AT91_PIN_PC8, |
| 49 | .enable_pin = AT91_PIN_PC14, | |
| 50 | }; | |
| 51 | ||
| 52 | static struct sam9_smc_config __initdata ek_nand_smc_config = { | |
| 53 | .ncs_read_setup = 0, | |
| 54 | .nrd_setup = 2, | |
| 55 | .ncs_write_setup = 0, | |
| 56 | .nwe_setup = 2, | |
| 57 | ||
| 58 | .ncs_read_pulse = 4, | |
| 59 | .nrd_pulse = 4, | |
| 60 | .ncs_write_pulse = 4, | |
| 61 | .nwe_pulse = 4, | |
| 62 | ||
| 63 | .read_cycle = 7, | |
| 64 | .write_cycle = 7, | |
| 65 | ||
| 66 | .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE, | |
| 67 | .tdf_cycles = 3, | |
| 68 | }; | |
| 69 | ||
| 70 | static void __init ek_add_device_nand(void) | |
| 71 | { | |
| 72 | ek_nand_data.bus_width_16 = board_have_nand_16bit(); | |
| 73 | /* setup bus-width (8 or 16) */ | |
| 74 | if (ek_nand_data.bus_width_16) | |
| 75 | ek_nand_smc_config.mode |= AT91_SMC_DBW_16; | |
| 76 | else | |
| 77 | ek_nand_smc_config.mode |= AT91_SMC_DBW_8; | |
| 78 | ||
| 79 | /* configure chip-select 3 (NAND) */ | |
| faee0cc3 | 80 | sam9_smc_configure(0, 3, &ek_nand_smc_config); |
| 49fe2ba3 NF |
81 | |
| 82 | at91_add_device_nand(&ek_nand_data); | |
| 83 | } | |
| 84 | ||
| 85 | static const struct of_device_id aic_of_match[] __initconst = { | |
| 86 | { .compatible = "atmel,at91rm9200-aic", }, | |
| 87 | {}, | |
| 88 | }; | |
| 89 | ||
| 90 | static void __init at91_dt_init_irq(void) | |
| 91 | { | |
| 92 | irq_domain_generate_simple(aic_of_match, 0xfffff000, 0); | |
| 93 | at91_init_irq_default(); | |
| 94 | } | |
| 95 | ||
| 96 | static void __init at91_dt_device_init(void) | |
| 97 | { | |
| 98 | of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); | |
| 99 | ||
| 100 | /* NAND */ | |
| 101 | ek_add_device_nand(); | |
| 102 | } | |
| 103 | ||
| 104 | static const char *at91_dt_board_compat[] __initdata = { | |
| 105 | "atmel,at91sam9m10g45ek", | |
| 2b9ccf3c | 106 | "atmel,at91sam9x5ek", |
| fea3158c | 107 | "calao,usb-a9g20", |
| 49fe2ba3 NF |
108 | NULL |
| 109 | }; | |
| 110 | ||
| 111 | DT_MACHINE_START(at91sam_dt, "Atmel AT91SAM (Device Tree)") | |
| 112 | /* Maintainer: Atmel */ | |
| 113 | .timer = &at91sam926x_timer, | |
| 114 | .map_io = at91_map_io, | |
| 115 | .init_early = ek_init_early, | |
| 116 | .init_irq = at91_dt_init_irq, | |
| 117 | .init_machine = at91_dt_device_init, | |
| 118 | .dt_compat = at91_dt_board_compat, | |
| 119 | MACHINE_END |