Commit | Line | Data |
---|---|---|
73a59c1c | 1 | /* |
9d041268 | 2 | * linux/arch/arm/mach-at91/clock.c |
73a59c1c SP |
3 | * |
4 | * Copyright (C) 2005 David Brownell | |
5 | * Copyright (C) 2005 Ivan Kokshaysky | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | */ | |
12 | ||
13 | #include <linux/module.h> | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/fs.h> | |
17 | #include <linux/debugfs.h> | |
18 | #include <linux/seq_file.h> | |
19 | #include <linux/list.h> | |
20 | #include <linux/errno.h> | |
21 | #include <linux/err.h> | |
22 | #include <linux/spinlock.h> | |
23 | #include <linux/delay.h> | |
24 | #include <linux/clk.h> | |
fced80c7 | 25 | #include <linux/io.h> |
eb5e76ff | 26 | #include <linux/of_address.h> |
73a59c1c | 27 | |
a09e64fb RK |
28 | #include <mach/hardware.h> |
29 | #include <mach/at91_pmc.h> | |
30 | #include <mach/cpu.h> | |
73a59c1c | 31 | |
0d781716 JCPV |
32 | #include <asm/proc-fns.h> |
33 | ||
2eeaaa21 | 34 | #include "clock.h" |
5e38efae | 35 | #include "generic.h" |
73a59c1c | 36 | |
b5514952 | 37 | void __iomem *at91_pmc_base; |
f19b797c | 38 | EXPORT_SYMBOL_GPL(at91_pmc_base); |
55c20c0a | 39 | |
73a59c1c SP |
40 | /* |
41 | * There's a lot more which can be done with clocks, including cpufreq | |
42 | * integration, slow clock mode support (for system suspend), letting | |
43 | * PLLB be used at other rates (on boards that don't need USB), etc. | |
44 | */ | |
45 | ||
2eeaaa21 AV |
46 | #define clk_is_primary(x) ((x)->type & CLK_TYPE_PRIMARY) |
47 | #define clk_is_programmable(x) ((x)->type & CLK_TYPE_PROGRAMMABLE) | |
48 | #define clk_is_peripheral(x) ((x)->type & CLK_TYPE_PERIPHERAL) | |
d481f864 | 49 | #define clk_is_sys(x) ((x)->type & CLK_TYPE_SYSTEM) |
2eeaaa21 AV |
50 | |
51 | ||
6d0485a9 NF |
52 | /* |
53 | * Chips have some kind of clocks : group them by functionality | |
54 | */ | |
9918ceaf | 55 | #define cpu_has_utmi() ( cpu_is_at91sam9rl() \ |
11128726 | 56 | || cpu_is_at91sam9g45() \ |
8f4b4794 LD |
57 | || cpu_is_at91sam9x5() \ |
58 | || cpu_is_sama5d3()) | |
59 | ||
60 | #define cpu_has_1056M_plla() (cpu_is_sama5d3()) | |
6d0485a9 | 61 | |
2ef9df7a | 62 | #define cpu_has_800M_plla() ( cpu_is_at91sam9g20() \ |
11128726 | 63 | || cpu_is_at91sam9g45() \ |
74db4fb9 HX |
64 | || cpu_is_at91sam9x5() \ |
65 | || cpu_is_at91sam9n12()) | |
6d0485a9 | 66 | |
eab41708 | 67 | #define cpu_has_300M_plla() (cpu_is_at91sam9g10()) |
6d0485a9 | 68 | |
2ed1f589 NF |
69 | #define cpu_has_240M_plla() (cpu_is_at91sam9261() \ |
70 | || cpu_is_at91sam9263() \ | |
71 | || cpu_is_at91sam9rl()) | |
72 | ||
73 | #define cpu_has_210M_plla() (cpu_is_at91sam9260()) | |
74 | ||
2ef9df7a | 75 | #define cpu_has_pllb() (!(cpu_is_at91sam9rl() \ |
11128726 | 76 | || cpu_is_at91sam9g45() \ |
74db4fb9 HX |
77 | || cpu_is_at91sam9x5() \ |
78 | || cpu_is_at91sam9n12())) | |
2ef9df7a | 79 | |
11128726 | 80 | #define cpu_has_upll() (cpu_is_at91sam9g45() \ |
8f4b4794 LD |
81 | || cpu_is_at91sam9x5() \ |
82 | || cpu_is_sama5d3()) | |
6d0485a9 NF |
83 | |
84 | /* USB host HS & FS */ | |
85 | #define cpu_has_uhp() (!cpu_is_at91sam9rl()) | |
86 | ||
87 | /* USB device FS only */ | |
2ef9df7a | 88 | #define cpu_has_udpfs() (!(cpu_is_at91sam9rl() \ |
11128726 | 89 | || cpu_is_at91sam9g45() \ |
8f4b4794 LD |
90 | || cpu_is_at91sam9x5() \ |
91 | || cpu_is_sama5d3())) | |
11128726 NF |
92 | |
93 | #define cpu_has_plladiv2() (cpu_is_at91sam9g45() \ | |
74db4fb9 | 94 | || cpu_is_at91sam9x5() \ |
8f4b4794 LD |
95 | || cpu_is_at91sam9n12() \ |
96 | || cpu_is_sama5d3()) | |
11128726 NF |
97 | |
98 | #define cpu_has_mdiv3() (cpu_is_at91sam9g45() \ | |
74db4fb9 | 99 | || cpu_is_at91sam9x5() \ |
8f4b4794 LD |
100 | || cpu_is_at91sam9n12() \ |
101 | || cpu_is_sama5d3()) | |
11128726 | 102 | |
74db4fb9 | 103 | #define cpu_has_alt_prescaler() (cpu_is_at91sam9x5() \ |
8f4b4794 LD |
104 | || cpu_is_at91sam9n12() \ |
105 | || cpu_is_sama5d3()) | |
6d0485a9 | 106 | |
2eeaaa21 AV |
107 | static LIST_HEAD(clocks); |
108 | static DEFINE_SPINLOCK(clk_lock); | |
73a59c1c | 109 | |
2eeaaa21 | 110 | static u32 at91_pllb_usb_init; |
73a59c1c SP |
111 | |
112 | /* | |
113 | * Four primary clock sources: two crystal oscillators (32K, main), and | |
114 | * two PLLs. PLLA usually runs the master clock; and PLLB must run at | |
115 | * 48 MHz (unless no USB function clocks are needed). The main clock and | |
116 | * both PLLs are turned off to run in "slow clock mode" (system suspend). | |
117 | */ | |
118 | static struct clk clk32k = { | |
119 | .name = "clk32k", | |
120 | .rate_hz = AT91_SLOW_CLOCK, | |
121 | .users = 1, /* always on */ | |
122 | .id = 0, | |
2eeaaa21 | 123 | .type = CLK_TYPE_PRIMARY, |
73a59c1c SP |
124 | }; |
125 | static struct clk main_clk = { | |
126 | .name = "main", | |
91f8ed83 | 127 | .pmc_mask = AT91_PMC_MOSCS, /* in PMC_SR */ |
73a59c1c | 128 | .id = 1, |
2eeaaa21 | 129 | .type = CLK_TYPE_PRIMARY, |
73a59c1c SP |
130 | }; |
131 | static struct clk plla = { | |
132 | .name = "plla", | |
133 | .parent = &main_clk, | |
91f8ed83 | 134 | .pmc_mask = AT91_PMC_LOCKA, /* in PMC_SR */ |
73a59c1c | 135 | .id = 2, |
2eeaaa21 | 136 | .type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL, |
73a59c1c SP |
137 | }; |
138 | ||
139 | static void pllb_mode(struct clk *clk, int is_on) | |
140 | { | |
141 | u32 value; | |
142 | ||
143 | if (is_on) { | |
144 | is_on = AT91_PMC_LOCKB; | |
145 | value = at91_pllb_usb_init; | |
146 | } else | |
147 | value = 0; | |
148 | ||
2eeaaa21 | 149 | // REVISIT: Add work-around for AT91RM9200 Errata #26 ? |
b5514952 | 150 | at91_pmc_write(AT91_CKGR_PLLBR, value); |
73a59c1c SP |
151 | |
152 | do { | |
153 | cpu_relax(); | |
b5514952 | 154 | } while ((at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != is_on); |
73a59c1c SP |
155 | } |
156 | ||
157 | static struct clk pllb = { | |
158 | .name = "pllb", | |
159 | .parent = &main_clk, | |
91f8ed83 | 160 | .pmc_mask = AT91_PMC_LOCKB, /* in PMC_SR */ |
73a59c1c SP |
161 | .mode = pllb_mode, |
162 | .id = 3, | |
2eeaaa21 | 163 | .type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL, |
73a59c1c SP |
164 | }; |
165 | ||
166 | static void pmc_sys_mode(struct clk *clk, int is_on) | |
167 | { | |
168 | if (is_on) | |
b5514952 | 169 | at91_pmc_write(AT91_PMC_SCER, clk->pmc_mask); |
73a59c1c | 170 | else |
b5514952 | 171 | at91_pmc_write(AT91_PMC_SCDR, clk->pmc_mask); |
73a59c1c SP |
172 | } |
173 | ||
53d71680 SP |
174 | static void pmc_uckr_mode(struct clk *clk, int is_on) |
175 | { | |
b5514952 | 176 | unsigned int uckr = at91_pmc_read(AT91_CKGR_UCKR); |
53d71680 SP |
177 | |
178 | if (is_on) { | |
179 | is_on = AT91_PMC_LOCKU; | |
b5514952 | 180 | at91_pmc_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask); |
53d71680 | 181 | } else |
b5514952 | 182 | at91_pmc_write(AT91_CKGR_UCKR, uckr & ~(clk->pmc_mask)); |
53d71680 SP |
183 | |
184 | do { | |
185 | cpu_relax(); | |
b5514952 | 186 | } while ((at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKU) != is_on); |
53d71680 SP |
187 | } |
188 | ||
73a59c1c SP |
189 | /* USB function clocks (PLLB must be 48 MHz) */ |
190 | static struct clk udpck = { | |
191 | .name = "udpck", | |
192 | .parent = &pllb, | |
73a59c1c SP |
193 | .mode = pmc_sys_mode, |
194 | }; | |
bd602995 | 195 | struct clk utmi_clk = { |
53d71680 SP |
196 | .name = "utmi_clk", |
197 | .parent = &main_clk, | |
198 | .pmc_mask = AT91_PMC_UPLLEN, /* in CKGR_UCKR */ | |
199 | .mode = pmc_uckr_mode, | |
200 | .type = CLK_TYPE_PLL, | |
201 | }; | |
73a59c1c SP |
202 | static struct clk uhpck = { |
203 | .name = "uhpck", | |
6d0485a9 | 204 | /*.parent = ... we choose parent at runtime */ |
73a59c1c SP |
205 | .mode = pmc_sys_mode, |
206 | }; | |
207 | ||
73a59c1c SP |
208 | |
209 | /* | |
210 | * The master clock is divided from the CPU clock (by 1-4). It's used for | |
211 | * memory, interfaces to on-chip peripherals, the AIC, and sometimes more | |
212 | * (e.g baud rate generation). It's sourced from one of the primary clocks. | |
213 | */ | |
bd602995 | 214 | struct clk mck = { |
73a59c1c | 215 | .name = "mck", |
91f8ed83 | 216 | .pmc_mask = AT91_PMC_MCKRDY, /* in PMC_SR */ |
73a59c1c SP |
217 | }; |
218 | ||
219 | static void pmc_periph_mode(struct clk *clk, int is_on) | |
220 | { | |
8f4b4794 LD |
221 | u32 regval = 0; |
222 | ||
223 | /* | |
224 | * With sama5d3 devices, we are managing clock division so we have to | |
225 | * use the Peripheral Control Register introduced from at91sam9x5 | |
226 | * devices. | |
227 | */ | |
228 | if (cpu_is_sama5d3()) { | |
229 | regval |= AT91_PMC_PCR_CMD; /* write command */ | |
230 | regval |= clk->pid & AT91_PMC_PCR_PID; /* peripheral selection */ | |
231 | regval |= AT91_PMC_PCR_DIV(clk->div); | |
232 | if (is_on) | |
233 | regval |= AT91_PMC_PCR_EN; /* enable clock */ | |
234 | at91_pmc_write(AT91_PMC_PCR, regval); | |
235 | } else { | |
236 | if (is_on) | |
237 | at91_pmc_write(AT91_PMC_PCER, clk->pmc_mask); | |
238 | else | |
239 | at91_pmc_write(AT91_PMC_PCDR, clk->pmc_mask); | |
240 | } | |
73a59c1c SP |
241 | } |
242 | ||
2eeaaa21 AV |
243 | static struct clk __init *at91_css_to_clk(unsigned long css) |
244 | { | |
245 | switch (css) { | |
246 | case AT91_PMC_CSS_SLOW: | |
247 | return &clk32k; | |
248 | case AT91_PMC_CSS_MAIN: | |
249 | return &main_clk; | |
250 | case AT91_PMC_CSS_PLLA: | |
251 | return &plla; | |
252 | case AT91_PMC_CSS_PLLB: | |
6d0485a9 NF |
253 | if (cpu_has_upll()) |
254 | /* CSS_PLLB == CSS_UPLL */ | |
255 | return &utmi_clk; | |
256 | else if (cpu_has_pllb()) | |
257 | return &pllb; | |
11128726 NF |
258 | break; |
259 | /* alternate PMC: can use master clock */ | |
260 | case AT91_PMC_CSS_MASTER: | |
261 | return &mck; | |
2eeaaa21 | 262 | } |
73a59c1c | 263 | |
2eeaaa21 AV |
264 | return NULL; |
265 | } | |
73a59c1c | 266 | |
11128726 NF |
267 | static int pmc_prescaler_divider(u32 reg) |
268 | { | |
269 | if (cpu_has_alt_prescaler()) { | |
270 | return 1 << ((reg & AT91_PMC_ALT_PRES) >> PMC_ALT_PRES_OFFSET); | |
271 | } else { | |
272 | return 1 << ((reg & AT91_PMC_PRES) >> PMC_PRES_OFFSET); | |
273 | } | |
274 | } | |
275 | ||
73a59c1c SP |
276 | static void __clk_enable(struct clk *clk) |
277 | { | |
278 | if (clk->parent) | |
279 | __clk_enable(clk->parent); | |
280 | if (clk->users++ == 0 && clk->mode) | |
281 | clk->mode(clk, 1); | |
282 | } | |
283 | ||
284 | int clk_enable(struct clk *clk) | |
285 | { | |
286 | unsigned long flags; | |
287 | ||
288 | spin_lock_irqsave(&clk_lock, flags); | |
289 | __clk_enable(clk); | |
290 | spin_unlock_irqrestore(&clk_lock, flags); | |
291 | return 0; | |
292 | } | |
293 | EXPORT_SYMBOL(clk_enable); | |
294 | ||
295 | static void __clk_disable(struct clk *clk) | |
296 | { | |
297 | BUG_ON(clk->users == 0); | |
298 | if (--clk->users == 0 && clk->mode) | |
299 | clk->mode(clk, 0); | |
300 | if (clk->parent) | |
301 | __clk_disable(clk->parent); | |
302 | } | |
303 | ||
304 | void clk_disable(struct clk *clk) | |
305 | { | |
306 | unsigned long flags; | |
307 | ||
308 | spin_lock_irqsave(&clk_lock, flags); | |
309 | __clk_disable(clk); | |
310 | spin_unlock_irqrestore(&clk_lock, flags); | |
311 | } | |
312 | EXPORT_SYMBOL(clk_disable); | |
313 | ||
314 | unsigned long clk_get_rate(struct clk *clk) | |
315 | { | |
316 | unsigned long flags; | |
317 | unsigned long rate; | |
318 | ||
319 | spin_lock_irqsave(&clk_lock, flags); | |
320 | for (;;) { | |
321 | rate = clk->rate_hz; | |
322 | if (rate || !clk->parent) | |
323 | break; | |
324 | clk = clk->parent; | |
325 | } | |
326 | spin_unlock_irqrestore(&clk_lock, flags); | |
327 | return rate; | |
328 | } | |
329 | EXPORT_SYMBOL(clk_get_rate); | |
330 | ||
331 | /*------------------------------------------------------------------------*/ | |
332 | ||
333 | #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS | |
334 | ||
335 | /* | |
336 | * For now, only the programmable clocks support reparenting (MCK could | |
337 | * do this too, with care) or rate changing (the PLLs could do this too, | |
338 | * ditto MCK but that's more for cpufreq). Drivers may reparent to get | |
339 | * a better rate match; we don't. | |
340 | */ | |
341 | ||
342 | long clk_round_rate(struct clk *clk, unsigned long rate) | |
343 | { | |
344 | unsigned long flags; | |
345 | unsigned prescale; | |
346 | unsigned long actual; | |
2ef9df7a | 347 | unsigned long prev = ULONG_MAX; |
73a59c1c | 348 | |
2eeaaa21 | 349 | if (!clk_is_programmable(clk)) |
73a59c1c SP |
350 | return -EINVAL; |
351 | spin_lock_irqsave(&clk_lock, flags); | |
352 | ||
353 | actual = clk->parent->rate_hz; | |
354 | for (prescale = 0; prescale < 7; prescale++) { | |
2ef9df7a NF |
355 | if (actual > rate) |
356 | prev = actual; | |
357 | ||
358 | if (actual && actual <= rate) { | |
359 | if ((prev - rate) < (rate - actual)) { | |
360 | actual = prev; | |
361 | prescale--; | |
362 | } | |
73a59c1c | 363 | break; |
2ef9df7a | 364 | } |
73a59c1c SP |
365 | actual >>= 1; |
366 | } | |
367 | ||
368 | spin_unlock_irqrestore(&clk_lock, flags); | |
369 | return (prescale < 7) ? actual : -ENOENT; | |
370 | } | |
371 | EXPORT_SYMBOL(clk_round_rate); | |
372 | ||
373 | int clk_set_rate(struct clk *clk, unsigned long rate) | |
374 | { | |
375 | unsigned long flags; | |
376 | unsigned prescale; | |
11128726 | 377 | unsigned long prescale_offset, css_mask; |
73a59c1c SP |
378 | unsigned long actual; |
379 | ||
2eeaaa21 | 380 | if (!clk_is_programmable(clk)) |
73a59c1c SP |
381 | return -EINVAL; |
382 | if (clk->users) | |
383 | return -EBUSY; | |
11128726 NF |
384 | |
385 | if (cpu_has_alt_prescaler()) { | |
386 | prescale_offset = PMC_ALT_PRES_OFFSET; | |
387 | css_mask = AT91_PMC_ALT_PCKR_CSS; | |
388 | } else { | |
389 | prescale_offset = PMC_PRES_OFFSET; | |
390 | css_mask = AT91_PMC_CSS; | |
391 | } | |
392 | ||
73a59c1c SP |
393 | spin_lock_irqsave(&clk_lock, flags); |
394 | ||
395 | actual = clk->parent->rate_hz; | |
396 | for (prescale = 0; prescale < 7; prescale++) { | |
397 | if (actual && actual <= rate) { | |
398 | u32 pckr; | |
399 | ||
b5514952 | 400 | pckr = at91_pmc_read(AT91_PMC_PCKR(clk->id)); |
11128726 NF |
401 | pckr &= css_mask; /* keep clock selection */ |
402 | pckr |= prescale << prescale_offset; | |
b5514952 | 403 | at91_pmc_write(AT91_PMC_PCKR(clk->id), pckr); |
73a59c1c SP |
404 | clk->rate_hz = actual; |
405 | break; | |
406 | } | |
407 | actual >>= 1; | |
408 | } | |
409 | ||
410 | spin_unlock_irqrestore(&clk_lock, flags); | |
411 | return (prescale < 7) ? actual : -ENOENT; | |
412 | } | |
413 | EXPORT_SYMBOL(clk_set_rate); | |
414 | ||
415 | struct clk *clk_get_parent(struct clk *clk) | |
416 | { | |
417 | return clk->parent; | |
418 | } | |
419 | EXPORT_SYMBOL(clk_get_parent); | |
420 | ||
421 | int clk_set_parent(struct clk *clk, struct clk *parent) | |
422 | { | |
423 | unsigned long flags; | |
424 | ||
425 | if (clk->users) | |
426 | return -EBUSY; | |
2eeaaa21 | 427 | if (!clk_is_primary(parent) || !clk_is_programmable(clk)) |
73a59c1c | 428 | return -EINVAL; |
2ef9df7a NF |
429 | |
430 | if (cpu_is_at91sam9rl() && parent->id == AT91_PMC_CSS_PLLB) | |
431 | return -EINVAL; | |
432 | ||
73a59c1c SP |
433 | spin_lock_irqsave(&clk_lock, flags); |
434 | ||
435 | clk->rate_hz = parent->rate_hz; | |
436 | clk->parent = parent; | |
b5514952 | 437 | at91_pmc_write(AT91_PMC_PCKR(clk->id), parent->id); |
73a59c1c SP |
438 | |
439 | spin_unlock_irqrestore(&clk_lock, flags); | |
440 | return 0; | |
441 | } | |
442 | EXPORT_SYMBOL(clk_set_parent); | |
443 | ||
6d0485a9 | 444 | /* establish PCK0..PCKN parentage and rate */ |
72e7ae81 | 445 | static void __init init_programmable_clock(struct clk *clk) |
2eeaaa21 AV |
446 | { |
447 | struct clk *parent; | |
448 | u32 pckr; | |
11128726 NF |
449 | unsigned int css_mask; |
450 | ||
451 | if (cpu_has_alt_prescaler()) | |
452 | css_mask = AT91_PMC_ALT_PCKR_CSS; | |
453 | else | |
454 | css_mask = AT91_PMC_CSS; | |
2eeaaa21 | 455 | |
b5514952 | 456 | pckr = at91_pmc_read(AT91_PMC_PCKR(clk->id)); |
11128726 | 457 | parent = at91_css_to_clk(pckr & css_mask); |
2eeaaa21 | 458 | clk->parent = parent; |
11128726 | 459 | clk->rate_hz = parent->rate_hz / pmc_prescaler_divider(pckr); |
2eeaaa21 AV |
460 | } |
461 | ||
73a59c1c SP |
462 | #endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */ |
463 | ||
464 | /*------------------------------------------------------------------------*/ | |
465 | ||
466 | #ifdef CONFIG_DEBUG_FS | |
467 | ||
468 | static int at91_clk_show(struct seq_file *s, void *unused) | |
469 | { | |
8f4b4794 | 470 | u32 scsr, pcsr, pcsr1 = 0, uckr = 0, sr; |
2eeaaa21 | 471 | struct clk *clk; |
73a59c1c | 472 | |
b5514952 JCPV |
473 | scsr = at91_pmc_read(AT91_PMC_SCSR); |
474 | pcsr = at91_pmc_read(AT91_PMC_PCSR); | |
8f4b4794 LD |
475 | if (cpu_is_sama5d3()) |
476 | pcsr1 = at91_pmc_read(AT91_PMC_PCSR1); | |
b5514952 | 477 | sr = at91_pmc_read(AT91_PMC_SR); |
940192e3 NF |
478 | seq_printf(s, "SCSR = %8x\n", scsr); |
479 | seq_printf(s, "PCSR = %8x\n", pcsr); | |
8f4b4794 LD |
480 | if (cpu_is_sama5d3()) |
481 | seq_printf(s, "PCSR1 = %8x\n", pcsr1); | |
b5514952 JCPV |
482 | seq_printf(s, "MOR = %8x\n", at91_pmc_read(AT91_CKGR_MOR)); |
483 | seq_printf(s, "MCFR = %8x\n", at91_pmc_read(AT91_CKGR_MCFR)); | |
484 | seq_printf(s, "PLLA = %8x\n", at91_pmc_read(AT91_CKGR_PLLAR)); | |
6d0485a9 | 485 | if (cpu_has_pllb()) |
b5514952 | 486 | seq_printf(s, "PLLB = %8x\n", at91_pmc_read(AT91_CKGR_PLLBR)); |
940192e3 | 487 | if (cpu_has_utmi()) { |
b5514952 | 488 | uckr = at91_pmc_read(AT91_CKGR_UCKR); |
940192e3 NF |
489 | seq_printf(s, "UCKR = %8x\n", uckr); |
490 | } | |
b5514952 | 491 | seq_printf(s, "MCKR = %8x\n", at91_pmc_read(AT91_PMC_MCKR)); |
6d0485a9 | 492 | if (cpu_has_upll()) |
b5514952 | 493 | seq_printf(s, "USB = %8x\n", at91_pmc_read(AT91_PMC_USB)); |
940192e3 | 494 | seq_printf(s, "SR = %8x\n", sr); |
73a59c1c SP |
495 | |
496 | seq_printf(s, "\n"); | |
497 | ||
2eeaaa21 AV |
498 | list_for_each_entry(clk, &clocks, node) { |
499 | char *state; | |
73a59c1c | 500 | |
8f4b4794 | 501 | if (clk->mode == pmc_sys_mode) { |
73a59c1c | 502 | state = (scsr & clk->pmc_mask) ? "on" : "off"; |
8f4b4794 LD |
503 | } else if (clk->mode == pmc_periph_mode) { |
504 | if (cpu_is_sama5d3()) { | |
505 | u32 pmc_mask = 1 << (clk->pid % 32); | |
506 | ||
507 | if (clk->pid > 31) | |
508 | state = (pcsr1 & pmc_mask) ? "on" : "off"; | |
509 | else | |
510 | state = (pcsr & pmc_mask) ? "on" : "off"; | |
511 | } else { | |
512 | state = (pcsr & clk->pmc_mask) ? "on" : "off"; | |
513 | } | |
514 | } else if (clk->mode == pmc_uckr_mode) { | |
53d71680 | 515 | state = (uckr & clk->pmc_mask) ? "on" : "off"; |
8f4b4794 | 516 | } else if (clk->pmc_mask) { |
73a59c1c | 517 | state = (sr & clk->pmc_mask) ? "on" : "off"; |
8f4b4794 | 518 | } else if (clk == &clk32k || clk == &main_clk) { |
73a59c1c | 519 | state = "on"; |
8f4b4794 | 520 | } else { |
73a59c1c | 521 | state = ""; |
8f4b4794 | 522 | } |
73a59c1c | 523 | |
8f4b4794 | 524 | seq_printf(s, "%-10s users=%2d %-3s %9lu Hz %s\n", |
73a59c1c SP |
525 | clk->name, clk->users, state, clk_get_rate(clk), |
526 | clk->parent ? clk->parent->name : ""); | |
527 | } | |
528 | return 0; | |
529 | } | |
530 | ||
531 | static int at91_clk_open(struct inode *inode, struct file *file) | |
532 | { | |
533 | return single_open(file, at91_clk_show, NULL); | |
534 | } | |
535 | ||
5dfe4c96 | 536 | static const struct file_operations at91_clk_operations = { |
73a59c1c SP |
537 | .open = at91_clk_open, |
538 | .read = seq_read, | |
539 | .llseek = seq_lseek, | |
540 | .release = single_release, | |
541 | }; | |
542 | ||
543 | static int __init at91_clk_debugfs_init(void) | |
544 | { | |
545 | /* /sys/kernel/debug/at91_clk */ | |
546 | (void) debugfs_create_file("at91_clk", S_IFREG | S_IRUGO, NULL, NULL, &at91_clk_operations); | |
547 | ||
548 | return 0; | |
549 | } | |
550 | postcore_initcall(at91_clk_debugfs_init); | |
551 | ||
552 | #endif | |
553 | ||
2eeaaa21 AV |
554 | /*------------------------------------------------------------------------*/ |
555 | ||
556 | /* Register a new clock */ | |
bd602995 JCPV |
557 | static void __init at91_clk_add(struct clk *clk) |
558 | { | |
559 | list_add_tail(&clk->node, &clocks); | |
560 | ||
561 | clk->cl.con_id = clk->name; | |
562 | clk->cl.clk = clk; | |
563 | clkdev_add(&clk->cl); | |
564 | } | |
565 | ||
2eeaaa21 AV |
566 | int __init clk_register(struct clk *clk) |
567 | { | |
568 | if (clk_is_peripheral(clk)) { | |
5afddee4 NF |
569 | if (!clk->parent) |
570 | clk->parent = &mck; | |
8f4b4794 LD |
571 | if (cpu_is_sama5d3()) |
572 | clk->rate_hz = DIV_ROUND_UP(clk->parent->rate_hz, | |
573 | 1 << clk->div); | |
2eeaaa21 | 574 | clk->mode = pmc_periph_mode; |
2eeaaa21 | 575 | } |
d481f864 AV |
576 | else if (clk_is_sys(clk)) { |
577 | clk->parent = &mck; | |
578 | clk->mode = pmc_sys_mode; | |
d481f864 | 579 | } |
2eeaaa21 AV |
580 | #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS |
581 | else if (clk_is_programmable(clk)) { | |
582 | clk->mode = pmc_sys_mode; | |
583 | init_programmable_clock(clk); | |
2eeaaa21 AV |
584 | } |
585 | #endif | |
586 | ||
bd602995 JCPV |
587 | at91_clk_add(clk); |
588 | ||
2eeaaa21 AV |
589 | return 0; |
590 | } | |
591 | ||
73a59c1c SP |
592 | /*------------------------------------------------------------------------*/ |
593 | ||
594 | static u32 __init at91_pll_rate(struct clk *pll, u32 freq, u32 reg) | |
595 | { | |
596 | unsigned mul, div; | |
597 | ||
598 | div = reg & 0xff; | |
8f4b4794 LD |
599 | if (cpu_is_sama5d3()) |
600 | mul = AT91_PMC3_MUL_GET(reg); | |
601 | else | |
602 | mul = AT91_PMC_MUL_GET(reg); | |
603 | ||
73a59c1c SP |
604 | if (div && mul) { |
605 | freq /= div; | |
606 | freq *= mul + 1; | |
607 | } else | |
608 | freq = 0; | |
69b648a2 | 609 | |
73a59c1c SP |
610 | return freq; |
611 | } | |
612 | ||
69b648a2 AV |
613 | static u32 __init at91_usb_rate(struct clk *pll, u32 freq, u32 reg) |
614 | { | |
615 | if (pll == &pllb && (reg & AT91_PMC_USB96M)) | |
616 | return freq / 2; | |
617 | else | |
618 | return freq; | |
619 | } | |
620 | ||
73a59c1c SP |
621 | static unsigned __init at91_pll_calc(unsigned main_freq, unsigned out_freq) |
622 | { | |
623 | unsigned i, div = 0, mul = 0, diff = 1 << 30; | |
624 | unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00; | |
625 | ||
626 | /* PLL output max 240 MHz (or 180 MHz per errata) */ | |
627 | if (out_freq > 240000000) | |
628 | goto fail; | |
629 | ||
630 | for (i = 1; i < 256; i++) { | |
631 | int diff1; | |
632 | unsigned input, mul1; | |
633 | ||
634 | /* | |
635 | * PLL input between 1MHz and 32MHz per spec, but lower | |
636 | * frequences seem necessary in some cases so allow 100K. | |
61352667 | 637 | * Warning: some newer products need 2MHz min. |
73a59c1c SP |
638 | */ |
639 | input = main_freq / i; | |
61352667 | 640 | if (cpu_is_at91sam9g20() && input < 2000000) |
641 | continue; | |
73a59c1c SP |
642 | if (input < 100000) |
643 | continue; | |
644 | if (input > 32000000) | |
645 | continue; | |
646 | ||
647 | mul1 = out_freq / input; | |
61352667 | 648 | if (cpu_is_at91sam9g20() && mul > 63) |
649 | continue; | |
73a59c1c SP |
650 | if (mul1 > 2048) |
651 | continue; | |
652 | if (mul1 < 2) | |
653 | goto fail; | |
654 | ||
655 | diff1 = out_freq - input * mul1; | |
656 | if (diff1 < 0) | |
657 | diff1 = -diff1; | |
658 | if (diff > diff1) { | |
659 | diff = diff1; | |
660 | div = i; | |
661 | mul = mul1; | |
662 | if (diff == 0) | |
663 | break; | |
664 | } | |
665 | } | |
666 | if (i == 256 && diff > (out_freq >> 5)) | |
667 | goto fail; | |
668 | return ret | ((mul - 1) << 16) | div; | |
669 | fail: | |
670 | return 0; | |
671 | } | |
672 | ||
bcad6dc3 | 673 | static struct clk *const standard_pmc_clocks[] __initconst = { |
2eeaaa21 AV |
674 | /* four primary clocks */ |
675 | &clk32k, | |
676 | &main_clk, | |
677 | &plla, | |
2eeaaa21 AV |
678 | |
679 | /* MCK */ | |
680 | &mck | |
681 | }; | |
682 | ||
6d0485a9 NF |
683 | /* PLLB generated USB full speed clock init */ |
684 | static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock) | |
685 | { | |
686 | /* | |
687 | * USB clock init: choose 48 MHz PLLB value, | |
688 | * disable 48MHz clock during usb peripheral suspend. | |
689 | * | |
690 | * REVISIT: assumes MCK doesn't derive from PLLB! | |
691 | */ | |
692 | uhpck.parent = &pllb; | |
693 | ||
694 | at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M; | |
695 | pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init); | |
696 | if (cpu_is_at91rm9200()) { | |
697 | uhpck.pmc_mask = AT91RM9200_PMC_UHP; | |
698 | udpck.pmc_mask = AT91RM9200_PMC_UDP; | |
b5514952 | 699 | at91_pmc_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP); |
eab41708 NF |
700 | } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || |
701 | cpu_is_at91sam9263() || cpu_is_at91sam9g20() || | |
7a2207a0 | 702 | cpu_is_at91sam9g10()) { |
6d0485a9 NF |
703 | uhpck.pmc_mask = AT91SAM926x_PMC_UHP; |
704 | udpck.pmc_mask = AT91SAM926x_PMC_UDP; | |
6d0485a9 | 705 | } |
b5514952 | 706 | at91_pmc_write(AT91_CKGR_PLLBR, 0); |
6d0485a9 NF |
707 | |
708 | udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); | |
709 | uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); | |
710 | } | |
711 | ||
712 | /* UPLL generated USB full speed clock init */ | |
713 | static void __init at91_upll_usbfs_clock_init(unsigned long main_clock) | |
714 | { | |
715 | /* | |
716 | * USB clock init: choose 480 MHz from UPLL, | |
717 | */ | |
718 | unsigned int usbr = AT91_PMC_USBS_UPLL; | |
719 | ||
720 | /* Setup divider by 10 to reach 48 MHz */ | |
721 | usbr |= ((10 - 1) << 8) & AT91_PMC_OHCIUSBDIV; | |
722 | ||
b5514952 | 723 | at91_pmc_write(AT91_PMC_USB, usbr); |
6d0485a9 NF |
724 | |
725 | /* Now set uhpck values */ | |
726 | uhpck.parent = &utmi_clk; | |
727 | uhpck.pmc_mask = AT91SAM926x_PMC_UHP; | |
8251544f | 728 | uhpck.rate_hz = utmi_clk.rate_hz; |
b5514952 | 729 | uhpck.rate_hz /= 1 + ((at91_pmc_read(AT91_PMC_USB) & AT91_PMC_OHCIUSBDIV) >> 8); |
6d0485a9 NF |
730 | } |
731 | ||
eb5e76ff | 732 | static int __init at91_pmc_init(unsigned long main_clock) |
73a59c1c SP |
733 | { |
734 | unsigned tmp, freq, mckr; | |
2eeaaa21 | 735 | int i; |
2ef9df7a | 736 | int pll_overclock = false; |
73a59c1c SP |
737 | |
738 | /* | |
739 | * When the bootloader initialized the main oscillator correctly, | |
740 | * there's no problem using the cycle counter. But if it didn't, | |
741 | * or when using oscillator bypass mode, we must be told the speed | |
742 | * of the main clock. | |
743 | */ | |
744 | if (!main_clock) { | |
745 | do { | |
b5514952 | 746 | tmp = at91_pmc_read(AT91_CKGR_MCFR); |
69b648a2 AV |
747 | } while (!(tmp & AT91_PMC_MAINRDY)); |
748 | main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16); | |
73a59c1c SP |
749 | } |
750 | main_clk.rate_hz = main_clock; | |
751 | ||
752 | /* report if PLLA is more than mildly overclocked */ | |
b5514952 | 753 | plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_pmc_read(AT91_CKGR_PLLAR)); |
8f4b4794 LD |
754 | if (cpu_has_1056M_plla()) { |
755 | if (plla.rate_hz > 1056000000) | |
2ef9df7a NF |
756 | pll_overclock = true; |
757 | } else if (cpu_has_800M_plla()) { | |
758 | if (plla.rate_hz > 800000000) | |
759 | pll_overclock = true; | |
8f4b4794 LD |
760 | } else if (cpu_has_300M_plla()) { |
761 | if (plla.rate_hz > 300000000) | |
762 | pll_overclock = true; | |
2ed1f589 NF |
763 | } else if (cpu_has_240M_plla()) { |
764 | if (plla.rate_hz > 240000000) | |
765 | pll_overclock = true; | |
766 | } else if (cpu_has_210M_plla()) { | |
767 | if (plla.rate_hz > 210000000) | |
768 | pll_overclock = true; | |
2ef9df7a NF |
769 | } else { |
770 | if (plla.rate_hz > 209000000) | |
771 | pll_overclock = true; | |
772 | } | |
773 | if (pll_overclock) | |
73a59c1c SP |
774 | pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000); |
775 | ||
11128726 | 776 | if (cpu_has_plladiv2()) { |
b5514952 | 777 | mckr = at91_pmc_read(AT91_PMC_MCKR); |
2ef9df7a NF |
778 | plla.rate_hz /= (1 << ((mckr & AT91_PMC_PLLADIV2) >> 12)); /* plla divisor by 2 */ |
779 | } | |
6d0485a9 | 780 | |
2ef9df7a | 781 | if (!cpu_has_pllb() && cpu_has_upll()) { |
6d0485a9 NF |
782 | /* setup UTMI clock as the fourth primary clock |
783 | * (instead of pllb) */ | |
784 | utmi_clk.type |= CLK_TYPE_PRIMARY; | |
785 | utmi_clk.id = 3; | |
d481f864 | 786 | } |
73a59c1c | 787 | |
69b648a2 | 788 | |
53d71680 SP |
789 | /* |
790 | * USB HS clock init | |
791 | */ | |
5e38efae | 792 | if (cpu_has_utmi()) { |
53d71680 SP |
793 | /* |
794 | * multiplier is hard-wired to 40 | |
795 | * (obtain the USB High Speed 480 MHz when input is 12 MHz) | |
796 | */ | |
797 | utmi_clk.rate_hz = 40 * utmi_clk.parent->rate_hz; | |
11128726 NF |
798 | |
799 | /* UTMI bias and PLL are managed at the same time */ | |
800 | if (cpu_has_upll()) | |
801 | utmi_clk.pmc_mask |= AT91_PMC_BIASEN; | |
5e38efae | 802 | } |
6d0485a9 NF |
803 | |
804 | /* | |
805 | * USB FS clock init | |
806 | */ | |
807 | if (cpu_has_pllb()) | |
808 | at91_pllb_usbfs_clock_init(main_clock); | |
809 | if (cpu_has_upll()) | |
810 | /* assumes that we choose UPLL for USB and not PLLA */ | |
811 | at91_upll_usbfs_clock_init(main_clock); | |
53d71680 | 812 | |
73a59c1c SP |
813 | /* |
814 | * MCK and CPU derive from one of those primary clocks. | |
815 | * For now, assume this parentage won't change. | |
816 | */ | |
b5514952 | 817 | mckr = at91_pmc_read(AT91_PMC_MCKR); |
2eeaaa21 | 818 | mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS); |
73a59c1c | 819 | freq = mck.parent->rate_hz; |
11128726 | 820 | freq /= pmc_prescaler_divider(mckr); /* prescale */ |
6d0485a9 | 821 | if (cpu_is_at91rm9200()) { |
a95c729b | 822 | mck.rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ |
6d0485a9 | 823 | } else if (cpu_is_at91sam9g20()) { |
61352667 | 824 | mck.rate_hz = (mckr & AT91_PMC_MDIV) ? |
825 | freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq; /* mdiv ; (x >> 7) = ((x >> 8) * 2) */ | |
826 | if (mckr & AT91_PMC_PDIV) | |
827 | freq /= 2; /* processor clock division */ | |
11128726 | 828 | } else if (cpu_has_mdiv3()) { |
2ef9df7a NF |
829 | mck.rate_hz = (mckr & AT91_PMC_MDIV) == AT91SAM9_PMC_MDIV_3 ? |
830 | freq / 3 : freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ | |
6d0485a9 | 831 | } else { |
5e38efae | 832 | mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ |
6d0485a9 | 833 | } |
73a59c1c | 834 | |
11128726 NF |
835 | if (cpu_has_alt_prescaler()) { |
836 | /* Programmable clocks can use MCK */ | |
837 | mck.type |= CLK_TYPE_PRIMARY; | |
838 | mck.id = 4; | |
839 | } | |
840 | ||
2eeaaa21 AV |
841 | /* Register the PMC's standard clocks */ |
842 | for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++) | |
bd602995 | 843 | at91_clk_add(standard_pmc_clocks[i]); |
2eeaaa21 | 844 | |
6d0485a9 | 845 | if (cpu_has_pllb()) |
bd602995 | 846 | at91_clk_add(&pllb); |
6d0485a9 NF |
847 | |
848 | if (cpu_has_uhp()) | |
bd602995 | 849 | at91_clk_add(&uhpck); |
6d0485a9 NF |
850 | |
851 | if (cpu_has_udpfs()) | |
bd602995 | 852 | at91_clk_add(&udpck); |
6d0485a9 NF |
853 | |
854 | if (cpu_has_utmi()) | |
bd602995 | 855 | at91_clk_add(&utmi_clk); |
53d71680 | 856 | |
91f8ed83 AV |
857 | /* MCK and CPU clock are "always on" */ |
858 | clk_enable(&mck); | |
859 | ||
73a59c1c SP |
860 | printk("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n", |
861 | freq / 1000000, (unsigned) mck.rate_hz / 1000000, | |
862 | (unsigned) main_clock / 1000000, | |
863 | ((unsigned) main_clock % 1000000) / 1000); | |
864 | ||
c9b75d13 AV |
865 | return 0; |
866 | } | |
867 | ||
eb5e76ff JCPV |
868 | #if defined(CONFIG_OF) |
869 | static struct of_device_id pmc_ids[] = { | |
870 | { .compatible = "atmel,at91rm9200-pmc" }, | |
871 | { /*sentinel*/ } | |
872 | }; | |
873 | ||
874 | static struct of_device_id osc_ids[] = { | |
875 | { .compatible = "atmel,osc" }, | |
876 | { /*sentinel*/ } | |
877 | }; | |
878 | ||
879 | int __init at91_dt_clock_init(void) | |
880 | { | |
881 | struct device_node *np; | |
882 | u32 main_clock = 0; | |
883 | ||
884 | np = of_find_matching_node(NULL, pmc_ids); | |
885 | if (!np) | |
886 | panic("unable to find compatible pmc node in dtb\n"); | |
887 | ||
888 | at91_pmc_base = of_iomap(np, 0); | |
889 | if (!at91_pmc_base) | |
890 | panic("unable to map pmc cpu registers\n"); | |
891 | ||
892 | of_node_put(np); | |
893 | ||
894 | /* retrieve the freqency of fixed clocks from device tree */ | |
895 | np = of_find_matching_node(NULL, osc_ids); | |
896 | if (np) { | |
897 | u32 rate; | |
898 | if (!of_property_read_u32(np, "clock-frequency", &rate)) | |
899 | main_clock = rate; | |
900 | } | |
901 | ||
902 | of_node_put(np); | |
903 | ||
904 | return at91_pmc_init(main_clock); | |
905 | } | |
906 | #endif | |
907 | ||
908 | int __init at91_clock_init(unsigned long main_clock) | |
909 | { | |
910 | at91_pmc_base = ioremap(AT91_PMC, 256); | |
911 | if (!at91_pmc_base) | |
912 | panic("Impossible to ioremap AT91_PMC 0x%x\n", AT91_PMC); | |
913 | ||
914 | return at91_pmc_init(main_clock); | |
915 | } | |
916 | ||
c9b75d13 AV |
917 | /* |
918 | * Several unused clocks may be active. Turn them off. | |
919 | */ | |
920 | static int __init at91_clock_reset(void) | |
921 | { | |
922 | unsigned long pcdr = 0; | |
8f4b4794 | 923 | unsigned long pcdr1 = 0; |
c9b75d13 AV |
924 | unsigned long scdr = 0; |
925 | struct clk *clk; | |
926 | ||
927 | list_for_each_entry(clk, &clocks, node) { | |
928 | if (clk->users > 0) | |
929 | continue; | |
930 | ||
8f4b4794 LD |
931 | if (clk->mode == pmc_periph_mode) { |
932 | if (cpu_is_sama5d3()) { | |
933 | u32 pmc_mask = 1 << (clk->pid % 32); | |
934 | ||
935 | if (clk->pid > 31) | |
936 | pcdr1 |= pmc_mask; | |
937 | else | |
938 | pcdr |= pmc_mask; | |
939 | } else | |
940 | pcdr |= clk->pmc_mask; | |
941 | } | |
c9b75d13 AV |
942 | |
943 | if (clk->mode == pmc_sys_mode) | |
944 | scdr |= clk->pmc_mask; | |
945 | ||
946 | pr_debug("Clocks: disable unused %s\n", clk->name); | |
947 | } | |
91f8ed83 | 948 | |
b5514952 | 949 | at91_pmc_write(AT91_PMC_SCDR, scdr); |
8f4b4794 LD |
950 | if (cpu_is_sama5d3()) |
951 | at91_pmc_write(AT91_PMC_PCDR1, pcdr1); | |
73a59c1c SP |
952 | |
953 | return 0; | |
954 | } | |
c9b75d13 | 955 | late_initcall(at91_clock_reset); |
0d781716 JCPV |
956 | |
957 | void at91sam9_idle(void) | |
958 | { | |
b5514952 | 959 | at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK); |
0d781716 JCPV |
960 | cpu_do_idle(); |
961 | } |