[deliverable/linux.git] / arch / arm / mach-at91 / clock.c

/*
 * linux/arch/arm/mach-at91/clock.c
 *
 * Copyright (C) 2005 David Brownell
 * Copyright (C) 2005 Ivan Kokshaysky
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/fs.h>
#include <linux/debugfs.h>
#include <linux/seq_file.h>
#include <linux/list.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/spinlock.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/io.h>

#include <mach/hardware.h>
#include <mach/at91_pmc.h>
#include <mach/cpu.h>

#include "clock.h"


/*
 * There's a lot more which can be done with clocks, including cpufreq
 * integration, slow clock mode support (for system suspend), letting
 * PLLB be used at other rates (on boards that don't need USB), etc.
 */

#define clk_is_primary(x)	((x)->type & CLK_TYPE_PRIMARY)
#define clk_is_programmable(x)	((x)->type & CLK_TYPE_PROGRAMMABLE)
#define clk_is_peripheral(x)	((x)->type & CLK_TYPE_PERIPHERAL)
#define clk_is_sys(x)		((x)->type & CLK_TYPE_SYSTEM)


static LIST_HEAD(clocks);
static DEFINE_SPINLOCK(clk_lock);

static u32 at91_pllb_usb_init;

/*
 * Four primary clock sources:  two crystal oscillators (32K, main), and
 * two PLLs.  PLLA usually runs the master clock; and PLLB must run at
 * 48 MHz (unless no USB function clocks are needed).  The main clock and
 * both PLLs are turned off to run in "slow clock mode" (system suspend).
 */
static struct clk clk32k = {
	.name		= "clk32k",
	.rate_hz	= AT91_SLOW_CLOCK,
	.users		= 1,		/* always on */
	.id		= 0,
	.type		= CLK_TYPE_PRIMARY,
};
static struct clk main_clk = {
	.name		= "main",
	.pmc_mask	= AT91_PMC_MOSCS,	/* in PMC_SR */
	.id		= 1,
	.type		= CLK_TYPE_PRIMARY,
};
static struct clk plla = {
	.name		= "plla",
	.parent		= &main_clk,
	.pmc_mask	= AT91_PMC_LOCKA,	/* in PMC_SR */
	.id		= 2,
	.type		= CLK_TYPE_PRIMARY | CLK_TYPE_PLL,
};

static void pllb_mode(struct clk *clk, int is_on)
{
	u32	value;

	if (is_on) {
		is_on = AT91_PMC_LOCKB;
		value = at91_pllb_usb_init;
	} else
		value = 0;

	// REVISIT: Add work-around for AT91RM9200 Errata #26 ?
	at91_sys_write(AT91_CKGR_PLLBR, value);

	do {
		cpu_relax();
	} while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != is_on);
}

static struct clk pllb = {
	.name		= "pllb",
	.parent		= &main_clk,
	.pmc_mask	= AT91_PMC_LOCKB,	/* in PMC_SR */
	.mode		= pllb_mode,
	.id		= 3,
	.type		= CLK_TYPE_PRIMARY | CLK_TYPE_PLL,
};

static void pmc_sys_mode(struct clk *clk, int is_on)
{
	if (is_on)
		at91_sys_write(AT91_PMC_SCER, clk->pmc_mask);
	else
		at91_sys_write(AT91_PMC_SCDR, clk->pmc_mask);
}

static void pmc_uckr_mode(struct clk *clk, int is_on)
{
	unsigned int uckr = at91_sys_read(AT91_CKGR_UCKR);

	if (is_on) {
		is_on = AT91_PMC_LOCKU;
		at91_sys_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask);
	} else
		at91_sys_write(AT91_CKGR_UCKR, uckr & ~(clk->pmc_mask));

	do {
		cpu_relax();
	} while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKU) != is_on);
}

/* USB function clocks (PLLB must be 48 MHz) */
static struct clk udpck = {
	.name		= "udpck",
	.parent		= &pllb,
	.mode		= pmc_sys_mode,
};
static struct clk utmi_clk = {
	.name		= "utmi_clk",
	.parent		= &main_clk,
	.pmc_mask	= AT91_PMC_UPLLEN,	/* in CKGR_UCKR */
	.mode		= pmc_uckr_mode,
	.type		= CLK_TYPE_PLL,
};
static struct clk uhpck = {
	.name		= "uhpck",
	.parent		= &pllb,
	.mode		= pmc_sys_mode,
};


/*
 * The master clock is divided from the CPU clock (by 1-4).  It's used for
 * memory, interfaces to on-chip peripherals, the AIC, and sometimes more
 * (e.g baud rate generation).  It's sourced from one of the primary clocks.
 */
static struct clk mck = {
	.name		= "mck",
	.pmc_mask	= AT91_PMC_MCKRDY,	/* in PMC_SR */
};

static void pmc_periph_mode(struct clk *clk, int is_on)
{
	if (is_on)
		at91_sys_write(AT91_PMC_PCER, clk->pmc_mask);
	else
		at91_sys_write(AT91_PMC_PCDR, clk->pmc_mask);
}

static struct clk __init *at91_css_to_clk(unsigned long css)
{
	switch (css) {
		case AT91_PMC_CSS_SLOW:
			return &clk32k;
		case AT91_PMC_CSS_MAIN:
			return &main_clk;
		case AT91_PMC_CSS_PLLA:
			return &plla;
		case AT91_PMC_CSS_PLLB:
			return &pllb;
	}

	return NULL;
}

/*
 * Associate a particular clock with a function (eg, "uart") and device.
 * The drivers can then request the same 'function' with several different
 * devices and not care about which clock name to use.
 */
void __init at91_clock_associate(const char *id, struct device *dev, const char *func)
{
	struct clk *clk = clk_get(NULL, id);

	if (!dev || !clk || !IS_ERR(clk_get(dev, func)))
		return;

	clk->function = func;
	clk->dev = dev;
}

/* clocks cannot be de-registered no refcounting necessary */
struct clk *clk_get(struct device *dev, const char *id)
{
	struct clk *clk;

	list_for_each_entry(clk, &clocks, node) {
		if (strcmp(id, clk->name) == 0)
			return clk;
		if (clk->function && (dev == clk->dev) && strcmp(id, clk->function) == 0)
			return clk;
	}

	return ERR_PTR(-ENOENT);
}
EXPORT_SYMBOL(clk_get);

void clk_put(struct clk *clk)
{
}
EXPORT_SYMBOL(clk_put);

static void __clk_enable(struct clk *clk)
{
	if (clk->parent)
		__clk_enable(clk->parent);
	if (clk->users++ == 0 && clk->mode)
		clk->mode(clk, 1);
}

int clk_enable(struct clk *clk)
{
	unsigned long	flags;

	spin_lock_irqsave(&clk_lock, flags);
	__clk_enable(clk);
	spin_unlock_irqrestore(&clk_lock, flags);
	return 0;
}
EXPORT_SYMBOL(clk_enable);

static void __clk_disable(struct clk *clk)
{
	BUG_ON(clk->users == 0);
	if (--clk->users == 0 && clk->mode)
		clk->mode(clk, 0);
	if (clk->parent)
		__clk_disable(clk->parent);
}

void clk_disable(struct clk *clk)
{
	unsigned long	flags;

	spin_lock_irqsave(&clk_lock, flags);
	__clk_disable(clk);
	spin_unlock_irqrestore(&clk_lock, flags);
}
EXPORT_SYMBOL(clk_disable);

unsigned long clk_get_rate(struct clk *clk)
{
	unsigned long	flags;
	unsigned long	rate;

	spin_lock_irqsave(&clk_lock, flags);
	for (;;) {
		rate = clk->rate_hz;
		if (rate || !clk->parent)
			break;
		clk = clk->parent;
	}
	spin_unlock_irqrestore(&clk_lock, flags);
	return rate;
}
EXPORT_SYMBOL(clk_get_rate);

/*------------------------------------------------------------------------*/

#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS

/*
 * For now, only the programmable clocks support reparenting (MCK could
 * do this too, with care) or rate changing (the PLLs could do this too,
 * ditto MCK but that's more for cpufreq).  Drivers may reparent to get
 * a better rate match; we don't.
 */

long clk_round_rate(struct clk *clk, unsigned long rate)
{
	unsigned long	flags;
	unsigned	prescale;
	unsigned long	actual;

	if (!clk_is_programmable(clk))
		return -EINVAL;
	spin_lock_irqsave(&clk_lock, flags);

	actual = clk->parent->rate_hz;
	for (prescale = 0; prescale < 7; prescale++) {
		if (actual && actual <= rate)
			break;
		actual >>= 1;
	}

	spin_unlock_irqrestore(&clk_lock, flags);
	return (prescale < 7) ? actual : -ENOENT;
}
EXPORT_SYMBOL(clk_round_rate);

int clk_set_rate(struct clk *clk, unsigned long rate)
{
	unsigned long	flags;
	unsigned	prescale;
	unsigned long	actual;

	if (!clk_is_programmable(clk))
		return -EINVAL;
	if (clk->users)
		return -EBUSY;
	spin_lock_irqsave(&clk_lock, flags);

	actual = clk->parent->rate_hz;
	for (prescale = 0; prescale < 7; prescale++) {
		if (actual && actual <= rate) {
			u32	pckr;

			pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
			pckr &= AT91_PMC_CSS_PLLB;	/* clock selection */
			pckr |= prescale << 2;
			at91_sys_write(AT91_PMC_PCKR(clk->id), pckr);
			clk->rate_hz = actual;
			break;
		}
		actual >>= 1;
	}

	spin_unlock_irqrestore(&clk_lock, flags);
	return (prescale < 7) ? actual : -ENOENT;
}
EXPORT_SYMBOL(clk_set_rate);

struct clk *clk_get_parent(struct clk *clk)
{
	return clk->parent;
}
EXPORT_SYMBOL(clk_get_parent);

int clk_set_parent(struct clk *clk, struct clk *parent)
{
	unsigned long	flags;

	if (clk->users)
		return -EBUSY;
	if (!clk_is_primary(parent) || !clk_is_programmable(clk))
		return -EINVAL;
	spin_lock_irqsave(&clk_lock, flags);

	clk->rate_hz = parent->rate_hz;
	clk->parent = parent;
	at91_sys_write(AT91_PMC_PCKR(clk->id), parent->id);

	spin_unlock_irqrestore(&clk_lock, flags);
	return 0;
}
EXPORT_SYMBOL(clk_set_parent);

/* establish PCK0..PCK3 parentage and rate */
static void __init init_programmable_clock(struct clk *clk)
{
	struct clk	*parent;
	u32		pckr;

	pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
	parent = at91_css_to_clk(pckr & AT91_PMC_CSS);
	clk->parent = parent;
	clk->rate_hz = parent->rate_hz / (1 << ((pckr & AT91_PMC_PRES) >> 2));
}

#endif	/* CONFIG_AT91_PROGRAMMABLE_CLOCKS */

/*------------------------------------------------------------------------*/

#ifdef CONFIG_DEBUG_FS

static int at91_clk_show(struct seq_file *s, void *unused)
{
	u32		scsr, pcsr, uckr = 0, sr;
	struct clk	*clk;

	seq_printf(s, "SCSR = %8x\n", scsr = at91_sys_read(AT91_PMC_SCSR));
	seq_printf(s, "PCSR = %8x\n", pcsr = at91_sys_read(AT91_PMC_PCSR));
	seq_printf(s, "MOR  = %8x\n", at91_sys_read(AT91_CKGR_MOR));
	seq_printf(s, "MCFR = %8x\n", at91_sys_read(AT91_CKGR_MCFR));
	seq_printf(s, "PLLA = %8x\n", at91_sys_read(AT91_CKGR_PLLAR));
	if (!cpu_is_at91sam9rl())
		seq_printf(s, "PLLB = %8x\n", at91_sys_read(AT91_CKGR_PLLBR));
	if (cpu_is_at91cap9() || cpu_is_at91sam9rl())
		seq_printf(s, "UCKR = %8x\n", uckr = at91_sys_read(AT91_CKGR_UCKR));
	seq_printf(s, "MCKR = %8x\n", at91_sys_read(AT91_PMC_MCKR));
	seq_printf(s, "SR   = %8x\n", sr = at91_sys_read(AT91_PMC_SR));

	seq_printf(s, "\n");

	list_for_each_entry(clk, &clocks, node) {
		char	*state;

		if (clk->mode == pmc_sys_mode)
			state = (scsr & clk->pmc_mask) ? "on" : "off";
		else if (clk->mode == pmc_periph_mode)
			state = (pcsr & clk->pmc_mask) ? "on" : "off";
		else if (clk->mode == pmc_uckr_mode)
			state = (uckr & clk->pmc_mask) ? "on" : "off";
		else if (clk->pmc_mask)
			state = (sr & clk->pmc_mask) ? "on" : "off";
		else if (clk == &clk32k || clk == &main_clk)
			state = "on";
		else
			state = "";

		seq_printf(s, "%-10s users=%2d %-3s %9ld Hz %s\n",
			clk->name, clk->users, state, clk_get_rate(clk),
			clk->parent ? clk->parent->name : "");
	}
	return 0;
}

static int at91_clk_open(struct inode *inode, struct file *file)
{
	return single_open(file, at91_clk_show, NULL);
}

static const struct file_operations at91_clk_operations = {
	.open		= at91_clk_open,
	.read		= seq_read,
	.llseek		= seq_lseek,
	.release	= single_release,
};

static int __init at91_clk_debugfs_init(void)
{
	/* /sys/kernel/debug/at91_clk */
	(void) debugfs_create_file("at91_clk", S_IFREG | S_IRUGO, NULL, NULL, &at91_clk_operations);

	return 0;
}
postcore_initcall(at91_clk_debugfs_init);

#endif

/*------------------------------------------------------------------------*/

/* Register a new clock */
int __init clk_register(struct clk *clk)
{
	if (clk_is_peripheral(clk)) {
		clk->parent = &mck;
		clk->mode = pmc_periph_mode;
		list_add_tail(&clk->node, &clocks);
	}
	else if (clk_is_sys(clk)) {
		clk->parent = &mck;
		clk->mode = pmc_sys_mode;

		list_add_tail(&clk->node, &clocks);
	}
#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
	else if (clk_is_programmable(clk)) {
		clk->mode = pmc_sys_mode;
		init_programmable_clock(clk);
		list_add_tail(&clk->node, &clocks);
	}
#endif

	return 0;
}


/*------------------------------------------------------------------------*/

static u32 __init at91_pll_rate(struct clk *pll, u32 freq, u32 reg)
{
	unsigned mul, div;

	div = reg & 0xff;
	mul = (reg >> 16) & 0x7ff;
	if (div && mul) {
		freq /= div;
		freq *= mul + 1;
	} else
		freq = 0;

	return freq;
}

static u32 __init at91_usb_rate(struct clk *pll, u32 freq, u32 reg)
{
	if (pll == &pllb && (reg & AT91_PMC_USB96M))
		return freq / 2;
	else
		return freq;
}

static unsigned __init at91_pll_calc(unsigned main_freq, unsigned out_freq)
{
	unsigned i, div = 0, mul = 0, diff = 1 << 30;
	unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;

	/* PLL output max 240 MHz (or 180 MHz per errata) */
	if (out_freq > 240000000)
		goto fail;

	for (i = 1; i < 256; i++) {
		int diff1;
		unsigned input, mul1;

		/*
		 * PLL input between 1MHz and 32MHz per spec, but lower
		 * frequences seem necessary in some cases so allow 100K.
		 * Warning: some newer products need 2MHz min.
		 */
		input = main_freq / i;
		if (cpu_is_at91sam9g20() && input < 2000000)
			continue;
		if (input < 100000)
			continue;
		if (input > 32000000)
			continue;

		mul1 = out_freq / input;
		if (cpu_is_at91sam9g20() && mul > 63)
			continue;
		if (mul1 > 2048)
			continue;
		if (mul1 < 2)
			goto fail;

		diff1 = out_freq - input * mul1;
		if (diff1 < 0)
			diff1 = -diff1;
		if (diff > diff1) {
			diff = diff1;
			div = i;
			mul = mul1;
			if (diff == 0)
				break;
		}
	}
	if (i == 256 && diff > (out_freq >> 5))
		goto fail;
	return ret | ((mul - 1) << 16) | div;
fail:
	return 0;
}

static struct clk *const standard_pmc_clocks[] __initdata = {
	/* four primary clocks */
	&clk32k,
	&main_clk,
	&plla,
	&pllb,

	/* PLLB children (USB) */
	&udpck,
	&uhpck,

	/* MCK */
	&mck
};

int __init at91_clock_init(unsigned long main_clock)
{
	unsigned tmp, freq, mckr;
	int i;

	/*
	 * When the bootloader initialized the main oscillator correctly,
	 * there's no problem using the cycle counter.  But if it didn't,
	 * or when using oscillator bypass mode, we must be told the speed
	 * of the main clock.
	 */
	if (!main_clock) {
		do {
			tmp = at91_sys_read(AT91_CKGR_MCFR);
		} while (!(tmp & AT91_PMC_MAINRDY));
		main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16);
	}
	main_clk.rate_hz = main_clock;

	/* report if PLLA is more than mildly overclocked */
	plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR));
	if ((!cpu_is_at91sam9g20() && plla.rate_hz > 209000000)
	   || (cpu_is_at91sam9g20() && plla.rate_hz > 800000000))
		pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);

	/*
	 * USB clock init:  choose 48 MHz PLLB value,
	 * disable 48MHz clock during usb peripheral suspend.
	 *
	 * REVISIT:  assumes MCK doesn't derive from PLLB!
	 */
	at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M;
	pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
	if (cpu_is_at91rm9200()) {
		uhpck.pmc_mask = AT91RM9200_PMC_UHP;
		udpck.pmc_mask = AT91RM9200_PMC_UDP;
		at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
	} else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || cpu_is_at91sam9263() || cpu_is_at91sam9g20()) {
		uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
		udpck.pmc_mask = AT91SAM926x_PMC_UDP;
	} else if (cpu_is_at91cap9()) {
		uhpck.pmc_mask = AT91CAP9_PMC_UHP;
	}
	at91_sys_write(AT91_CKGR_PLLBR, 0);

	udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
	uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);

	/*
	 * USB HS clock init
	 */
	if (cpu_is_at91cap9() || cpu_is_at91sam9rl()) {
		/*
		 * multiplier is hard-wired to 40
		 * (obtain the USB High Speed 480 MHz when input is 12 MHz)
		 */
		utmi_clk.rate_hz = 40 * utmi_clk.parent->rate_hz;
	}

	/*
	 * MCK and CPU derive from one of those primary clocks.
	 * For now, assume this parentage won't change.
	 */
	mckr = at91_sys_read(AT91_PMC_MCKR);
	mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS);
	freq = mck.parent->rate_hz;
	freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2));				/* prescale */
	if (cpu_is_at91rm9200())
		mck.rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8));	/* mdiv */
	else if (cpu_is_at91sam9g20()) {
		mck.rate_hz = (mckr & AT91_PMC_MDIV) ?
			freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq;	/* mdiv ; (x >> 7) = ((x >> 8) * 2) */
		if (mckr & AT91_PMC_PDIV)
			freq /= 2;		/* processor clock division */
	} else
		mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8));      /* mdiv */

	/* Register the PMC's standard clocks */
	for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
		list_add_tail(&standard_pmc_clocks[i]->node, &clocks);

	if (cpu_is_at91cap9() || cpu_is_at91sam9rl())
		list_add_tail(&utmi_clk.node, &clocks);

	/* MCK and CPU clock are "always on" */
	clk_enable(&mck);

	printk("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n",
		freq / 1000000, (unsigned) mck.rate_hz / 1000000,
		(unsigned) main_clock / 1000000,
		((unsigned) main_clock % 1000000) / 1000);

	return 0;
}

/*
 * Several unused clocks may be active.  Turn them off.
 */
static int __init at91_clock_reset(void)
{
	unsigned long pcdr = 0;
	unsigned long scdr = 0;
	struct clk *clk;

	list_for_each_entry(clk, &clocks, node) {
		if (clk->users > 0)
			continue;

		if (clk->mode == pmc_periph_mode)
			pcdr |= clk->pmc_mask;

		if (clk->mode == pmc_sys_mode)
			scdr |= clk->pmc_mask;

		pr_debug("Clocks: disable unused %s\n", clk->name);
	}

	at91_sys_write(AT91_PMC_PCDR, pcdr);
	at91_sys_write(AT91_PMC_SCDR, scdr);

	return 0;
}
late_initcall(at91_clock_reset);
Commit	Line	Data
73a59c1c	1	/*
9d041268	2	* linux/arch/arm/mach-at91/clock.c
73a59c1c SP	3	*
	4	* Copyright (C) 2005 David Brownell
	5	* Copyright (C) 2005 Ivan Kokshaysky
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*/
	12
	13	#include <linux/module.h>
	14	#include <linux/kernel.h>
	15	#include <linux/init.h>
	16	#include <linux/fs.h>
	17	#include <linux/debugfs.h>
	18	#include <linux/seq_file.h>
	19	#include <linux/list.h>
	20	#include <linux/errno.h>
	21	#include <linux/err.h>
	22	#include <linux/spinlock.h>
	23	#include <linux/delay.h>
	24	#include <linux/clk.h>
fced80c7	25	#include <linux/io.h>
73a59c1c	26
a09e64fb RK	27	#include <mach/hardware.h>
	28	#include <mach/at91_pmc.h>
	29	#include <mach/cpu.h>
73a59c1c	30
2eeaaa21	31	#include "clock.h"
73a59c1c	32
55c20c0a	33
73a59c1c SP	34	/*
	35	* There's a lot more which can be done with clocks, including cpufreq
	36	* integration, slow clock mode support (for system suspend), letting
	37	* PLLB be used at other rates (on boards that don't need USB), etc.
	38	*/
	39
2eeaaa21 AV	40	#define clk_is_primary(x) ((x)->type & CLK_TYPE_PRIMARY)
	41	#define clk_is_programmable(x) ((x)->type & CLK_TYPE_PROGRAMMABLE)
	42	#define clk_is_peripheral(x) ((x)->type & CLK_TYPE_PERIPHERAL)
d481f864	43	#define clk_is_sys(x) ((x)->type & CLK_TYPE_SYSTEM)
2eeaaa21 AV	44
	45
	46	static LIST_HEAD(clocks);
	47	static DEFINE_SPINLOCK(clk_lock);
73a59c1c	48
2eeaaa21	49	static u32 at91_pllb_usb_init;
73a59c1c SP	50
	51	/*
	52	* Four primary clock sources: two crystal oscillators (32K, main), and
	53	* two PLLs. PLLA usually runs the master clock; and PLLB must run at
	54	* 48 MHz (unless no USB function clocks are needed). The main clock and
	55	* both PLLs are turned off to run in "slow clock mode" (system suspend).
	56	*/
	57	static struct clk clk32k = {
	58	.name = "clk32k",
	59	.rate_hz = AT91_SLOW_CLOCK,
	60	.users = 1, /* always on */
	61	.id = 0,
2eeaaa21	62	.type = CLK_TYPE_PRIMARY,
73a59c1c SP	63	};
	64	static struct clk main_clk = {
	65	.name = "main",
91f8ed83	66	.pmc_mask = AT91_PMC_MOSCS, /* in PMC_SR */
73a59c1c	67	.id = 1,
2eeaaa21	68	.type = CLK_TYPE_PRIMARY,
73a59c1c SP	69	};
	70	static struct clk plla = {
	71	.name = "plla",
	72	.parent = &main_clk,
91f8ed83	73	.pmc_mask = AT91_PMC_LOCKA, /* in PMC_SR */
73a59c1c	74	.id = 2,
2eeaaa21	75	.type = CLK_TYPE_PRIMARY \| CLK_TYPE_PLL,
73a59c1c SP	76	};
	77
	78	static void pllb_mode(struct clk *clk, int is_on)
	79	{
	80	u32 value;
	81
	82	if (is_on) {
	83	is_on = AT91_PMC_LOCKB;
	84	value = at91_pllb_usb_init;
	85	} else
	86	value = 0;
	87
2eeaaa21	88	// REVISIT: Add work-around for AT91RM9200 Errata #26 ?
73a59c1c SP	89	at91_sys_write(AT91_CKGR_PLLBR, value);
	90
	91	do {
	92	cpu_relax();
	93	} while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != is_on);
	94	}
	95
	96	static struct clk pllb = {
	97	.name = "pllb",
	98	.parent = &main_clk,
91f8ed83	99	.pmc_mask = AT91_PMC_LOCKB, /* in PMC_SR */
73a59c1c SP	100	.mode = pllb_mode,
73a59c1c SP	101	.id = 3,
2eeaaa21	102	.type = CLK_TYPE_PRIMARY \| CLK_TYPE_PLL,
73a59c1c SP	103	};
	104
	105	static void pmc_sys_mode(struct clk *clk, int is_on)
	106	{
	107	if (is_on)
	108	at91_sys_write(AT91_PMC_SCER, clk->pmc_mask);
	109	else
	110	at91_sys_write(AT91_PMC_SCDR, clk->pmc_mask);
	111	}
	112
53d71680 SP	113	static void pmc_uckr_mode(struct clk *clk, int is_on)
	114	{
	115	unsigned int uckr = at91_sys_read(AT91_CKGR_UCKR);
	116
	117	if (is_on) {
	118	is_on = AT91_PMC_LOCKU;
	119	at91_sys_write(AT91_CKGR_UCKR, uckr \| clk->pmc_mask);
	120	} else
	121	at91_sys_write(AT91_CKGR_UCKR, uckr & ~(clk->pmc_mask));
	122
	123	do {
	124	cpu_relax();
	125	} while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKU) != is_on);
	126	}
	127
73a59c1c SP	128	/* USB function clocks (PLLB must be 48 MHz) */
	129	static struct clk udpck = {
	130	.name = "udpck",
	131	.parent = &pllb,
73a59c1c SP	132	.mode = pmc_sys_mode,
73a59c1c SP	133	};
53d71680 SP	134	static struct clk utmi_clk = {
	135	.name = "utmi_clk",
	136	.parent = &main_clk,
	137	.pmc_mask = AT91_PMC_UPLLEN, /* in CKGR_UCKR */
	138	.mode = pmc_uckr_mode,
	139	.type = CLK_TYPE_PLL,
	140	};
73a59c1c SP	141	static struct clk uhpck = {
	142	.name = "uhpck",
	143	.parent = &pllb,
73a59c1c SP	144	.mode = pmc_sys_mode,
	145	};
	146
73a59c1c SP	147
	148	/*
	149	* The master clock is divided from the CPU clock (by 1-4). It's used for
	150	* memory, interfaces to on-chip peripherals, the AIC, and sometimes more
	151	* (e.g baud rate generation). It's sourced from one of the primary clocks.
	152	*/
	153	static struct clk mck = {
	154	.name = "mck",
91f8ed83	155	.pmc_mask = AT91_PMC_MCKRDY, /* in PMC_SR */
73a59c1c SP	156	};
	157
	158	static void pmc_periph_mode(struct clk *clk, int is_on)
	159	{
	160	if (is_on)
	161	at91_sys_write(AT91_PMC_PCER, clk->pmc_mask);
	162	else
	163	at91_sys_write(AT91_PMC_PCDR, clk->pmc_mask);
	164	}
	165
2eeaaa21 AV	166	static struct clk __init *at91_css_to_clk(unsigned long css)
	167	{
	168	switch (css) {
	169	case AT91_PMC_CSS_SLOW:
	170	return &clk32k;
	171	case AT91_PMC_CSS_MAIN:
	172	return &main_clk;
	173	case AT91_PMC_CSS_PLLA:
	174	return &plla;
	175	case AT91_PMC_CSS_PLLB:
	176	return &pllb;
	177	}
73a59c1c	178
2eeaaa21 AV	179	return NULL;
2eeaaa21 AV	180	}
73a59c1c	181
91f8ed83 AV	182	/*
	183	* Associate a particular clock with a function (eg, "uart") and device.
	184	* The drivers can then request the same 'function' with several different
	185	* devices and not care about which clock name to use.
	186	*/
	187	void __init at91_clock_associate(const char id, struct device dev, const char *func)
	188	{
	189	struct clk *clk = clk_get(NULL, id);
	190
	191	if (!dev \|\| !clk \|\| !IS_ERR(clk_get(dev, func)))
	192	return;
	193
	194	clk->function = func;
	195	clk->dev = dev;
	196	}
	197
2eeaaa21	198	/* clocks cannot be de-registered no refcounting necessary */
73a59c1c SP	199	struct clk clk_get(struct device dev, const char *id)
73a59c1c SP	200	{
2eeaaa21	201	struct clk *clk;
91f8ed83	202
2eeaaa21	203	list_for_each_entry(clk, &clocks, node) {
91f8ed83 AV	204	if (strcmp(id, clk->name) == 0)
	205	return clk;
	206	if (clk->function && (dev == clk->dev) && strcmp(id, clk->function) == 0)
	207	return clk;
73a59c1c SP	208	}
	209
	210	return ERR_PTR(-ENOENT);
	211	}
	212	EXPORT_SYMBOL(clk_get);
	213
	214	void clk_put(struct clk *clk)
	215	{
	216	}
	217	EXPORT_SYMBOL(clk_put);
	218
	219	static void __clk_enable(struct clk *clk)
	220	{
	221	if (clk->parent)
	222	__clk_enable(clk->parent);
	223	if (clk->users++ == 0 && clk->mode)
	224	clk->mode(clk, 1);
	225	}
	226
	227	int clk_enable(struct clk *clk)
	228	{
	229	unsigned long flags;
	230
	231	spin_lock_irqsave(&clk_lock, flags);
	232	__clk_enable(clk);
	233	spin_unlock_irqrestore(&clk_lock, flags);
	234	return 0;
	235	}
	236	EXPORT_SYMBOL(clk_enable);
	237
	238	static void __clk_disable(struct clk *clk)
	239	{
	240	BUG_ON(clk->users == 0);
	241	if (--clk->users == 0 && clk->mode)
	242	clk->mode(clk, 0);
	243	if (clk->parent)
	244	__clk_disable(clk->parent);
	245	}
	246
	247	void clk_disable(struct clk *clk)
	248	{
	249	unsigned long flags;
	250
	251	spin_lock_irqsave(&clk_lock, flags);
	252	__clk_disable(clk);
	253	spin_unlock_irqrestore(&clk_lock, flags);
	254	}
	255	EXPORT_SYMBOL(clk_disable);
	256
	257	unsigned long clk_get_rate(struct clk *clk)
	258	{
	259	unsigned long flags;
	260	unsigned long rate;
	261
	262	spin_lock_irqsave(&clk_lock, flags);
	263	for (;;) {
	264	rate = clk->rate_hz;
	265	if (rate \|\| !clk->parent)
	266	break;
	267	clk = clk->parent;
	268	}
	269	spin_unlock_irqrestore(&clk_lock, flags);
	270	return rate;
	271	}
272	EXPORT_SYMBOL(clk_get_rate);
273
274	/------------------------------------------------------------------------/
275
276	#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
277
278	/*
279	* For now, only the programmable clocks support reparenting (MCK could
280	* do this too, with care) or rate changing (the PLLs could do this too,
281	* ditto MCK but that's more for cpufreq). Drivers may reparent to get
282	* a better rate match; we don't.
283	*/
284
285	long clk_round_rate(struct clk *clk, unsigned long rate)
286	{
287	unsigned long flags;
288	unsigned prescale;
289	unsigned long actual;
290
2eeaaa21	291	if (!clk_is_programmable(clk))
73a59c1c SP	292	return -EINVAL;
	293	spin_lock_irqsave(&clk_lock, flags);
	294
	295	actual = clk->parent->rate_hz;
	296	for (prescale = 0; prescale < 7; prescale++) {
	297	if (actual && actual <= rate)
	298	break;
	299	actual >>= 1;
	300	}
	301
	302	spin_unlock_irqrestore(&clk_lock, flags);
	303	return (prescale < 7) ? actual : -ENOENT;
	304	}
	305	EXPORT_SYMBOL(clk_round_rate);
	306
	307	int clk_set_rate(struct clk *clk, unsigned long rate)
	308	{
	309	unsigned long flags;
	310	unsigned prescale;
	311	unsigned long actual;
	312
2eeaaa21	313	if (!clk_is_programmable(clk))
73a59c1c SP	314	return -EINVAL;
	315	if (clk->users)
	316	return -EBUSY;
	317	spin_lock_irqsave(&clk_lock, flags);
	318
	319	actual = clk->parent->rate_hz;
	320	for (prescale = 0; prescale < 7; prescale++) {
	321	if (actual && actual <= rate) {
	322	u32 pckr;
	323
	324	pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
69b648a2	325	pckr &= AT91_PMC_CSS_PLLB; /* clock selection */
73a59c1c SP	326	pckr \|= prescale << 2;
	327	at91_sys_write(AT91_PMC_PCKR(clk->id), pckr);
	328	clk->rate_hz = actual;
	329	break;
	330	}
	331	actual >>= 1;
	332	}
	333
	334	spin_unlock_irqrestore(&clk_lock, flags);
	335	return (prescale < 7) ? actual : -ENOENT;
	336	}
	337	EXPORT_SYMBOL(clk_set_rate);
	338
	339	struct clk clk_get_parent(struct clk clk)
	340	{
	341	return clk->parent;
	342	}
	343	EXPORT_SYMBOL(clk_get_parent);
	344
	345	int clk_set_parent(struct clk clk, struct clk parent)
	346	{
	347	unsigned long flags;
	348
	349	if (clk->users)
	350	return -EBUSY;
2eeaaa21	351	if (!clk_is_primary(parent) \|\| !clk_is_programmable(clk))
73a59c1c SP	352	return -EINVAL;
	353	spin_lock_irqsave(&clk_lock, flags);
	354
	355	clk->rate_hz = parent->rate_hz;
	356	clk->parent = parent;
	357	at91_sys_write(AT91_PMC_PCKR(clk->id), parent->id);
	358
	359	spin_unlock_irqrestore(&clk_lock, flags);
	360	return 0;
	361	}
	362	EXPORT_SYMBOL(clk_set_parent);
	363
2eeaaa21	364	/* establish PCK0..PCK3 parentage and rate */
72e7ae81	365	static void __init init_programmable_clock(struct clk *clk)
2eeaaa21 AV	366	{
	367	struct clk *parent;
	368	u32 pckr;
	369
	370	pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
	371	parent = at91_css_to_clk(pckr & AT91_PMC_CSS);
	372	clk->parent = parent;
a95c729b	373	clk->rate_hz = parent->rate_hz / (1 << ((pckr & AT91_PMC_PRES) >> 2));
2eeaaa21 AV	374	}
2eeaaa21 AV	375
73a59c1c SP	376	#endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
	377
	378	/------------------------------------------------------------------------/
	379
	380	#ifdef CONFIG_DEBUG_FS
	381
	382	static int at91_clk_show(struct seq_file s, void unused)
	383	{
53d71680	384	u32 scsr, pcsr, uckr = 0, sr;
2eeaaa21	385	struct clk *clk;
73a59c1c SP	386
	387	seq_printf(s, "SCSR = %8x\n", scsr = at91_sys_read(AT91_PMC_SCSR));
	388	seq_printf(s, "PCSR = %8x\n", pcsr = at91_sys_read(AT91_PMC_PCSR));
73a59c1c SP	389	seq_printf(s, "MOR = %8x\n", at91_sys_read(AT91_CKGR_MOR));
	390	seq_printf(s, "MCFR = %8x\n", at91_sys_read(AT91_CKGR_MCFR));
	391	seq_printf(s, "PLLA = %8x\n", at91_sys_read(AT91_CKGR_PLLAR));
ba45ca43 NF	392	if (!cpu_is_at91sam9rl())
	393	seq_printf(s, "PLLB = %8x\n", at91_sys_read(AT91_CKGR_PLLBR));
	394	if (cpu_is_at91cap9() \|\| cpu_is_at91sam9rl())
53d71680	395	seq_printf(s, "UCKR = %8x\n", uckr = at91_sys_read(AT91_CKGR_UCKR));
73a59c1c	396	seq_printf(s, "MCKR = %8x\n", at91_sys_read(AT91_PMC_MCKR));
73a59c1c SP	397	seq_printf(s, "SR = %8x\n", sr = at91_sys_read(AT91_PMC_SR));
	398
	399	seq_printf(s, "\n");
	400
2eeaaa21 AV	401	list_for_each_entry(clk, &clocks, node) {
2eeaaa21 AV	402	char *state;
73a59c1c SP	403
	404	if (clk->mode == pmc_sys_mode)
	405	state = (scsr & clk->pmc_mask) ? "on" : "off";
	406	else if (clk->mode == pmc_periph_mode)
	407	state = (pcsr & clk->pmc_mask) ? "on" : "off";
53d71680 SP	408	else if (clk->mode == pmc_uckr_mode)
53d71680 SP	409	state = (uckr & clk->pmc_mask) ? "on" : "off";
73a59c1c SP	410	else if (clk->pmc_mask)
	411	state = (sr & clk->pmc_mask) ? "on" : "off";
	412	else if (clk == &clk32k \|\| clk == &main_clk)
	413	state = "on";
	414	else
	415	state = "";
	416
69b648a2	417	seq_printf(s, "%-10s users=%2d %-3s %9ld Hz %s\n",
73a59c1c SP	418	clk->name, clk->users, state, clk_get_rate(clk),
	419	clk->parent ? clk->parent->name : "");
	420	}
	421	return 0;
	422	}
	423
	424	static int at91_clk_open(struct inode inode, struct file file)
	425	{
	426	return single_open(file, at91_clk_show, NULL);
	427	}
	428
5dfe4c96	429	static const struct file_operations at91_clk_operations = {
73a59c1c SP	430	.open = at91_clk_open,
	431	.read = seq_read,
	432	.llseek = seq_lseek,
	433	.release = single_release,
	434	};
	435
	436	static int __init at91_clk_debugfs_init(void)
	437	{
	438	/* /sys/kernel/debug/at91_clk */
	439	(void) debugfs_create_file("at91_clk", S_IFREG \| S_IRUGO, NULL, NULL, &at91_clk_operations);
	440
	441	return 0;
	442	}
	443	postcore_initcall(at91_clk_debugfs_init);
	444
	445	#endif
	446
2eeaaa21 AV	447	/------------------------------------------------------------------------/
	448
	449	/* Register a new clock */
	450	int __init clk_register(struct clk *clk)
	451	{
	452	if (clk_is_peripheral(clk)) {
	453	clk->parent = &mck;
	454	clk->mode = pmc_periph_mode;
	455	list_add_tail(&clk->node, &clocks);
	456	}
d481f864 AV	457	else if (clk_is_sys(clk)) {
	458	clk->parent = &mck;
	459	clk->mode = pmc_sys_mode;
	460
	461	list_add_tail(&clk->node, &clocks);
	462	}
2eeaaa21 AV	463	#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
	464	else if (clk_is_programmable(clk)) {
	465	clk->mode = pmc_sys_mode;
	466	init_programmable_clock(clk);
	467	list_add_tail(&clk->node, &clocks);
	468	}
	469	#endif
	470
	471	return 0;
	472	}
	473
	474
73a59c1c SP	475	/------------------------------------------------------------------------/
	476
	477	static u32 __init at91_pll_rate(struct clk *pll, u32 freq, u32 reg)
	478	{
	479	unsigned mul, div;
	480
	481	div = reg & 0xff;
	482	mul = (reg >> 16) & 0x7ff;
	483	if (div && mul) {
	484	freq /= div;
	485	freq *= mul + 1;
	486	} else
	487	freq = 0;
69b648a2	488
73a59c1c SP	489	return freq;
	490	}
	491
69b648a2 AV	492	static u32 __init at91_usb_rate(struct clk *pll, u32 freq, u32 reg)
	493	{
	494	if (pll == &pllb && (reg & AT91_PMC_USB96M))
	495	return freq / 2;
	496	else
	497	return freq;
	498	}
	499
73a59c1c SP	500	static unsigned __init at91_pll_calc(unsigned main_freq, unsigned out_freq)
	501	{
	502	unsigned i, div = 0, mul = 0, diff = 1 << 30;
	503	unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
	504
	505	/* PLL output max 240 MHz (or 180 MHz per errata) */
	506	if (out_freq > 240000000)
	507	goto fail;
	508
	509	for (i = 1; i < 256; i++) {
	510	int diff1;
	511	unsigned input, mul1;
	512
	513	/*
	514	* PLL input between 1MHz and 32MHz per spec, but lower
	515	* frequences seem necessary in some cases so allow 100K.
61352667	516	* Warning: some newer products need 2MHz min.
73a59c1c SP	517	*/
73a59c1c SP	518	input = main_freq / i;
61352667	519	if (cpu_is_at91sam9g20() && input < 2000000)
61352667	520	continue;
73a59c1c SP	521	if (input < 100000)
	522	continue;
	523	if (input > 32000000)
	524	continue;
	525
	526	mul1 = out_freq / input;
61352667	527	if (cpu_is_at91sam9g20() && mul > 63)
61352667	528	continue;
73a59c1c SP	529	if (mul1 > 2048)
	530	continue;
	531	if (mul1 < 2)
	532	goto fail;
	533
	534	diff1 = out_freq - input * mul1;
	535	if (diff1 < 0)
	536	diff1 = -diff1;
	537	if (diff > diff1) {
	538	diff = diff1;
	539	div = i;
	540	mul = mul1;
	541	if (diff == 0)
	542	break;
	543	}
	544	}
	545	if (i == 256 && diff > (out_freq >> 5))
	546	goto fail;
	547	return ret \| ((mul - 1) << 16) \| div;
	548	fail:
	549	return 0;
	550	}
	551
2eeaaa21 AV	552	static struct clk *const standard_pmc_clocks[] __initdata = {
	553	/* four primary clocks */
	554	&clk32k,
	555	&main_clk,
	556	&plla,
	557	&pllb,
	558
	559	/* PLLB children (USB) */
	560	&udpck,
	561	&uhpck,
	562
	563	/* MCK */
	564	&mck
	565	};
	566
73a59c1c SP	567	int __init at91_clock_init(unsigned long main_clock)
	568	{
	569	unsigned tmp, freq, mckr;
2eeaaa21	570	int i;
73a59c1c SP	571
	572	/*
	573	* When the bootloader initialized the main oscillator correctly,
	574	* there's no problem using the cycle counter. But if it didn't,
	575	* or when using oscillator bypass mode, we must be told the speed
	576	* of the main clock.
	577	*/
	578	if (!main_clock) {
	579	do {
	580	tmp = at91_sys_read(AT91_CKGR_MCFR);
69b648a2 AV	581	} while (!(tmp & AT91_PMC_MAINRDY));
69b648a2 AV	582	main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16);
73a59c1c SP	583	}
	584	main_clk.rate_hz = main_clock;
	585
	586	/* report if PLLA is more than mildly overclocked */
	587	plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR));
61352667	588	if ((!cpu_is_at91sam9g20() && plla.rate_hz > 209000000)
61352667	589	\|\| (cpu_is_at91sam9g20() && plla.rate_hz > 800000000))
73a59c1c SP	590	pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
	591
	592	/*
c9b75d13	593	* USB clock init: choose 48 MHz PLLB value,
73a59c1c SP	594	* disable 48MHz clock during usb peripheral suspend.
	595	*
	596	* REVISIT: assumes MCK doesn't derive from PLLB!
	597	*/
69b648a2	598	at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) \| AT91_PMC_USB96M;
73a59c1c	599	pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
d481f864 AV	600	if (cpu_is_at91rm9200()) {
	601	uhpck.pmc_mask = AT91RM9200_PMC_UHP;
	602	udpck.pmc_mask = AT91RM9200_PMC_UDP;
d481f864	603	at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
61352667	604	} else if (cpu_is_at91sam9260() \|\| cpu_is_at91sam9261() \|\| cpu_is_at91sam9263() \|\| cpu_is_at91sam9g20()) {
d481f864 AV	605	uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
d481f864 AV	606	udpck.pmc_mask = AT91SAM926x_PMC_UDP;
2b3b3516 AV	607	} else if (cpu_is_at91cap9()) {
2b3b3516 AV	608	uhpck.pmc_mask = AT91CAP9_PMC_UHP;
d481f864	609	}
73a59c1c	610	at91_sys_write(AT91_CKGR_PLLBR, 0);
73a59c1c	611
69b648a2 AV	612	udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
	613	uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
	614
53d71680 SP	615	/*
	616	* USB HS clock init
	617	*/
ba45ca43	618	if (cpu_is_at91cap9() \|\| cpu_is_at91sam9rl()) {
53d71680 SP	619	/*
	620	* multiplier is hard-wired to 40
	621	* (obtain the USB High Speed 480 MHz when input is 12 MHz)
	622	*/
	623	utmi_clk.rate_hz = 40 * utmi_clk.parent->rate_hz;
	624	}
	625
73a59c1c SP	626	/*
	627	* MCK and CPU derive from one of those primary clocks.
	628	* For now, assume this parentage won't change.
	629	*/
	630	mckr = at91_sys_read(AT91_PMC_MCKR);
2eeaaa21	631	mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS);
73a59c1c	632	freq = mck.parent->rate_hz;
a95c729b AV	633	freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2)); /* prescale */
	634	if (cpu_is_at91rm9200())
	635	mck.rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
61352667	636	else if (cpu_is_at91sam9g20()) {
	637	mck.rate_hz = (mckr & AT91_PMC_MDIV) ?
	638	freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq; /* mdiv ; (x >> 7) = ((x >> 8) * 2) */
	639	if (mckr & AT91_PMC_PDIV)
	640	freq /= 2; /* processor clock division */
	641	} else
	642	mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
73a59c1c	643
2eeaaa21 AV	644	/* Register the PMC's standard clocks */
	645	for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
	646	list_add_tail(&standard_pmc_clocks[i]->node, &clocks);
	647
ba45ca43	648	if (cpu_is_at91cap9() \|\| cpu_is_at91sam9rl())
53d71680 SP	649	list_add_tail(&utmi_clk.node, &clocks);
53d71680 SP	650
91f8ed83 AV	651	/* MCK and CPU clock are "always on" */
	652	clk_enable(&mck);
	653
73a59c1c SP	654	printk("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n",
	655	freq / 1000000, (unsigned) mck.rate_hz / 1000000,
	656	(unsigned) main_clock / 1000000,
	657	((unsigned) main_clock % 1000000) / 1000);
	658
c9b75d13 AV	659	return 0;
	660	}
	661
	662	/*
	663	* Several unused clocks may be active. Turn them off.
	664	*/
	665	static int __init at91_clock_reset(void)
	666	{
	667	unsigned long pcdr = 0;
	668	unsigned long scdr = 0;
	669	struct clk *clk;
	670
	671	list_for_each_entry(clk, &clocks, node) {
	672	if (clk->users > 0)
	673	continue;
	674
	675	if (clk->mode == pmc_periph_mode)
	676	pcdr \|= clk->pmc_mask;
	677
	678	if (clk->mode == pmc_sys_mode)
	679	scdr \|= clk->pmc_mask;
	680
	681	pr_debug("Clocks: disable unused %s\n", clk->name);
	682	}
91f8ed83	683
c9b75d13 AV	684	at91_sys_write(AT91_PMC_PCDR, pcdr);
c9b75d13 AV	685	at91_sys_write(AT91_PMC_SCDR, scdr);
73a59c1c SP	686
	687	return 0;
	688	}
c9b75d13	689	late_initcall(at91_clock_reset);