Commit | Line | Data |
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79da7a61 | 1 | /* |
a09e64fb | 2 | * arch/arm/mach-at91/include/mach/cpu.h |
79da7a61 | 3 | * |
8c3583b6 JCPV |
4 | * Copyright (C) 2006 SAN People |
5 | * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | |
79da7a61 AV |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | */ | |
13 | ||
8c3583b6 JCPV |
14 | #ifndef __MACH_CPU_H__ |
15 | #define __MACH_CPU_H__ | |
79da7a61 AV |
16 | |
17 | #define ARCH_ID_AT91RM9200 0x09290780 | |
18 | #define ARCH_ID_AT91SAM9260 0x019803a0 | |
19 | #define ARCH_ID_AT91SAM9261 0x019703a0 | |
b2c65616 | 20 | #define ARCH_ID_AT91SAM9263 0x019607a0 |
e2941054 | 21 | #define ARCH_ID_AT91SAM9G10 0x019903a0 |
61352667 | 22 | #define ARCH_ID_AT91SAM9G20 0x019905a0 |
2b3b3516 | 23 | #define ARCH_ID_AT91SAM9RL64 0x019b03a0 |
fddcc0ae | 24 | #define ARCH_ID_AT91SAM9G45 0x819b05a0 |
d8951ade NF |
25 | #define ARCH_ID_AT91SAM9G45MRL 0x819b05a2 /* aka 9G45-ES2 & non ES lots */ |
26 | #define ARCH_ID_AT91SAM9G45ES 0x819b05a1 /* 9G45-ES (Engineering Sample) */ | |
9baeb7e4 | 27 | #define ARCH_ID_AT91SAM9X5 0x819a05a0 |
79da7a61 | 28 | |
f7eee89b AV |
29 | #define ARCH_ID_AT91SAM9XE128 0x329973a0 |
30 | #define ARCH_ID_AT91SAM9XE256 0x329a93a0 | |
31 | #define ARCH_ID_AT91SAM9XE512 0x329aa3a0 | |
79da7a61 | 32 | |
70672224 GU |
33 | #define ARCH_ID_AT91M40800 0x14080044 |
34 | #define ARCH_ID_AT91R40807 0x44080746 | |
35 | #define ARCH_ID_AT91M40807 0x14080745 | |
36 | #define ARCH_ID_AT91R40008 0x44000840 | |
37 | ||
fddcc0ae NF |
38 | #define ARCH_EXID_AT91SAM9M11 0x00000001 |
39 | #define ARCH_EXID_AT91SAM9M10 0x00000002 | |
5f9f0a41 | 40 | #define ARCH_EXID_AT91SAM9G46 0x00000003 |
fddcc0ae NF |
41 | #define ARCH_EXID_AT91SAM9G45 0x00000004 |
42 | ||
9baeb7e4 JCPV |
43 | #define ARCH_EXID_AT91SAM9G15 0x00000000 |
44 | #define ARCH_EXID_AT91SAM9G35 0x00000001 | |
45 | #define ARCH_EXID_AT91SAM9X35 0x00000002 | |
46 | #define ARCH_EXID_AT91SAM9G25 0x00000003 | |
47 | #define ARCH_EXID_AT91SAM9X25 0x00000004 | |
48 | ||
f7eee89b AV |
49 | #define ARCH_FAMILY_AT91X92 0x09200000 |
50 | #define ARCH_FAMILY_AT91SAM9 0x01900000 | |
51 | #define ARCH_FAMILY_AT91SAM9XE 0x02900000 | |
52 | ||
8c3583b6 JCPV |
53 | /* RM9200 type */ |
54 | #define ARCH_REVISON_9200_BGA (0 << 0) | |
55 | #define ARCH_REVISON_9200_PQFP (1 << 0) | |
56 | ||
1e3ce2b8 | 57 | #ifndef __ASSEMBLY__ |
8c3583b6 JCPV |
58 | enum at91_soc_type { |
59 | /* 920T */ | |
60 | AT91_SOC_RM9200, | |
61 | ||
8c3583b6 JCPV |
62 | /* SAM92xx */ |
63 | AT91_SOC_SAM9260, AT91_SOC_SAM9261, AT91_SOC_SAM9263, | |
64 | ||
65 | /* SAM9Gxx */ | |
66 | AT91_SOC_SAM9G10, AT91_SOC_SAM9G20, AT91_SOC_SAM9G45, | |
67 | ||
68 | /* SAM9RL */ | |
69 | AT91_SOC_SAM9RL, | |
70 | ||
71 | /* SAM9X5 */ | |
72 | AT91_SOC_SAM9X5, | |
73 | ||
74 | /* Unknown type */ | |
75 | AT91_SOC_NONE | |
76 | }; | |
77 | ||
78 | enum at91_soc_subtype { | |
79 | /* RM9200 */ | |
80 | AT91_SOC_RM9200_BGA, AT91_SOC_RM9200_PQFP, | |
81 | ||
8c3583b6 JCPV |
82 | /* SAM9260 */ |
83 | AT91_SOC_SAM9XE, | |
84 | ||
85 | /* SAM9G45 */ | |
86 | AT91_SOC_SAM9G45ES, AT91_SOC_SAM9M10, AT91_SOC_SAM9G46, AT91_SOC_SAM9M11, | |
87 | ||
88 | /* SAM9X5 */ | |
89 | AT91_SOC_SAM9G15, AT91_SOC_SAM9G35, AT91_SOC_SAM9X35, | |
90 | AT91_SOC_SAM9G25, AT91_SOC_SAM9X25, | |
91 | ||
92 | /* Unknown subtype */ | |
93 | AT91_SOC_SUBTYPE_NONE | |
94 | }; | |
95 | ||
96 | struct at91_socinfo { | |
97 | unsigned int type, subtype; | |
98 | unsigned int cidr, exid; | |
99 | }; | |
100 | ||
101 | extern struct at91_socinfo at91_soc_initdata; | |
102 | const char *at91_get_soc_type(struct at91_socinfo *c); | |
103 | const char *at91_get_soc_subtype(struct at91_socinfo *c); | |
104 | ||
105 | static inline int at91_soc_is_detected(void) | |
7be90a6b | 106 | { |
8c3583b6 | 107 | return at91_soc_initdata.type != AT91_SOC_NONE; |
7be90a6b | 108 | } |
f7eee89b | 109 | |
1e3ce2b8 | 110 | #ifdef CONFIG_SOC_AT91RM9200 |
8c3583b6 JCPV |
111 | #define cpu_is_at91rm9200() (at91_soc_initdata.type == AT91_SOC_RM9200) |
112 | #define cpu_is_at91rm9200_bga() (at91_soc_initdata.subtype == AT91_SOC_RM9200_BGA) | |
113 | #define cpu_is_at91rm9200_pqfp() (at91_soc_initdata.subtype == AT91_SOC_RM9200_PQFP) | |
79da7a61 AV |
114 | #else |
115 | #define cpu_is_at91rm9200() (0) | |
e57556e3 JCPV |
116 | #define cpu_is_at91rm9200_bga() (0) |
117 | #define cpu_is_at91rm9200_pqfp() (0) | |
79da7a61 AV |
118 | #endif |
119 | ||
1e3ce2b8 | 120 | #ifdef CONFIG_SOC_AT91SAM9260 |
8c3583b6 JCPV |
121 | #define cpu_is_at91sam9xe() (at91_soc_initdata.subtype == AT91_SOC_SAM9XE) |
122 | #define cpu_is_at91sam9260() (at91_soc_initdata.type == AT91_SOC_SAM9260) | |
1e3ce2b8 | 123 | #define cpu_is_at91sam9g20() (at91_soc_initdata.type == AT91_SOC_SAM9G20) |
79da7a61 | 124 | #else |
f7eee89b | 125 | #define cpu_is_at91sam9xe() (0) |
79da7a61 | 126 | #define cpu_is_at91sam9260() (0) |
61352667 | 127 | #define cpu_is_at91sam9g20() (0) |
128 | #endif | |
129 | ||
1e3ce2b8 | 130 | #ifdef CONFIG_SOC_AT91SAM9261 |
8c3583b6 | 131 | #define cpu_is_at91sam9261() (at91_soc_initdata.type == AT91_SOC_SAM9261) |
8c3583b6 | 132 | #define cpu_is_at91sam9g10() (at91_soc_initdata.type == AT91_SOC_SAM9G10) |
b784b7c0 | 133 | #else |
1e3ce2b8 | 134 | #define cpu_is_at91sam9261() (0) |
b784b7c0 NF |
135 | #define cpu_is_at91sam9g10() (0) |
136 | #endif | |
137 | ||
1e3ce2b8 | 138 | #ifdef CONFIG_SOC_AT91SAM9263 |
8c3583b6 | 139 | #define cpu_is_at91sam9263() (at91_soc_initdata.type == AT91_SOC_SAM9263) |
b2c65616 AV |
140 | #else |
141 | #define cpu_is_at91sam9263() (0) | |
142 | #endif | |
143 | ||
1e3ce2b8 | 144 | #ifdef CONFIG_SOC_AT91SAM9RL |
8c3583b6 | 145 | #define cpu_is_at91sam9rl() (at91_soc_initdata.type == AT91_SOC_SAM9RL) |
877d7720 AV |
146 | #else |
147 | #define cpu_is_at91sam9rl() (0) | |
148 | #endif | |
149 | ||
1e3ce2b8 | 150 | #ifdef CONFIG_SOC_AT91SAM9G45 |
8c3583b6 JCPV |
151 | #define cpu_is_at91sam9g45() (at91_soc_initdata.type == AT91_SOC_SAM9G45) |
152 | #define cpu_is_at91sam9g45es() (at91_soc_initdata.subtype == AT91_SOC_SAM9G45ES) | |
153 | #define cpu_is_at91sam9m10() (at91_soc_initdata.subtype == AT91_SOC_SAM9M10) | |
154 | #define cpu_is_at91sam9g46() (at91_soc_initdata.subtype == AT91_SOC_SAM9G46) | |
155 | #define cpu_is_at91sam9m11() (at91_soc_initdata.subtype == AT91_SOC_SAM9M11) | |
fddcc0ae NF |
156 | #else |
157 | #define cpu_is_at91sam9g45() (0) | |
d8951ade | 158 | #define cpu_is_at91sam9g45es() (0) |
5f9f0a41 NF |
159 | #define cpu_is_at91sam9m10() (0) |
160 | #define cpu_is_at91sam9g46() (0) | |
161 | #define cpu_is_at91sam9m11() (0) | |
fddcc0ae NF |
162 | #endif |
163 | ||
1e3ce2b8 | 164 | #ifdef CONFIG_SOC_AT91SAM9X5 |
8c3583b6 JCPV |
165 | #define cpu_is_at91sam9x5() (at91_soc_initdata.type == AT91_SOC_SAM9X5) |
166 | #define cpu_is_at91sam9g15() (at91_soc_initdata.subtype == AT91_SOC_SAM9G15) | |
167 | #define cpu_is_at91sam9g35() (at91_soc_initdata.subtype == AT91_SOC_SAM9G35) | |
168 | #define cpu_is_at91sam9x35() (at91_soc_initdata.subtype == AT91_SOC_SAM9X35) | |
169 | #define cpu_is_at91sam9g25() (at91_soc_initdata.subtype == AT91_SOC_SAM9G25) | |
170 | #define cpu_is_at91sam9x25() (at91_soc_initdata.subtype == AT91_SOC_SAM9X25) | |
9baeb7e4 JCPV |
171 | #else |
172 | #define cpu_is_at91sam9x5() (0) | |
173 | #define cpu_is_at91sam9g15() (0) | |
174 | #define cpu_is_at91sam9g35() (0) | |
175 | #define cpu_is_at91sam9x35() (0) | |
176 | #define cpu_is_at91sam9g25() (0) | |
177 | #define cpu_is_at91sam9x25() (0) | |
178 | #endif | |
179 | ||
e7498281 HS |
180 | /* |
181 | * Since this is ARM, we will never run on any AVR32 CPU. But these | |
182 | * definitions may reduce clutter in common drivers. | |
183 | */ | |
184 | #define cpu_is_at32ap7000() (0) | |
1e3ce2b8 | 185 | #endif /* __ASSEMBLY__ */ |
e7498281 | 186 | |
8c3583b6 | 187 | #endif /* __MACH_CPU_H__ */ |