Commit | Line | Data |
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73a59c1c | 1 | /* |
a09e64fb | 2 | * arch/arm/mach-at91/include/mach/system.h |
73a59c1c SP |
3 | * |
4 | * Copyright (C) 2003 SAN People | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | */ | |
20 | ||
21 | #ifndef __ASM_ARCH_SYSTEM_H | |
22 | #define __ASM_ARCH_SYSTEM_H | |
23 | ||
a09e64fb RK |
24 | #include <mach/hardware.h> |
25 | #include <mach/at91_st.h> | |
26 | #include <mach/at91_dbgu.h> | |
73a59c1c SP |
27 | |
28 | static inline void arch_idle(void) | |
29 | { | |
30 | /* | |
31 | * Disable the processor clock. The processor will be automatically | |
32 | * re-enabled by an interrupt or by a reset. | |
33 | */ | |
34 | // at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK); | |
35 | ||
36 | /* | |
37 | * Set the processor (CP15) into 'Wait for Interrupt' mode. | |
38 | * Unlike disabling the processor clock via the PMC (above) | |
39 | * this allows the processor to be woken via JTAG. | |
40 | */ | |
41 | cpu_do_idle(); | |
42 | } | |
43 | ||
1f4fd0a0 AV |
44 | void (*at91_arch_reset)(void); |
45 | ||
be093beb | 46 | static inline void arch_reset(char mode, const char *cmd) |
73a59c1c | 47 | { |
1f4fd0a0 AV |
48 | /* call the CPU-specific reset function */ |
49 | if (at91_arch_reset) | |
50 | (at91_arch_reset)(); | |
73a59c1c SP |
51 | } |
52 | ||
53 | #endif |