[deliverable/linux.git] / arch / arm / mach-at91 / include / mach / uncompress.h

/*
 * arch/arm/mach-at91/include/mach/uncompress.h
 *
 * Copyright (C) 2003 SAN People
 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

#ifndef __ASM_ARCH_UNCOMPRESS_H
#define __ASM_ARCH_UNCOMPRESS_H

#include <linux/io.h>
#include <linux/atmel_serial.h>
#include <mach/hardware.h>

#include <mach/at91_dbgu.h>
#include <mach/cpu.h>

void __iomem *at91_uart;

#if !defined(CONFIG_ARCH_AT91X40)
static const u32 uarts_rm9200[] = {
	AT91_BASE_DBGU0,
	AT91RM9200_BASE_US0,
	AT91RM9200_BASE_US1,
	AT91RM9200_BASE_US2,
	AT91RM9200_BASE_US3,
	0,
};

static const u32 uarts_sam9260[] = {
	AT91_BASE_DBGU0,
	AT91SAM9260_BASE_US0,
	AT91SAM9260_BASE_US1,
	AT91SAM9260_BASE_US2,
	AT91SAM9260_BASE_US3,
	AT91SAM9260_BASE_US4,
	AT91SAM9260_BASE_US5,
	0,
};

static const u32 uarts_sam9261[] = {
	AT91_BASE_DBGU0,
	AT91SAM9261_BASE_US0,
	AT91SAM9261_BASE_US1,
	AT91SAM9261_BASE_US2,
	0,
};

static const u32 uarts_sam9263[] = {
	AT91_BASE_DBGU1,
	AT91SAM9263_BASE_US0,
	AT91SAM9263_BASE_US1,
	AT91SAM9263_BASE_US2,
	0,
};

static const u32 uarts_sam9g45[] = {
	AT91_BASE_DBGU1,
	AT91SAM9G45_BASE_US0,
	AT91SAM9G45_BASE_US1,
	AT91SAM9G45_BASE_US2,
	AT91SAM9G45_BASE_US3,
	0,
};

static const u32 uarts_sam9rl[] = {
	AT91_BASE_DBGU0,
	AT91SAM9RL_BASE_US0,
	AT91SAM9RL_BASE_US1,
	AT91SAM9RL_BASE_US2,
	AT91SAM9RL_BASE_US3,
	0,
};

static const u32 uarts_sam9x5[] = {
	AT91_BASE_DBGU0,
	AT91SAM9X5_BASE_USART0,
	AT91SAM9X5_BASE_USART1,
	AT91SAM9X5_BASE_USART2,
	0,
};

static inline const u32* decomp_soc_detect(void __iomem *dbgu_base)
{
	u32 cidr, socid;

	cidr = __raw_readl(dbgu_base + AT91_DBGU_CIDR);
	socid = cidr & ~AT91_CIDR_VERSION;

	switch (socid) {
	case ARCH_ID_AT91RM9200:
		return uarts_rm9200;

	case ARCH_ID_AT91SAM9G20:
	case ARCH_ID_AT91SAM9260:
		return uarts_sam9260;

	case ARCH_ID_AT91SAM9261:
		return uarts_sam9261;

	case ARCH_ID_AT91SAM9263:
		return uarts_sam9263;

	case ARCH_ID_AT91SAM9G45:
		return uarts_sam9g45;

	case ARCH_ID_AT91SAM9RL64:
		return uarts_sam9rl;

	case ARCH_ID_AT91SAM9X5:
		return uarts_sam9x5;
	}

	/* at91sam9g10 */
	if ((cidr & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10) {
		return uarts_sam9261;
	}
	/* at91sam9xe */
	else if ((cidr & AT91_CIDR_ARCH) == ARCH_FAMILY_AT91SAM9XE) {
		return uarts_sam9260;
	}

	return NULL;
}

static inline void arch_decomp_setup(void)
{
	int i = 0;
	const u32* usarts;

	usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU0);

	if (!usarts)
		usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU1);
	if (!usarts) {
		at91_uart = NULL;
		return;
	}

	do {
		/* physical address */
		at91_uart = (void __iomem *)usarts[i];

		if (__raw_readl(at91_uart + ATMEL_US_BRGR))
			return;
		i++;
	} while (usarts[i]);

	at91_uart = NULL;
}
#else
static inline void arch_decomp_setup(void)
{
	at91_uart = NULL;
}
#endif

/*
 * The following code assumes the serial port has already been
 * initialized by the bootloader.  If you didn't setup a port in
 * your bootloader then nothing will appear (which might be desired).
 *
 * This does not append a newline
 */
static void putc(int c)
{
	if (!at91_uart)
		return;

	while (!(__raw_readl(at91_uart + ATMEL_US_CSR) & ATMEL_US_TXRDY))
		barrier();
	__raw_writel(c, at91_uart + ATMEL_US_THR);
}

static inline void flush(void)
{
	if (!at91_uart)
		return;

	/* wait for transmission to complete */
	while (!(__raw_readl(at91_uart + ATMEL_US_CSR) & ATMEL_US_TXEMPTY))
		barrier();
}

#define arch_decomp_wdog()

#endif
Commit	Line	Data
73a59c1c	1	/*
a09e64fb	2	* arch/arm/mach-at91/include/mach/uncompress.h
73a59c1c	3	*
5f29d0a0 JCPV	4	* Copyright (C) 2003 SAN People
5f29d0a0 JCPV	5	* Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
73a59c1c SP	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	20	*/
	21
	22	#ifndef __ASM_ARCH_UNCOMPRESS_H
	23	#define __ASM_ARCH_UNCOMPRESS_H
	24
fced80c7	25	#include <linux/io.h>
fa3218d8	26	#include <linux/atmel_serial.h>
4091ac4a	27	#include <mach/hardware.h>
fa3218d8	28
5f29d0a0 JCPV	29	#include <mach/at91_dbgu.h>
5f29d0a0 JCPV	30	#include <mach/cpu.h>
73a59c1c	31
c40a763b JCPV	32	void __iomem *at91_uart;
c40a763b JCPV	33
5f29d0a0 JCPV	34	#if !defined(CONFIG_ARCH_AT91X40)
	35	static const u32 uarts_rm9200[] = {
	36	AT91_BASE_DBGU0,
	37	AT91RM9200_BASE_US0,
	38	AT91RM9200_BASE_US1,
	39	AT91RM9200_BASE_US2,
	40	AT91RM9200_BASE_US3,
	41	0,
	42	};
	43
	44	static const u32 uarts_sam9260[] = {
	45	AT91_BASE_DBGU0,
	46	AT91SAM9260_BASE_US0,
	47	AT91SAM9260_BASE_US1,
	48	AT91SAM9260_BASE_US2,
	49	AT91SAM9260_BASE_US3,
	50	AT91SAM9260_BASE_US4,
	51	AT91SAM9260_BASE_US5,
	52	0,
	53	};
	54
	55	static const u32 uarts_sam9261[] = {
	56	AT91_BASE_DBGU0,
	57	AT91SAM9261_BASE_US0,
	58	AT91SAM9261_BASE_US1,
	59	AT91SAM9261_BASE_US2,
	60	0,
	61	};
	62
	63	static const u32 uarts_sam9263[] = {
	64	AT91_BASE_DBGU1,
	65	AT91SAM9263_BASE_US0,
	66	AT91SAM9263_BASE_US1,
	67	AT91SAM9263_BASE_US2,
	68	0,
	69	};
	70
	71	static const u32 uarts_sam9g45[] = {
	72	AT91_BASE_DBGU1,
	73	AT91SAM9G45_BASE_US0,
	74	AT91SAM9G45_BASE_US1,
	75	AT91SAM9G45_BASE_US2,
	76	AT91SAM9G45_BASE_US3,
	77	0,
	78	};
	79
	80	static const u32 uarts_sam9rl[] = {
	81	AT91_BASE_DBGU0,
	82	AT91SAM9RL_BASE_US0,
	83	AT91SAM9RL_BASE_US1,
	84	AT91SAM9RL_BASE_US2,
	85	AT91SAM9RL_BASE_US3,
	86	0,
	87	};
	88
	89	static const u32 uarts_sam9x5[] = {
	90	AT91_BASE_DBGU0,
	91	AT91SAM9X5_BASE_USART0,
	92	AT91SAM9X5_BASE_USART1,
	93	AT91SAM9X5_BASE_USART2,
	94	0,
	95	};
	96
dca4ba41	97	static inline const u32* decomp_soc_detect(void __iomem *dbgu_base)
5f29d0a0 JCPV	98	{
	99	u32 cidr, socid;
	100
	101	cidr = __raw_readl(dbgu_base + AT91_DBGU_CIDR);
	102	socid = cidr & ~AT91_CIDR_VERSION;
	103
	104	switch (socid) {
	105	case ARCH_ID_AT91RM9200:
	106	return uarts_rm9200;
	107
	108	case ARCH_ID_AT91SAM9G20:
	109	case ARCH_ID_AT91SAM9260:
	110	return uarts_sam9260;
	111
	112	case ARCH_ID_AT91SAM9261:
	113	return uarts_sam9261;
	114
	115	case ARCH_ID_AT91SAM9263:
	116	return uarts_sam9263;
	117
	118	case ARCH_ID_AT91SAM9G45:
	119	return uarts_sam9g45;
	120
	121	case ARCH_ID_AT91SAM9RL64:
	122	return uarts_sam9rl;
	123
	124	case ARCH_ID_AT91SAM9X5:
	125	return uarts_sam9x5;
	126	}
	127
	128	/* at91sam9g10 */
	129	if ((cidr & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10) {
	130	return uarts_sam9261;
	131	}
	132	/* at91sam9xe */
	133	else if ((cidr & AT91_CIDR_ARCH) == ARCH_FAMILY_AT91SAM9XE) {
	134	return uarts_sam9260;
	135	}
	136
	137	return NULL;
	138	}
	139
c40a763b JCPV	140	static inline void arch_decomp_setup(void)
c40a763b JCPV	141	{
5f29d0a0 JCPV	142	int i = 0;
	143	const u32* usarts;
	144
dca4ba41	145	usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU0);
5f29d0a0 JCPV	146
5f29d0a0 JCPV	147	if (!usarts)
dca4ba41	148	usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU1);
5f29d0a0 JCPV	149	if (!usarts) {
	150	at91_uart = NULL;
	151	return;
	152	}
	153
	154	do {
	155	/* physical address */
	156	at91_uart = (void __iomem *)usarts[i];
	157
	158	if (__raw_readl(at91_uart + ATMEL_US_BRGR))
	159	return;
	160	i++;
	161	} while (usarts[i]);
	162
	163	at91_uart = NULL;
c40a763b	164	}
5f29d0a0 JCPV	165	#else
	166	static inline void arch_decomp_setup(void)
	167	{
	168	at91_uart = NULL;
	169	}
	170	#endif
	171
73a59c1c SP	172	/*
73a59c1c SP	173	* The following code assumes the serial port has already been
55d8baee	174	* initialized by the bootloader. If you didn't setup a port in
73a59c1c SP	175	* your bootloader then nothing will appear (which might be desired).
	176	*
	177	* This does not append a newline
	178	*/
a081568d RK	179	static void putc(int c)
a081568d RK	180	{
5f29d0a0 JCPV	181	if (!at91_uart)
	182	return;
	183
c40a763b	184	while (!(__raw_readl(at91_uart + ATMEL_US_CSR) & ATMEL_US_TXRDY))
a081568d	185	barrier();
c40a763b	186	__raw_writel(c, at91_uart + ATMEL_US_THR);
a081568d RK	187	}
	188
	189	static inline void flush(void)
73a59c1c	190	{
5f29d0a0 JCPV	191	if (!at91_uart)
	192	return;
	193
73a59c1c	194	/* wait for transmission to complete */
c40a763b	195	while (!(__raw_readl(at91_uart + ATMEL_US_CSR) & ATMEL_US_TXEMPTY))
a081568d	196	barrier();
73a59c1c SP	197	}
73a59c1c SP	198
73a59c1c SP	199	#define arch_decomp_wdog()
	200
	201	#endif