[deliverable/linux.git] / arch / arm / mach-at91 / irq.c

/*
 * linux/arch/arm/mach-at91/irq.c
 *
 *  Copyright (C) 2004 SAN People
 *  Copyright (C) 2004 ATMEL
 *  Copyright (C) Rick Bronson
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/mm.h>
#include <linux/types.h>

#include <asm/hardware.h>
#include <asm/irq.h>
#include <asm/mach-types.h>
#include <asm/setup.h>

#include <asm/mach/arch.h>
#include <asm/mach/irq.h>
#include <asm/mach/map.h>


static void at91_aic_mask_irq(unsigned int irq)
{
	/* Disable interrupt on AIC */
	at91_sys_write(AT91_AIC_IDCR, 1 << irq);
}

static void at91_aic_unmask_irq(unsigned int irq)
{
	/* Enable interrupt on AIC */
	at91_sys_write(AT91_AIC_IECR, 1 << irq);
}

unsigned int at91_extern_irq;

#define is_extern_irq(irq) ((1 << (irq)) & at91_extern_irq)

static int at91_aic_set_type(unsigned irq, unsigned type)
{
	unsigned int smr, srctype;

	switch (type) {
	case IRQT_HIGH:
		srctype = AT91_AIC_SRCTYPE_HIGH;
		break;
	case IRQT_RISING:
		srctype = AT91_AIC_SRCTYPE_RISING;
		break;
	case IRQT_LOW:
		if ((irq == AT91_ID_FIQ) || is_extern_irq(irq))		/* only supported on external interrupts */
			srctype = AT91_AIC_SRCTYPE_LOW;
		else
			return -EINVAL;
		break;
	case IRQT_FALLING:
		if ((irq == AT91_ID_FIQ) || is_extern_irq(irq))		/* only supported on external interrupts */
			srctype = AT91_AIC_SRCTYPE_FALLING;
		else
			return -EINVAL;
		break;
	default:
		return -EINVAL;
	}

	smr = at91_sys_read(AT91_AIC_SMR(irq)) & ~AT91_AIC_SRCTYPE;
	at91_sys_write(AT91_AIC_SMR(irq), smr | srctype);
	return 0;
}

#ifdef CONFIG_PM

static u32 wakeups;
static u32 backups;

static int at91_aic_set_wake(unsigned irq, unsigned value)
{
	if (unlikely(irq >= 32))
		return -EINVAL;

	if (value)
		wakeups |= (1 << irq);
	else
		wakeups &= ~(1 << irq);

	return 0;
}

void at91_irq_suspend(void)
{
	backups = at91_sys_read(AT91_AIC_IMR);
	at91_sys_write(AT91_AIC_IDCR, backups);
	at91_sys_write(AT91_AIC_IECR, wakeups);
}

void at91_irq_resume(void)
{
	at91_sys_write(AT91_AIC_IDCR, wakeups);
	at91_sys_write(AT91_AIC_IECR, backups);
}

#else
#define at91_aic_set_wake	NULL
#endif

static struct irq_chip at91_aic_chip = {
	.name		= "AIC",
	.ack		= at91_aic_mask_irq,
	.mask		= at91_aic_mask_irq,
	.unmask		= at91_aic_unmask_irq,
	.set_type	= at91_aic_set_type,
	.set_wake	= at91_aic_set_wake,
};

/*
 * Initialize the AIC interrupt controller.
 */
void __init at91_aic_init(unsigned int priority[NR_AIC_IRQS])
{
	unsigned int i;

	/*
	 * The IVR is used by macro get_irqnr_and_base to read and verify.
	 * The irq number is NR_AIC_IRQS when a spurious interrupt has occurred.
	 */
	for (i = 0; i < NR_AIC_IRQS; i++) {
		/* Put irq number in Source Vector Register: */
		at91_sys_write(AT91_AIC_SVR(i), i);
		/* Active Low interrupt, with the specified priority */
		at91_sys_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]);

		set_irq_chip(i, &at91_aic_chip);
		set_irq_handler(i, handle_level_irq);
		set_irq_flags(i, IRQF_VALID | IRQF_PROBE);

		/* Perform 8 End Of Interrupt Command to make sure AIC will not Lock out nIRQ */
		if (i < 8)
			at91_sys_write(AT91_AIC_EOICR, 0);
	}

	/*
	 * Spurious Interrupt ID in Spurious Vector Register is NR_AIC_IRQS
	 * When there is no current interrupt, the IRQ Vector Register reads the value stored in AIC_SPU
	 */
	at91_sys_write(AT91_AIC_SPU, NR_AIC_IRQS);

	/* No debugging in AIC: Debug (Protect) Control Register */
	at91_sys_write(AT91_AIC_DCR, 0);

	/* Disable and clear all interrupts initially */
	at91_sys_write(AT91_AIC_IDCR, 0xFFFFFFFF);
	at91_sys_write(AT91_AIC_ICCR, 0xFFFFFFFF);
}
Commit	Line	Data
73a59c1c	1	/*
9d041268	2	* linux/arch/arm/mach-at91/irq.c
73a59c1c SP	3	*
	4	* Copyright (C) 2004 SAN People
	5	* Copyright (C) 2004 ATMEL
	6	* Copyright (C) Rick Bronson
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	21	*/
	22
73a59c1c SP	23	#include <linux/init.h>
	24	#include <linux/module.h>
	25	#include <linux/mm.h>
	26	#include <linux/types.h>
	27
	28	#include <asm/hardware.h>
	29	#include <asm/irq.h>
	30	#include <asm/mach-types.h>
	31	#include <asm/setup.h>
	32
	33	#include <asm/mach/arch.h>
	34	#include <asm/mach/irq.h>
	35	#include <asm/mach/map.h>
	36
73a59c1c	37
ba854e18	38	static void at91_aic_mask_irq(unsigned int irq)
73a59c1c SP	39	{
	40	/* Disable interrupt on AIC */
	41	at91_sys_write(AT91_AIC_IDCR, 1 << irq);
	42	}
	43
ba854e18	44	static void at91_aic_unmask_irq(unsigned int irq)
73a59c1c SP	45	{
	46	/* Enable interrupt on AIC */
	47	at91_sys_write(AT91_AIC_IECR, 1 << irq);
	48	}
	49
1f4fd0a0 AV	50	unsigned int at91_extern_irq;
	51
	52	#define is_extern_irq(irq) ((1 << (irq)) & at91_extern_irq)
	53
ba854e18	54	static int at91_aic_set_type(unsigned irq, unsigned type)
73a59c1c SP	55	{
	56	unsigned int smr, srctype;
	57
73a59c1c SP	58	switch (type) {
	59	case IRQT_HIGH:
	60	srctype = AT91_AIC_SRCTYPE_HIGH;
	61	break;
	62	case IRQT_RISING:
	63	srctype = AT91_AIC_SRCTYPE_RISING;
	64	break;
	65	case IRQT_LOW:
1f4fd0a0 AV	66	if ((irq == AT91_ID_FIQ) \|\| is_extern_irq(irq)) /* only supported on external interrupts */
	67	srctype = AT91_AIC_SRCTYPE_LOW;
	68	else
37f2e4bc	69	return -EINVAL;
73a59c1c SP	70	break;
73a59c1c SP	71	case IRQT_FALLING:
1f4fd0a0 AV	72	if ((irq == AT91_ID_FIQ) \|\| is_extern_irq(irq)) /* only supported on external interrupts */
	73	srctype = AT91_AIC_SRCTYPE_FALLING;
	74	else
37f2e4bc	75	return -EINVAL;
73a59c1c SP	76	break;
	77	default:
	78	return -EINVAL;
	79	}
	80
	81	smr = at91_sys_read(AT91_AIC_SMR(irq)) & ~AT91_AIC_SRCTYPE;
	82	at91_sys_write(AT91_AIC_SMR(irq), smr \| srctype);
	83	return 0;
	84	}
	85
683c66bf AV	86	#ifdef CONFIG_PM
	87
	88	static u32 wakeups;
	89	static u32 backups;
	90
ba854e18	91	static int at91_aic_set_wake(unsigned irq, unsigned value)
683c66bf AV	92	{
	93	if (unlikely(irq >= 32))
	94	return -EINVAL;
	95
	96	if (value)
	97	wakeups \|= (1 << irq);
	98	else
	99	wakeups &= ~(1 << irq);
	100
	101	return 0;
	102	}
	103
	104	void at91_irq_suspend(void)
	105	{
	106	backups = at91_sys_read(AT91_AIC_IMR);
	107	at91_sys_write(AT91_AIC_IDCR, backups);
	108	at91_sys_write(AT91_AIC_IECR, wakeups);
	109	}
	110
	111	void at91_irq_resume(void)
	112	{
	113	at91_sys_write(AT91_AIC_IDCR, wakeups);
	114	at91_sys_write(AT91_AIC_IECR, backups);
	115	}
	116
	117	#else
ba854e18	118	#define at91_aic_set_wake NULL
683c66bf AV	119	#endif
683c66bf AV	120
38c677cb DB	121	static struct irq_chip at91_aic_chip = {
38c677cb DB	122	.name = "AIC",
ba854e18 AV	123	.ack = at91_aic_mask_irq,
	124	.mask = at91_aic_mask_irq,
	125	.unmask = at91_aic_unmask_irq,
	126	.set_type = at91_aic_set_type,
	127	.set_wake = at91_aic_set_wake,
73a59c1c SP	128	};
	129
	130	/*
	131	* Initialize the AIC interrupt controller.
	132	*/
ba854e18	133	void __init at91_aic_init(unsigned int priority[NR_AIC_IRQS])
73a59c1c SP	134	{
	135	unsigned int i;
	136
73a59c1c SP	137	/*
	138	* The IVR is used by macro get_irqnr_and_base to read and verify.
	139	* The irq number is NR_AIC_IRQS when a spurious interrupt has occurred.
	140	*/
	141	for (i = 0; i < NR_AIC_IRQS; i++) {
	142	/* Put irq number in Source Vector Register: */
	143	at91_sys_write(AT91_AIC_SVR(i), i);
ba854e18	144	/* Active Low interrupt, with the specified priority */
73a59c1c SP	145	at91_sys_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW \| priority[i]);
73a59c1c SP	146
ba854e18	147	set_irq_chip(i, &at91_aic_chip);
10dd5ce2	148	set_irq_handler(i, handle_level_irq);
73a59c1c SP	149	set_irq_flags(i, IRQF_VALID \| IRQF_PROBE);
	150
	151	/* Perform 8 End Of Interrupt Command to make sure AIC will not Lock out nIRQ */
	152	if (i < 8)
	153	at91_sys_write(AT91_AIC_EOICR, 0);
	154	}
	155
	156	/*
	157	* Spurious Interrupt ID in Spurious Vector Register is NR_AIC_IRQS
	158	* When there is no current interrupt, the IRQ Vector Register reads the value stored in AIC_SPU
	159	*/
	160	at91_sys_write(AT91_AIC_SPU, NR_AIC_IRQS);
	161
	162	/* No debugging in AIC: Debug (Protect) Control Register */
	163	at91_sys_write(AT91_AIC_DCR, 0);
	164
	165	/* Disable and clear all interrupts initially */
	166	at91_sys_write(AT91_AIC_IDCR, 0xFFFFFFFF);
	167	at91_sys_write(AT91_AIC_ICCR, 0xFFFFFFFF);
	168	}