[deliverable/linux.git] / arch / arm / mach-at91 / pm.c

/*
 * arch/arm/mach-at91/pm.c
 * AT91 Power Management
 *
 * Copyright (C) 2005 David Brownell
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/gpio.h>
#include <linux/suspend.h>
#include <linux/sched.h>
#include <linux/proc_fs.h>
#include <linux/genalloc.h>
#include <linux/interrupt.h>
#include <linux/sysfs.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/clk/at91_pmc.h>

#include <asm/irq.h>
#include <linux/atomic.h>
#include <asm/mach/time.h>
#include <asm/mach/irq.h>
#include <asm/fncpy.h>
#include <asm/cacheflush.h>

#include "generic.h"
#include "pm.h"

/*
 * FIXME: this is needed to communicate between the pinctrl driver and
 * the PM implementation in the machine. Possibly part of the PM
 * implementation should be moved down into the pinctrl driver and get
 * called as part of the generic suspend/resume path.
 */
#ifdef CONFIG_PINCTRL_AT91
extern void at91_pinctrl_gpio_suspend(void);
extern void at91_pinctrl_gpio_resume(void);
#endif

static struct {
	unsigned long uhp_udp_mask;
	int memctrl;
} at91_pm_data;

void __iomem *at91_ramc_base[2];

static int at91_pm_valid_state(suspend_state_t state)
{
	switch (state) {
		case PM_SUSPEND_ON:
		case PM_SUSPEND_STANDBY:
		case PM_SUSPEND_MEM:
			return 1;

		default:
			return 0;
	}
}


static suspend_state_t target_state;

/*
 * Called after processes are frozen, but before we shutdown devices.
 */
static int at91_pm_begin(suspend_state_t state)
{
	target_state = state;
	return 0;
}

/*
 * Verify that all the clocks are correct before entering
 * slow-clock mode.
 */
static int at91_pm_verify_clocks(void)
{
	unsigned long scsr;
	int i;

	scsr = at91_pmc_read(AT91_PMC_SCSR);

	/* USB must not be using PLLB */
	if ((scsr & at91_pm_data.uhp_udp_mask) != 0) {
		pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
		return 0;
	}

	/* PCK0..PCK3 must be disabled, or configured to use clk32k */
	for (i = 0; i < 4; i++) {
		u32 css;

		if ((scsr & (AT91_PMC_PCK0 << i)) == 0)
			continue;

		css = at91_pmc_read(AT91_PMC_PCKR(i)) & AT91_PMC_CSS;
		if (css != AT91_PMC_CSS_SLOW) {
			pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css);
			return 0;
		}
	}

	return 1;
}

/*
 * Call this from platform driver suspend() to see how deeply to suspend.
 * For example, some controllers (like OHCI) need one of the PLL clocks
 * in order to act as a wakeup source, and those are not available when
 * going into slow clock mode.
 *
 * REVISIT: generalize as clk_will_be_available(clk)?  Other platforms have
 * the very same problem (but not using at91 main_clk), and it'd be better
 * to add one generic API rather than lots of platform-specific ones.
 */
int at91_suspend_entering_slow_clock(void)
{
	return (target_state == PM_SUSPEND_MEM);
}
EXPORT_SYMBOL(at91_suspend_entering_slow_clock);

static void (*at91_suspend_sram_fn)(void __iomem *pmc, void __iomem *ramc0,
			  void __iomem *ramc1, int memctrl);

extern void at91_pm_suspend_in_sram(void __iomem *pmc, void __iomem *ramc0,
			    void __iomem *ramc1, int memctrl);
extern u32 at91_pm_suspend_in_sram_sz;

static void at91_pm_suspend(suspend_state_t state)
{
	unsigned int pm_data = at91_pm_data.memctrl;

	pm_data |= (state == PM_SUSPEND_MEM) ?
				AT91_PM_MODE(AT91_PM_SLOW_CLOCK) : 0;

	flush_cache_all();
	outer_disable();

	at91_suspend_sram_fn(at91_pmc_base, at91_ramc_base[0],
				at91_ramc_base[1], pm_data);

	outer_resume();
}

static int at91_pm_enter(suspend_state_t state)
{
#ifdef CONFIG_PINCTRL_AT91
	at91_pinctrl_gpio_suspend();
#endif
	switch (state) {
	/*
	 * Suspend-to-RAM is like STANDBY plus slow clock mode, so
	 * drivers must suspend more deeply, the master clock switches
	 * to the clk32k and turns off the main oscillator
	 */
	case PM_SUSPEND_MEM:
		/*
		 * Ensure that clocks are in a valid state.
		 */
		if (!at91_pm_verify_clocks())
			goto error;

		at91_pm_suspend(state);

		break;

	/*
	 * STANDBY mode has *all* drivers suspended; ignores irqs not
	 * marked as 'wakeup' event sources; and reduces DRAM power.
	 * But otherwise it's identical to PM_SUSPEND_ON: cpu idle, and
	 * nothing fancy done with main or cpu clocks.
	 */
	case PM_SUSPEND_STANDBY:
		at91_pm_suspend(state);
		break;

	case PM_SUSPEND_ON:
		cpu_do_idle();
		break;

	default:
		pr_debug("AT91: PM - bogus suspend state %d\n", state);
		goto error;
	}

error:
	target_state = PM_SUSPEND_ON;

#ifdef CONFIG_PINCTRL_AT91
	at91_pinctrl_gpio_resume();
#endif
	return 0;
}

/*
 * Called right prior to thawing processes.
 */
static void at91_pm_end(void)
{
	target_state = PM_SUSPEND_ON;
}


static const struct platform_suspend_ops at91_pm_ops = {
	.valid	= at91_pm_valid_state,
	.begin	= at91_pm_begin,
	.enter	= at91_pm_enter,
	.end	= at91_pm_end,
};

static struct platform_device at91_cpuidle_device = {
	.name = "cpuidle-at91",
};

static void at91_pm_set_standby(void (*at91_standby)(void))
{
	if (at91_standby)
		at91_cpuidle_device.dev.platform_data = at91_standby;
}

/*
 * The AT91RM9200 goes into self-refresh mode with this command, and will
 * terminate self-refresh automatically on the next SDRAM access.
 *
 * Self-refresh mode is exited as soon as a memory access is made, but we don't
 * know for sure when that happens. However, we need to restore the low-power
 * mode if it was enabled before going idle. Restoring low-power mode while
 * still in self-refresh is "not recommended", but seems to work.
 */
static void at91rm9200_standby(void)
{
	u32 lpr = at91_ramc_read(0, AT91_MC_SDRAMC_LPR);

	asm volatile(
		"b    1f\n\t"
		".align    5\n\t"
		"1:  mcr    p15, 0, %0, c7, c10, 4\n\t"
		"    str    %0, [%1, %2]\n\t"
		"    str    %3, [%1, %4]\n\t"
		"    mcr    p15, 0, %0, c7, c0, 4\n\t"
		"    str    %5, [%1, %2]"
		:
		: "r" (0), "r" (at91_ramc_base[0]), "r" (AT91_MC_SDRAMC_LPR),
		  "r" (1), "r" (AT91_MC_SDRAMC_SRR),
		  "r" (lpr));
}

/* We manage both DDRAM/SDRAM controllers, we need more than one value to
 * remember.
 */
static void at91_ddr_standby(void)
{
	/* Those two values allow us to delay self-refresh activation
	 * to the maximum. */
	u32 lpr0, lpr1 = 0;
	u32 saved_lpr0, saved_lpr1 = 0;

	if (at91_ramc_base[1]) {
		saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
		lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
		lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
	}

	saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
	lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
	lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;

	/* self-refresh mode now */
	at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
	if (at91_ramc_base[1])
		at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);

	cpu_do_idle();

	at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
	if (at91_ramc_base[1])
		at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
}

/* We manage both DDRAM/SDRAM controllers, we need more than one value to
 * remember.
 */
static void at91sam9_sdram_standby(void)
{
	u32 lpr0, lpr1 = 0;
	u32 saved_lpr0, saved_lpr1 = 0;

	if (at91_ramc_base[1]) {
		saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR);
		lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB;
		lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
	}

	saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR);
	lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB;
	lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH;

	/* self-refresh mode now */
	at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0);
	if (at91_ramc_base[1])
		at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1);

	cpu_do_idle();

	at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0);
	if (at91_ramc_base[1])
		at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);
}

static const struct of_device_id const ramc_ids[] __initconst = {
	{ .compatible = "atmel,at91rm9200-sdramc", .data = at91rm9200_standby },
	{ .compatible = "atmel,at91sam9260-sdramc", .data = at91sam9_sdram_standby },
	{ .compatible = "atmel,at91sam9g45-ddramc", .data = at91_ddr_standby },
	{ .compatible = "atmel,sama5d3-ddramc", .data = at91_ddr_standby },
	{ /*sentinel*/ }
};

static __init void at91_dt_ramc(void)
{
	struct device_node *np;
	const struct of_device_id *of_id;
	int idx = 0;
	const void *standby = NULL;

	for_each_matching_node_and_match(np, ramc_ids, &of_id) {
		at91_ramc_base[idx] = of_iomap(np, 0);
		if (!at91_ramc_base[idx])
			panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx);

		if (!standby)
			standby = of_id->data;

		idx++;
	}

	if (!idx)
		panic(pr_fmt("unable to find compatible ram controller node in dtb\n"));

	if (!standby) {
		pr_warn("ramc no standby function available\n");
		return;
	}

	at91_pm_set_standby(standby);
}

static void __init at91_pm_sram_init(void)
{
	struct gen_pool *sram_pool;
	phys_addr_t sram_pbase;
	unsigned long sram_base;
	struct device_node *node;
	struct platform_device *pdev = NULL;

	for_each_compatible_node(node, NULL, "mmio-sram") {
		pdev = of_find_device_by_node(node);
		if (pdev) {
			of_node_put(node);
			break;
		}
	}

	if (!pdev) {
		pr_warn("%s: failed to find sram device!\n", __func__);
		return;
	}

	sram_pool = gen_pool_get(&pdev->dev, NULL);
	if (!sram_pool) {
		pr_warn("%s: sram pool unavailable!\n", __func__);
		return;
	}

	sram_base = gen_pool_alloc(sram_pool, at91_pm_suspend_in_sram_sz);
	if (!sram_base) {
		pr_warn("%s: unable to alloc sram!\n", __func__);
		return;
	}

	sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base);
	at91_suspend_sram_fn = __arm_ioremap_exec(sram_pbase,
					at91_pm_suspend_in_sram_sz, false);
	if (!at91_suspend_sram_fn) {
		pr_warn("SRAM: Could not map\n");
		return;
	}

	/* Copy the pm suspend handler to SRAM */
	at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn,
			&at91_pm_suspend_in_sram, at91_pm_suspend_in_sram_sz);
}

static void __init at91_pm_init(void)
{
	at91_pm_sram_init();

	if (at91_cpuidle_device.dev.platform_data)
		platform_device_register(&at91_cpuidle_device);

	if (at91_suspend_sram_fn)
		suspend_set_ops(&at91_pm_ops);
	else
		pr_info("AT91: PM not supported, due to no SRAM allocated\n");
}

void __init at91rm9200_pm_init(void)
{
	at91_dt_ramc();

	/*
	 * AT91RM9200 SDRAM low-power mode cannot be used with self-refresh.
	 */
	at91_ramc_write(0, AT91_MC_SDRAMC_LPR, 0);

	at91_pm_data.uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP;
	at91_pm_data.memctrl = AT91_MEMCTRL_MC;

	at91_pm_init();
}

void __init at91sam9260_pm_init(void)
{
	at91_dt_ramc();
	at91_pm_data.memctrl = AT91_MEMCTRL_SDRAMC;
	at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP;
	return at91_pm_init();
}

void __init at91sam9g45_pm_init(void)
{
	at91_dt_ramc();
	at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP;
	at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
	return at91_pm_init();
}

void __init at91sam9x5_pm_init(void)
{
	at91_dt_ramc();
	at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP;
	at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
	return at91_pm_init();
}
Commit	Line	Data
907d6deb	1	/*
9d041268	2	* arch/arm/mach-at91/pm.c
907d6deb AV	3	* AT91 Power Management
	4	*
	5	* Copyright (C) 2005 David Brownell
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*/
	12
2f8163ba	13	#include <linux/gpio.h>
95d9ffbe	14	#include <linux/suspend.h>
907d6deb AV	15	#include <linux/sched.h>
907d6deb AV	16	#include <linux/proc_fs.h>
d2e46790	17	#include <linux/genalloc.h>
907d6deb AV	18	#include <linux/interrupt.h>
	19	#include <linux/sysfs.h>
	20	#include <linux/module.h>
f5598d34	21	#include <linux/of.h>
d2e46790	22	#include <linux/of_platform.h>
827de1f1	23	#include <linux/of_address.h>
907d6deb	24	#include <linux/platform_device.h>
fced80c7	25	#include <linux/io.h>
2edb90ae	26	#include <linux/clk/at91_pmc.h>
907d6deb	27
907d6deb	28	#include <asm/irq.h>
60063497	29	#include <linux/atomic.h>
907d6deb AV	30	#include <asm/mach/time.h>
907d6deb AV	31	#include <asm/mach/irq.h>
d94e688c	32	#include <asm/fncpy.h>
385acc0d	33	#include <asm/cacheflush.h>
907d6deb	34
907d6deb	35	#include "generic.h"
1ea60cf7	36	#include "pm.h"
907d6deb	37
23b84082 AB	38	/*
	39	* FIXME: this is needed to communicate between the pinctrl driver and
	40	* the PM implementation in the machine. Possibly part of the PM
	41	* implementation should be moved down into the pinctrl driver and get
	42	* called as part of the generic suspend/resume path.
	43	*/
8423536f	44	#ifdef CONFIG_PINCTRL_AT91
23b84082 AB	45	extern void at91_pinctrl_gpio_suspend(void);
23b84082 AB	46	extern void at91_pinctrl_gpio_resume(void);
8423536f	47	#endif
23b84082	48
f5598d34 AB	49	static struct {
	50	unsigned long uhp_udp_mask;
	51	int memctrl;
	52	} at91_pm_data;
	53
827de1f1	54	void __iomem *at91_ramc_base[2];
5ad945ea	55
907d6deb AV	56	static int at91_pm_valid_state(suspend_state_t state)
	57	{
	58	switch (state) {
	59	case PM_SUSPEND_ON:
	60	case PM_SUSPEND_STANDBY:
	61	case PM_SUSPEND_MEM:
	62	return 1;
	63
	64	default:
	65	return 0;
	66	}
	67	}
	68
	69
	70	static suspend_state_t target_state;
	71
	72	/*
	73	* Called after processes are frozen, but before we shutdown devices.
	74	*/
c697eece	75	static int at91_pm_begin(suspend_state_t state)
907d6deb AV	76	{
	77	target_state = state;
	78	return 0;
	79	}
	80
	81	/*
	82	* Verify that all the clocks are correct before entering
	83	* slow-clock mode.
	84	*/
	85	static int at91_pm_verify_clocks(void)
	86	{
	87	unsigned long scsr;
	88	int i;
	89
b5514952	90	scsr = at91_pmc_read(AT91_PMC_SCSR);
907d6deb AV	91
907d6deb AV	92	/* USB must not be using PLLB */
f5598d34 AB	93	if ((scsr & at91_pm_data.uhp_udp_mask) != 0) {
	94	pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
	95	return 0;
907d6deb AV	96	}
907d6deb AV	97
907d6deb AV	98	/* PCK0..PCK3 must be disabled, or configured to use clk32k */
	99	for (i = 0; i < 4; i++) {
	100	u32 css;
	101
	102	if ((scsr & (AT91_PMC_PCK0 << i)) == 0)
	103	continue;
	104
b5514952	105	css = at91_pmc_read(AT91_PMC_PCKR(i)) & AT91_PMC_CSS;
907d6deb	106	if (css != AT91_PMC_CSS_SLOW) {
7f96b1ca	107	pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css);
907d6deb AV	108	return 0;
	109	}
	110	}
907d6deb AV	111
	112	return 1;
	113	}
	114
	115	/*
	116	* Call this from platform driver suspend() to see how deeply to suspend.
	117	* For example, some controllers (like OHCI) need one of the PLL clocks
	118	* in order to act as a wakeup source, and those are not available when
	119	* going into slow clock mode.
	120	*
	121	* REVISIT: generalize as clk_will_be_available(clk)? Other platforms have
	122	* the very same problem (but not using at91 main_clk), and it'd be better
	123	* to add one generic API rather than lots of platform-specific ones.
	124	*/
	125	int at91_suspend_entering_slow_clock(void)
	126	{
	127	return (target_state == PM_SUSPEND_MEM);
	128	}
	129	EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
	130
5726a8b9	131	static void (at91_suspend_sram_fn)(void __iomem pmc, void __iomem *ramc0,
fb7e197b	132	void __iomem *ramc1, int memctrl);
907d6deb	133
5726a8b9	134	extern void at91_pm_suspend_in_sram(void __iomem pmc, void __iomem ramc0,
fb7e197b	135	void __iomem *ramc1, int memctrl);
5726a8b9	136	extern u32 at91_pm_suspend_in_sram_sz;
f5d0f457	137
23be4be5 WY	138	static void at91_pm_suspend(suspend_state_t state)
	139	{
	140	unsigned int pm_data = at91_pm_data.memctrl;
	141
	142	pm_data \|= (state == PM_SUSPEND_MEM) ?
	143	AT91_PM_MODE(AT91_PM_SLOW_CLOCK) : 0;
	144
385acc0d WY	145	flush_cache_all();
	146	outer_disable();
	147
5726a8b9 WY	148	at91_suspend_sram_fn(at91_pmc_base, at91_ramc_base[0],
5726a8b9 WY	149	at91_ramc_base[1], pm_data);
385acc0d WY	150
385acc0d WY	151	outer_resume();
23be4be5 WY	152	}
23be4be5 WY	153
907d6deb AV	154	static int at91_pm_enter(suspend_state_t state)
907d6deb AV	155	{
8423536f	156	#ifdef CONFIG_PINCTRL_AT91
85c4b31e	157	at91_pinctrl_gpio_suspend();
8423536f	158	#endif
907d6deb	159	switch (state) {
23be4be5 WY	160	/*
	161	* Suspend-to-RAM is like STANDBY plus slow clock mode, so
	162	* drivers must suspend more deeply, the master clock switches
	163	* to the clk32k and turns off the main oscillator
	164	*/
	165	case PM_SUSPEND_MEM:
907d6deb	166	/*
23be4be5	167	* Ensure that clocks are in a valid state.
907d6deb	168	*/
23be4be5 WY	169	if (!at91_pm_verify_clocks())
23be4be5 WY	170	goto error;
907d6deb	171
23be4be5	172	at91_pm_suspend(state);
907d6deb	173
23be4be5	174	break;
907d6deb	175
23be4be5 WY	176	/*
	177	* STANDBY mode has all drivers suspended; ignores irqs not
	178	* marked as 'wakeup' event sources; and reduces DRAM power.
	179	* But otherwise it's identical to PM_SUSPEND_ON: cpu idle, and
	180	* nothing fancy done with main or cpu clocks.
	181	*/
	182	case PM_SUSPEND_STANDBY:
	183	at91_pm_suspend(state);
	184	break;
	185
	186	case PM_SUSPEND_ON:
	187	cpu_do_idle();
	188	break;
	189
	190	default:
	191	pr_debug("AT91: PM - bogus suspend state %d\n", state);
	192	goto error;
907d6deb AV	193	}
907d6deb AV	194
907d6deb AV	195	error:
907d6deb AV	196	target_state = PM_SUSPEND_ON;
07192604	197
8423536f	198	#ifdef CONFIG_PINCTRL_AT91
85c4b31e	199	at91_pinctrl_gpio_resume();
8423536f	200	#endif
907d6deb AV	201	return 0;
	202	}
	203
c697eece RW	204	/*
	205	* Called right prior to thawing processes.
	206	*/
	207	static void at91_pm_end(void)
	208	{
	209	target_state = PM_SUSPEND_ON;
	210	}
	211
907d6deb	212
2f55ac07	213	static const struct platform_suspend_ops at91_pm_ops = {
c697eece RW	214	.valid = at91_pm_valid_state,
	215	.begin = at91_pm_begin,
	216	.enter = at91_pm_enter,
	217	.end = at91_pm_end,
907d6deb AV	218	};
907d6deb AV	219
5ad945ea DL	220	static struct platform_device at91_cpuidle_device = {
	221	.name = "cpuidle-at91",
	222	};
	223
047794e1	224	static void at91_pm_set_standby(void (*at91_standby)(void))
5ad945ea	225	{
e32d995c	226	if (at91_standby)
5ad945ea	227	at91_cpuidle_device.dev.platform_data = at91_standby;
5ad945ea DL	228	}
5ad945ea DL	229
a18d0699 AB	230	/*
	231	* The AT91RM9200 goes into self-refresh mode with this command, and will
	232	* terminate self-refresh automatically on the next SDRAM access.
	233	*
	234	* Self-refresh mode is exited as soon as a memory access is made, but we don't
	235	* know for sure when that happens. However, we need to restore the low-power
	236	* mode if it was enabled before going idle. Restoring low-power mode while
	237	* still in self-refresh is "not recommended", but seems to work.
	238	*/
	239	static void at91rm9200_standby(void)
	240	{
d7d45f25	241	u32 lpr = at91_ramc_read(0, AT91_MC_SDRAMC_LPR);
a18d0699 AB	242
	243	asm volatile(
	244	"b 1f\n\t"
	245	".align 5\n\t"
	246	"1: mcr p15, 0, %0, c7, c10, 4\n\t"
	247	" str %0, [%1, %2]\n\t"
	248	" str %3, [%1, %4]\n\t"
	249	" mcr p15, 0, %0, c7, c0, 4\n\t"
	250	" str %5, [%1, %2]"
	251	:
d7d45f25 AB	252	: "r" (0), "r" (at91_ramc_base[0]), "r" (AT91_MC_SDRAMC_LPR),
d7d45f25 AB	253	"r" (1), "r" (AT91_MC_SDRAMC_SRR),
a18d0699 AB	254	"r" (lpr));
	255	}
	256
	257	/* We manage both DDRAM/SDRAM controllers, we need more than one value to
	258	* remember.
	259	*/
	260	static void at91_ddr_standby(void)
	261	{
	262	/* Those two values allow us to delay self-refresh activation
	263	* to the maximum. */
	264	u32 lpr0, lpr1 = 0;
	265	u32 saved_lpr0, saved_lpr1 = 0;
	266
	267	if (at91_ramc_base[1]) {
	268	saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
	269	lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
	270	lpr1 \|= AT91_DDRSDRC_LPCB_SELF_REFRESH;
	271	}
	272
	273	saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
	274	lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
	275	lpr0 \|= AT91_DDRSDRC_LPCB_SELF_REFRESH;
	276
	277	/* self-refresh mode now */
	278	at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
	279	if (at91_ramc_base[1])
	280	at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
	281
	282	cpu_do_idle();
	283
	284	at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
	285	if (at91_ramc_base[1])
	286	at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
	287	}
	288
	289	/* We manage both DDRAM/SDRAM controllers, we need more than one value to
	290	* remember.
	291	*/
	292	static void at91sam9_sdram_standby(void)
	293	{
	294	u32 lpr0, lpr1 = 0;
	295	u32 saved_lpr0, saved_lpr1 = 0;
	296
	297	if (at91_ramc_base[1]) {
	298	saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR);
	299	lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB;
	300	lpr1 \|= AT91_SDRAMC_LPCB_SELF_REFRESH;
	301	}
	302
	303	saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR);
	304	lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB;
	305	lpr0 \|= AT91_SDRAMC_LPCB_SELF_REFRESH;
	306
	307	/* self-refresh mode now */
	308	at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0);
	309	if (at91_ramc_base[1])
	310	at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1);
	311
	312	cpu_do_idle();
	313
	314	at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0);
	315	if (at91_ramc_base[1])
	316	at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);
	317	}
318
19c233b7	319	static const struct of_device_id const ramc_ids[] __initconst = {
827de1f1 AB	320	{ .compatible = "atmel,at91rm9200-sdramc", .data = at91rm9200_standby },
	321	{ .compatible = "atmel,at91sam9260-sdramc", .data = at91sam9_sdram_standby },
	322	{ .compatible = "atmel,at91sam9g45-ddramc", .data = at91_ddr_standby },
	323	{ .compatible = "atmel,sama5d3-ddramc", .data = at91_ddr_standby },
	324	{ /sentinel/ }
	325	};
	326
444d2d33	327	static __init void at91_dt_ramc(void)
827de1f1 AB	328	{
	329	struct device_node *np;
	330	const struct of_device_id *of_id;
	331	int idx = 0;
	332	const void *standby = NULL;
	333
	334	for_each_matching_node_and_match(np, ramc_ids, &of_id) {
	335	at91_ramc_base[idx] = of_iomap(np, 0);
	336	if (!at91_ramc_base[idx])
	337	panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx);
	338
	339	if (!standby)
	340	standby = of_id->data;
	341
	342	idx++;
	343	}
	344
	345	if (!idx)
	346	panic(pr_fmt("unable to find compatible ram controller node in dtb\n"));
	347
	348	if (!standby) {
	349	pr_warn("ramc no standby function available\n");
	350	return;
	351	}
	352
	353	at91_pm_set_standby(standby);
	354	}
	355
d2e46790 AB	356	static void __init at91_pm_sram_init(void)
	357	{
	358	struct gen_pool *sram_pool;
	359	phys_addr_t sram_pbase;
	360	unsigned long sram_base;
	361	struct device_node *node;
4a031f7d	362	struct platform_device *pdev = NULL;
d2e46790	363
4a031f7d AB	364	for_each_compatible_node(node, NULL, "mmio-sram") {
	365	pdev = of_find_device_by_node(node);
	366	if (pdev) {
	367	of_node_put(node);
	368	break;
	369	}
d2e46790 AB	370	}
d2e46790 AB	371
d2e46790 AB	372	if (!pdev) {
d2e46790 AB	373	pr_warn("%s: failed to find sram device!\n", __func__);
4a031f7d	374	return;
d2e46790 AB	375	}
d2e46790 AB	376
73858173	377	sram_pool = gen_pool_get(&pdev->dev, NULL);
d2e46790 AB	378	if (!sram_pool) {
d2e46790 AB	379	pr_warn("%s: sram pool unavailable!\n", __func__);
4a031f7d	380	return;
d2e46790 AB	381	}
d2e46790 AB	382
5726a8b9	383	sram_base = gen_pool_alloc(sram_pool, at91_pm_suspend_in_sram_sz);
d2e46790	384	if (!sram_base) {
5726a8b9	385	pr_warn("%s: unable to alloc sram!\n", __func__);
4a031f7d	386	return;
d2e46790 AB	387	}
	388
	389	sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base);
5726a8b9 WY	390	at91_suspend_sram_fn = __arm_ioremap_exec(sram_pbase,
	391	at91_pm_suspend_in_sram_sz, false);
	392	if (!at91_suspend_sram_fn) {
d94e688c WY	393	pr_warn("SRAM: Could not map\n");
	394	return;
	395	}
	396
5726a8b9 WY	397	/* Copy the pm suspend handler to SRAM */
	398	at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn,
	399	&at91_pm_suspend_in_sram, at91_pm_suspend_in_sram_sz);
d2e46790	400	}
d2e46790	401
4db0ba22	402	static void __init at91_pm_init(void)
907d6deb	403	{
d2e46790	404	at91_pm_sram_init();
f5d0f457	405
5ad945ea DL	406	if (at91_cpuidle_device.dev.platform_data)
5ad945ea DL	407	platform_device_register(&at91_cpuidle_device);
907d6deb	408
5726a8b9	409	if (at91_suspend_sram_fn)
d94e688c WY	410	suspend_set_ops(&at91_pm_ops);
	411	else
	412	pr_info("AT91: PM not supported, due to no SRAM allocated\n");
4db0ba22	413	}
907d6deb	414
ad3fc3e3	415	void __init at91rm9200_pm_init(void)
4db0ba22	416	{
827de1f1 AB	417	at91_dt_ramc();
827de1f1 AB	418
4db0ba22 AB	419	/*
	420	* AT91RM9200 SDRAM low-power mode cannot be used with self-refresh.
	421	*/
d7d45f25	422	at91_ramc_write(0, AT91_MC_SDRAMC_LPR, 0);
4db0ba22 AB	423
	424	at91_pm_data.uhp_udp_mask = AT91RM9200_PMC_UHP \| AT91RM9200_PMC_UDP;
	425	at91_pm_data.memctrl = AT91_MEMCTRL_MC;
	426
	427	at91_pm_init();
	428	}
	429
ad3fc3e3	430	void __init at91sam9260_pm_init(void)
4db0ba22	431	{
827de1f1	432	at91_dt_ramc();
4db0ba22 AB	433	at91_pm_data.memctrl = AT91_MEMCTRL_SDRAMC;
	434	at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP \| AT91SAM926x_PMC_UDP;
	435	return at91_pm_init();
	436	}
	437
ad3fc3e3	438	void __init at91sam9g45_pm_init(void)
4db0ba22	439	{
827de1f1	440	at91_dt_ramc();
4db0ba22 AB	441	at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP;
	442	at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
	443	return at91_pm_init();
907d6deb	444	}
bf02280e	445
ad3fc3e3	446	void __init at91sam9x5_pm_init(void)
bf02280e	447	{
827de1f1	448	at91_dt_ramc();
bf02280e NF	449	at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP \| AT91SAM926x_PMC_UDP;
	450	at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
	451	return at91_pm_init();
	452	}