[deliverable/linux.git] / arch / arm / mach-at91 / pm.c

/*
 * arch/arm/mach-at91/pm.c
 * AT91 Power Management
 *
 * Copyright (C) 2005 David Brownell
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/gpio.h>
#include <linux/suspend.h>
#include <linux/sched.h>
#include <linux/proc_fs.h>
#include <linux/genalloc.h>
#include <linux/interrupt.h>
#include <linux/sysfs.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/clk/at91_pmc.h>

#include <asm/irq.h>
#include <linux/atomic.h>
#include <asm/mach/time.h>
#include <asm/mach/irq.h>
#include <asm/fncpy.h>
#include <asm/cacheflush.h>
#include <asm/system_misc.h>

#include "generic.h"
#include "pm.h"

static void __iomem *pmc;

/*
 * FIXME: this is needed to communicate between the pinctrl driver and
 * the PM implementation in the machine. Possibly part of the PM
 * implementation should be moved down into the pinctrl driver and get
 * called as part of the generic suspend/resume path.
 */
#ifdef CONFIG_PINCTRL_AT91
extern void at91_pinctrl_gpio_suspend(void);
extern void at91_pinctrl_gpio_resume(void);
#endif

static struct {
	unsigned long uhp_udp_mask;
	int memctrl;
} at91_pm_data;

void __iomem *at91_ramc_base[2];

static int at91_pm_valid_state(suspend_state_t state)
{
	switch (state) {
		case PM_SUSPEND_ON:
		case PM_SUSPEND_STANDBY:
		case PM_SUSPEND_MEM:
			return 1;

		default:
			return 0;
	}
}


static suspend_state_t target_state;

/*
 * Called after processes are frozen, but before we shutdown devices.
 */
static int at91_pm_begin(suspend_state_t state)
{
	target_state = state;
	return 0;
}

/*
 * Verify that all the clocks are correct before entering
 * slow-clock mode.
 */
static int at91_pm_verify_clocks(void)
{
	unsigned long scsr;
	int i;

	scsr = readl(pmc + AT91_PMC_SCSR);

	/* USB must not be using PLLB */
	if ((scsr & at91_pm_data.uhp_udp_mask) != 0) {
		pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
		return 0;
	}

	/* PCK0..PCK3 must be disabled, or configured to use clk32k */
	for (i = 0; i < 4; i++) {
		u32 css;

		if ((scsr & (AT91_PMC_PCK0 << i)) == 0)
			continue;
		css = readl(pmc + AT91_PMC_PCKR(i)) & AT91_PMC_CSS;
		if (css != AT91_PMC_CSS_SLOW) {
			pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css);
			return 0;
		}
	}

	return 1;
}

/*
 * Call this from platform driver suspend() to see how deeply to suspend.
 * For example, some controllers (like OHCI) need one of the PLL clocks
 * in order to act as a wakeup source, and those are not available when
 * going into slow clock mode.
 *
 * REVISIT: generalize as clk_will_be_available(clk)?  Other platforms have
 * the very same problem (but not using at91 main_clk), and it'd be better
 * to add one generic API rather than lots of platform-specific ones.
 */
int at91_suspend_entering_slow_clock(void)
{
	return (target_state == PM_SUSPEND_MEM);
}
EXPORT_SYMBOL(at91_suspend_entering_slow_clock);

static void (*at91_suspend_sram_fn)(void __iomem *pmc, void __iomem *ramc0,
			  void __iomem *ramc1, int memctrl);

extern void at91_pm_suspend_in_sram(void __iomem *pmc, void __iomem *ramc0,
			    void __iomem *ramc1, int memctrl);
extern u32 at91_pm_suspend_in_sram_sz;

static void at91_pm_suspend(suspend_state_t state)
{
	unsigned int pm_data = at91_pm_data.memctrl;

	pm_data |= (state == PM_SUSPEND_MEM) ?
				AT91_PM_MODE(AT91_PM_SLOW_CLOCK) : 0;

	flush_cache_all();
	outer_disable();

	at91_suspend_sram_fn(pmc, at91_ramc_base[0],
			     at91_ramc_base[1], pm_data);

	outer_resume();
}

static int at91_pm_enter(suspend_state_t state)
{
#ifdef CONFIG_PINCTRL_AT91
	at91_pinctrl_gpio_suspend();
#endif
	switch (state) {
	/*
	 * Suspend-to-RAM is like STANDBY plus slow clock mode, so
	 * drivers must suspend more deeply, the master clock switches
	 * to the clk32k and turns off the main oscillator
	 */
	case PM_SUSPEND_MEM:
		/*
		 * Ensure that clocks are in a valid state.
		 */
		if (!at91_pm_verify_clocks())
			goto error;

		at91_pm_suspend(state);

		break;

	/*
	 * STANDBY mode has *all* drivers suspended; ignores irqs not
	 * marked as 'wakeup' event sources; and reduces DRAM power.
	 * But otherwise it's identical to PM_SUSPEND_ON: cpu idle, and
	 * nothing fancy done with main or cpu clocks.
	 */
	case PM_SUSPEND_STANDBY:
		at91_pm_suspend(state);
		break;

	case PM_SUSPEND_ON:
		cpu_do_idle();
		break;

	default:
		pr_debug("AT91: PM - bogus suspend state %d\n", state);
		goto error;
	}

error:
	target_state = PM_SUSPEND_ON;

#ifdef CONFIG_PINCTRL_AT91
	at91_pinctrl_gpio_resume();
#endif
	return 0;
}

/*
 * Called right prior to thawing processes.
 */
static void at91_pm_end(void)
{
	target_state = PM_SUSPEND_ON;
}


static const struct platform_suspend_ops at91_pm_ops = {
	.valid	= at91_pm_valid_state,
	.begin	= at91_pm_begin,
	.enter	= at91_pm_enter,
	.end	= at91_pm_end,
};

static struct platform_device at91_cpuidle_device = {
	.name = "cpuidle-at91",
};

static void at91_pm_set_standby(void (*at91_standby)(void))
{
	if (at91_standby)
		at91_cpuidle_device.dev.platform_data = at91_standby;
}

/*
 * The AT91RM9200 goes into self-refresh mode with this command, and will
 * terminate self-refresh automatically on the next SDRAM access.
 *
 * Self-refresh mode is exited as soon as a memory access is made, but we don't
 * know for sure when that happens. However, we need to restore the low-power
 * mode if it was enabled before going idle. Restoring low-power mode while
 * still in self-refresh is "not recommended", but seems to work.
 */
static void at91rm9200_standby(void)
{
	u32 lpr = at91_ramc_read(0, AT91_MC_SDRAMC_LPR);

	asm volatile(
		"b    1f\n\t"
		".align    5\n\t"
		"1:  mcr    p15, 0, %0, c7, c10, 4\n\t"
		"    str    %0, [%1, %2]\n\t"
		"    str    %3, [%1, %4]\n\t"
		"    mcr    p15, 0, %0, c7, c0, 4\n\t"
		"    str    %5, [%1, %2]"
		:
		: "r" (0), "r" (at91_ramc_base[0]), "r" (AT91_MC_SDRAMC_LPR),
		  "r" (1), "r" (AT91_MC_SDRAMC_SRR),
		  "r" (lpr));
}

/* We manage both DDRAM/SDRAM controllers, we need more than one value to
 * remember.
 */
static void at91_ddr_standby(void)
{
	/* Those two values allow us to delay self-refresh activation
	 * to the maximum. */
	u32 lpr0, lpr1 = 0;
	u32 saved_lpr0, saved_lpr1 = 0;

	if (at91_ramc_base[1]) {
		saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
		lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
		lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
	}

	saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
	lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
	lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;

	/* self-refresh mode now */
	at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
	if (at91_ramc_base[1])
		at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);

	cpu_do_idle();

	at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
	if (at91_ramc_base[1])
		at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
}

/* We manage both DDRAM/SDRAM controllers, we need more than one value to
 * remember.
 */
static void at91sam9_sdram_standby(void)
{
	u32 lpr0, lpr1 = 0;
	u32 saved_lpr0, saved_lpr1 = 0;

	if (at91_ramc_base[1]) {
		saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR);
		lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB;
		lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
	}

	saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR);
	lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB;
	lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH;

	/* self-refresh mode now */
	at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0);
	if (at91_ramc_base[1])
		at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1);

	cpu_do_idle();

	at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0);
	if (at91_ramc_base[1])
		at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);
}

static const struct of_device_id const ramc_ids[] __initconst = {
	{ .compatible = "atmel,at91rm9200-sdramc", .data = at91rm9200_standby },
	{ .compatible = "atmel,at91sam9260-sdramc", .data = at91sam9_sdram_standby },
	{ .compatible = "atmel,at91sam9g45-ddramc", .data = at91_ddr_standby },
	{ .compatible = "atmel,sama5d3-ddramc", .data = at91_ddr_standby },
	{ /*sentinel*/ }
};

static __init void at91_dt_ramc(void)
{
	struct device_node *np;
	const struct of_device_id *of_id;
	int idx = 0;
	const void *standby = NULL;

	for_each_matching_node_and_match(np, ramc_ids, &of_id) {
		at91_ramc_base[idx] = of_iomap(np, 0);
		if (!at91_ramc_base[idx])
			panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx);

		if (!standby)
			standby = of_id->data;

		idx++;
	}

	if (!idx)
		panic(pr_fmt("unable to find compatible ram controller node in dtb\n"));

	if (!standby) {
		pr_warn("ramc no standby function available\n");
		return;
	}

	at91_pm_set_standby(standby);
}

void at91rm9200_idle(void)
{
	/*
	 * Disable the processor clock.  The processor will be automatically
	 * re-enabled by an interrupt or by a reset.
	 */
	writel(AT91_PMC_PCK, pmc + AT91_PMC_SCDR);
}

void at91sam9_idle(void)
{
	writel(AT91_PMC_PCK, pmc + AT91_PMC_SCDR);
	cpu_do_idle();
}

static void __init at91_pm_sram_init(void)
{
	struct gen_pool *sram_pool;
	phys_addr_t sram_pbase;
	unsigned long sram_base;
	struct device_node *node;
	struct platform_device *pdev = NULL;

	for_each_compatible_node(node, NULL, "mmio-sram") {
		pdev = of_find_device_by_node(node);
		if (pdev) {
			of_node_put(node);
			break;
		}
	}

	if (!pdev) {
		pr_warn("%s: failed to find sram device!\n", __func__);
		return;
	}

	sram_pool = gen_pool_get(&pdev->dev, NULL);
	if (!sram_pool) {
		pr_warn("%s: sram pool unavailable!\n", __func__);
		return;
	}

	sram_base = gen_pool_alloc(sram_pool, at91_pm_suspend_in_sram_sz);
	if (!sram_base) {
		pr_warn("%s: unable to alloc sram!\n", __func__);
		return;
	}

	sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base);
	at91_suspend_sram_fn = __arm_ioremap_exec(sram_pbase,
					at91_pm_suspend_in_sram_sz, false);
	if (!at91_suspend_sram_fn) {
		pr_warn("SRAM: Could not map\n");
		return;
	}

	/* Copy the pm suspend handler to SRAM */
	at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn,
			&at91_pm_suspend_in_sram, at91_pm_suspend_in_sram_sz);
}

static const struct of_device_id atmel_pmc_ids[] __initconst = {
	{ .compatible = "atmel,at91rm9200-pmc"  },
	{ .compatible = "atmel,at91sam9260-pmc" },
	{ .compatible = "atmel,at91sam9g45-pmc" },
	{ .compatible = "atmel,at91sam9n12-pmc" },
	{ .compatible = "atmel,at91sam9x5-pmc" },
	{ .compatible = "atmel,sama5d3-pmc" },
	{ .compatible = "atmel,sama5d2-pmc" },
	{ /* sentinel */ },
};

static void __init at91_pm_init(void (*pm_idle)(void))
{
	struct device_node *pmc_np;

	if (at91_cpuidle_device.dev.platform_data)
		platform_device_register(&at91_cpuidle_device);

	pmc_np = of_find_matching_node(NULL, atmel_pmc_ids);
	pmc = of_iomap(pmc_np, 0);
	if (!pmc) {
		pr_err("AT91: PM not supported, PMC not found\n");
		return;
	}

	if (pm_idle)
		arm_pm_idle = pm_idle;

	at91_pm_sram_init();

	if (at91_suspend_sram_fn)
		suspend_set_ops(&at91_pm_ops);
	else
		pr_info("AT91: PM not supported, due to no SRAM allocated\n");
}

void __init at91rm9200_pm_init(void)
{
	at91_dt_ramc();

	/*
	 * AT91RM9200 SDRAM low-power mode cannot be used with self-refresh.
	 */
	at91_ramc_write(0, AT91_MC_SDRAMC_LPR, 0);

	at91_pm_data.uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP;
	at91_pm_data.memctrl = AT91_MEMCTRL_MC;

	at91_pm_init(at91rm9200_idle);
}

void __init at91sam9260_pm_init(void)
{
	at91_dt_ramc();
	at91_pm_data.memctrl = AT91_MEMCTRL_SDRAMC;
	at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP;
	at91_pm_init(at91sam9_idle);
}

void __init at91sam9g45_pm_init(void)
{
	at91_dt_ramc();
	at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP;
	at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
	at91_pm_init(at91sam9_idle);
}

void __init at91sam9x5_pm_init(void)
{
	at91_dt_ramc();
	at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP;
	at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
	at91_pm_init(at91sam9_idle);
}

void __init sama5_pm_init(void)
{
	at91_dt_ramc();
	at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP;
	at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
	at91_pm_init(NULL);
}
Commit	Line	Data
907d6deb	1	/*
9d041268	2	* arch/arm/mach-at91/pm.c
907d6deb AV	3	* AT91 Power Management
	4	*
	5	* Copyright (C) 2005 David Brownell
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*/
	12
2f8163ba	13	#include <linux/gpio.h>
95d9ffbe	14	#include <linux/suspend.h>
907d6deb AV	15	#include <linux/sched.h>
907d6deb AV	16	#include <linux/proc_fs.h>
d2e46790	17	#include <linux/genalloc.h>
907d6deb AV	18	#include <linux/interrupt.h>
	19	#include <linux/sysfs.h>
	20	#include <linux/module.h>
f5598d34	21	#include <linux/of.h>
d2e46790	22	#include <linux/of_platform.h>
827de1f1	23	#include <linux/of_address.h>
907d6deb	24	#include <linux/platform_device.h>
fced80c7	25	#include <linux/io.h>
2edb90ae	26	#include <linux/clk/at91_pmc.h>
907d6deb	27
907d6deb	28	#include <asm/irq.h>
60063497	29	#include <linux/atomic.h>
907d6deb AV	30	#include <asm/mach/time.h>
907d6deb AV	31	#include <asm/mach/irq.h>
d94e688c	32	#include <asm/fncpy.h>
385acc0d	33	#include <asm/cacheflush.h>
fbc7edca	34	#include <asm/system_misc.h>
907d6deb	35
907d6deb	36	#include "generic.h"
1ea60cf7	37	#include "pm.h"
907d6deb	38
5737b73e AB	39	static void __iomem *pmc;
5737b73e AB	40
23b84082 AB	41	/*
	42	* FIXME: this is needed to communicate between the pinctrl driver and
	43	* the PM implementation in the machine. Possibly part of the PM
	44	* implementation should be moved down into the pinctrl driver and get
	45	* called as part of the generic suspend/resume path.
	46	*/
8423536f	47	#ifdef CONFIG_PINCTRL_AT91
23b84082 AB	48	extern void at91_pinctrl_gpio_suspend(void);
23b84082 AB	49	extern void at91_pinctrl_gpio_resume(void);
8423536f	50	#endif
23b84082	51
f5598d34 AB	52	static struct {
	53	unsigned long uhp_udp_mask;
	54	int memctrl;
	55	} at91_pm_data;
	56
827de1f1	57	void __iomem *at91_ramc_base[2];
5ad945ea	58
907d6deb AV	59	static int at91_pm_valid_state(suspend_state_t state)
	60	{
	61	switch (state) {
	62	case PM_SUSPEND_ON:
	63	case PM_SUSPEND_STANDBY:
	64	case PM_SUSPEND_MEM:
	65	return 1;
	66
	67	default:
	68	return 0;
	69	}
	70	}
	71
	72
	73	static suspend_state_t target_state;
	74
	75	/*
	76	* Called after processes are frozen, but before we shutdown devices.
	77	*/
c697eece	78	static int at91_pm_begin(suspend_state_t state)
907d6deb AV	79	{
	80	target_state = state;
	81	return 0;
	82	}
	83
	84	/*
	85	* Verify that all the clocks are correct before entering
	86	* slow-clock mode.
	87	*/
	88	static int at91_pm_verify_clocks(void)
	89	{
	90	unsigned long scsr;
	91	int i;
	92
5737b73e	93	scsr = readl(pmc + AT91_PMC_SCSR);
907d6deb AV	94
907d6deb AV	95	/* USB must not be using PLLB */
f5598d34 AB	96	if ((scsr & at91_pm_data.uhp_udp_mask) != 0) {
	97	pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
	98	return 0;
907d6deb AV	99	}
907d6deb AV	100
907d6deb AV	101	/* PCK0..PCK3 must be disabled, or configured to use clk32k */
	102	for (i = 0; i < 4; i++) {
	103	u32 css;
	104
	105	if ((scsr & (AT91_PMC_PCK0 << i)) == 0)
	106	continue;
5737b73e	107	css = readl(pmc + AT91_PMC_PCKR(i)) & AT91_PMC_CSS;
907d6deb	108	if (css != AT91_PMC_CSS_SLOW) {
7f96b1ca	109	pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css);
907d6deb AV	110	return 0;
	111	}
	112	}
907d6deb AV	113
	114	return 1;
	115	}
	116
	117	/*
	118	* Call this from platform driver suspend() to see how deeply to suspend.
	119	* For example, some controllers (like OHCI) need one of the PLL clocks
	120	* in order to act as a wakeup source, and those are not available when
	121	* going into slow clock mode.
	122	*
	123	* REVISIT: generalize as clk_will_be_available(clk)? Other platforms have
	124	* the very same problem (but not using at91 main_clk), and it'd be better
	125	* to add one generic API rather than lots of platform-specific ones.
	126	*/
	127	int at91_suspend_entering_slow_clock(void)
	128	{
	129	return (target_state == PM_SUSPEND_MEM);
	130	}
	131	EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
	132
5726a8b9	133	static void (at91_suspend_sram_fn)(void __iomem pmc, void __iomem *ramc0,
fb7e197b	134	void __iomem *ramc1, int memctrl);
907d6deb	135
5726a8b9	136	extern void at91_pm_suspend_in_sram(void __iomem pmc, void __iomem ramc0,
fb7e197b	137	void __iomem *ramc1, int memctrl);
5726a8b9	138	extern u32 at91_pm_suspend_in_sram_sz;
f5d0f457	139
23be4be5 WY	140	static void at91_pm_suspend(suspend_state_t state)
	141	{
	142	unsigned int pm_data = at91_pm_data.memctrl;
	143
	144	pm_data \|= (state == PM_SUSPEND_MEM) ?
	145	AT91_PM_MODE(AT91_PM_SLOW_CLOCK) : 0;
	146
385acc0d WY	147	flush_cache_all();
	148	outer_disable();
	149
5737b73e AB	150	at91_suspend_sram_fn(pmc, at91_ramc_base[0],
5737b73e AB	151	at91_ramc_base[1], pm_data);
385acc0d WY	152
385acc0d WY	153	outer_resume();
23be4be5 WY	154	}
23be4be5 WY	155
907d6deb AV	156	static int at91_pm_enter(suspend_state_t state)
907d6deb AV	157	{
8423536f	158	#ifdef CONFIG_PINCTRL_AT91
85c4b31e	159	at91_pinctrl_gpio_suspend();
8423536f	160	#endif
907d6deb	161	switch (state) {
23be4be5 WY	162	/*
	163	* Suspend-to-RAM is like STANDBY plus slow clock mode, so
	164	* drivers must suspend more deeply, the master clock switches
	165	* to the clk32k and turns off the main oscillator
	166	*/
	167	case PM_SUSPEND_MEM:
907d6deb	168	/*
23be4be5	169	* Ensure that clocks are in a valid state.
907d6deb	170	*/
23be4be5 WY	171	if (!at91_pm_verify_clocks())
23be4be5 WY	172	goto error;
907d6deb	173
23be4be5	174	at91_pm_suspend(state);
907d6deb	175
23be4be5	176	break;
907d6deb	177
23be4be5 WY	178	/*
	179	* STANDBY mode has all drivers suspended; ignores irqs not
	180	* marked as 'wakeup' event sources; and reduces DRAM power.
	181	* But otherwise it's identical to PM_SUSPEND_ON: cpu idle, and
	182	* nothing fancy done with main or cpu clocks.
	183	*/
	184	case PM_SUSPEND_STANDBY:
	185	at91_pm_suspend(state);
	186	break;
	187
	188	case PM_SUSPEND_ON:
	189	cpu_do_idle();
	190	break;
	191
	192	default:
	193	pr_debug("AT91: PM - bogus suspend state %d\n", state);
	194	goto error;
907d6deb AV	195	}
907d6deb AV	196
907d6deb AV	197	error:
907d6deb AV	198	target_state = PM_SUSPEND_ON;
07192604	199
8423536f	200	#ifdef CONFIG_PINCTRL_AT91
85c4b31e	201	at91_pinctrl_gpio_resume();
8423536f	202	#endif
907d6deb AV	203	return 0;
	204	}
	205
c697eece RW	206	/*
	207	* Called right prior to thawing processes.
	208	*/
	209	static void at91_pm_end(void)
	210	{
	211	target_state = PM_SUSPEND_ON;
	212	}
	213
907d6deb	214
2f55ac07	215	static const struct platform_suspend_ops at91_pm_ops = {
c697eece RW	216	.valid = at91_pm_valid_state,
	217	.begin = at91_pm_begin,
	218	.enter = at91_pm_enter,
	219	.end = at91_pm_end,
907d6deb AV	220	};
907d6deb AV	221
5ad945ea DL	222	static struct platform_device at91_cpuidle_device = {
	223	.name = "cpuidle-at91",
	224	};
	225
047794e1	226	static void at91_pm_set_standby(void (*at91_standby)(void))
5ad945ea	227	{
e32d995c	228	if (at91_standby)
5ad945ea	229	at91_cpuidle_device.dev.platform_data = at91_standby;
5ad945ea DL	230	}
5ad945ea DL	231
a18d0699 AB	232	/*
	233	* The AT91RM9200 goes into self-refresh mode with this command, and will
	234	* terminate self-refresh automatically on the next SDRAM access.
	235	*
	236	* Self-refresh mode is exited as soon as a memory access is made, but we don't
	237	* know for sure when that happens. However, we need to restore the low-power
	238	* mode if it was enabled before going idle. Restoring low-power mode while
	239	* still in self-refresh is "not recommended", but seems to work.
	240	*/
	241	static void at91rm9200_standby(void)
	242	{
d7d45f25	243	u32 lpr = at91_ramc_read(0, AT91_MC_SDRAMC_LPR);
a18d0699 AB	244
	245	asm volatile(
	246	"b 1f\n\t"
	247	".align 5\n\t"
	248	"1: mcr p15, 0, %0, c7, c10, 4\n\t"
	249	" str %0, [%1, %2]\n\t"
	250	" str %3, [%1, %4]\n\t"
	251	" mcr p15, 0, %0, c7, c0, 4\n\t"
	252	" str %5, [%1, %2]"
	253	:
d7d45f25 AB	254	: "r" (0), "r" (at91_ramc_base[0]), "r" (AT91_MC_SDRAMC_LPR),
d7d45f25 AB	255	"r" (1), "r" (AT91_MC_SDRAMC_SRR),
a18d0699 AB	256	"r" (lpr));
	257	}
	258
	259	/* We manage both DDRAM/SDRAM controllers, we need more than one value to
	260	* remember.
	261	*/
	262	static void at91_ddr_standby(void)
	263	{
	264	/* Those two values allow us to delay self-refresh activation
	265	* to the maximum. */
	266	u32 lpr0, lpr1 = 0;
	267	u32 saved_lpr0, saved_lpr1 = 0;
	268
	269	if (at91_ramc_base[1]) {
	270	saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
	271	lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
	272	lpr1 \|= AT91_DDRSDRC_LPCB_SELF_REFRESH;
	273	}
	274
	275	saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
	276	lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
	277	lpr0 \|= AT91_DDRSDRC_LPCB_SELF_REFRESH;
	278
	279	/* self-refresh mode now */
	280	at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
	281	if (at91_ramc_base[1])
	282	at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
	283
	284	cpu_do_idle();
	285
	286	at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
	287	if (at91_ramc_base[1])
	288	at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
	289	}
	290
	291	/* We manage both DDRAM/SDRAM controllers, we need more than one value to
	292	* remember.
	293	*/
	294	static void at91sam9_sdram_standby(void)
	295	{
	296	u32 lpr0, lpr1 = 0;
	297	u32 saved_lpr0, saved_lpr1 = 0;
	298
	299	if (at91_ramc_base[1]) {
	300	saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR);
	301	lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB;
	302	lpr1 \|= AT91_SDRAMC_LPCB_SELF_REFRESH;
	303	}
	304
	305	saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR);
	306	lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB;
	307	lpr0 \|= AT91_SDRAMC_LPCB_SELF_REFRESH;
	308
	309	/* self-refresh mode now */
	310	at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0);
	311	if (at91_ramc_base[1])
	312	at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1);
	313
	314	cpu_do_idle();
	315
	316	at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0);
	317	if (at91_ramc_base[1])
	318	at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);
	319	}
320
19c233b7	321	static const struct of_device_id const ramc_ids[] __initconst = {
827de1f1 AB	322	{ .compatible = "atmel,at91rm9200-sdramc", .data = at91rm9200_standby },
	323	{ .compatible = "atmel,at91sam9260-sdramc", .data = at91sam9_sdram_standby },
	324	{ .compatible = "atmel,at91sam9g45-ddramc", .data = at91_ddr_standby },
	325	{ .compatible = "atmel,sama5d3-ddramc", .data = at91_ddr_standby },
	326	{ /sentinel/ }
	327	};
	328
444d2d33	329	static __init void at91_dt_ramc(void)
827de1f1 AB	330	{
	331	struct device_node *np;
	332	const struct of_device_id *of_id;
	333	int idx = 0;
	334	const void *standby = NULL;
	335
	336	for_each_matching_node_and_match(np, ramc_ids, &of_id) {
	337	at91_ramc_base[idx] = of_iomap(np, 0);
	338	if (!at91_ramc_base[idx])
	339	panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx);
	340
	341	if (!standby)
	342	standby = of_id->data;
	343
	344	idx++;
	345	}
	346
	347	if (!idx)
	348	panic(pr_fmt("unable to find compatible ram controller node in dtb\n"));
	349
	350	if (!standby) {
	351	pr_warn("ramc no standby function available\n");
	352	return;
	353	}
	354
	355	at91_pm_set_standby(standby);
	356	}
	357
fbc7edca AB	358	void at91rm9200_idle(void)
	359	{
	360	/*
	361	* Disable the processor clock. The processor will be automatically
	362	* re-enabled by an interrupt or by a reset.
	363	*/
	364	writel(AT91_PMC_PCK, pmc + AT91_PMC_SCDR);
	365	}
	366
	367	void at91sam9_idle(void)
	368	{
	369	writel(AT91_PMC_PCK, pmc + AT91_PMC_SCDR);
	370	cpu_do_idle();
	371	}
	372
d2e46790 AB	373	static void __init at91_pm_sram_init(void)
	374	{
	375	struct gen_pool *sram_pool;
	376	phys_addr_t sram_pbase;
	377	unsigned long sram_base;
	378	struct device_node *node;
4a031f7d	379	struct platform_device *pdev = NULL;
d2e46790	380
4a031f7d AB	381	for_each_compatible_node(node, NULL, "mmio-sram") {
	382	pdev = of_find_device_by_node(node);
	383	if (pdev) {
	384	of_node_put(node);
	385	break;
	386	}
d2e46790 AB	387	}
d2e46790 AB	388
d2e46790 AB	389	if (!pdev) {
d2e46790 AB	390	pr_warn("%s: failed to find sram device!\n", __func__);
4a031f7d	391	return;
d2e46790 AB	392	}
d2e46790 AB	393
73858173	394	sram_pool = gen_pool_get(&pdev->dev, NULL);
d2e46790 AB	395	if (!sram_pool) {
d2e46790 AB	396	pr_warn("%s: sram pool unavailable!\n", __func__);
4a031f7d	397	return;
d2e46790 AB	398	}
d2e46790 AB	399
5726a8b9	400	sram_base = gen_pool_alloc(sram_pool, at91_pm_suspend_in_sram_sz);
d2e46790	401	if (!sram_base) {
5726a8b9	402	pr_warn("%s: unable to alloc sram!\n", __func__);
4a031f7d	403	return;
d2e46790 AB	404	}
	405
	406	sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base);
5726a8b9 WY	407	at91_suspend_sram_fn = __arm_ioremap_exec(sram_pbase,
	408	at91_pm_suspend_in_sram_sz, false);
	409	if (!at91_suspend_sram_fn) {
d94e688c WY	410	pr_warn("SRAM: Could not map\n");
	411	return;
	412	}
	413
5726a8b9 WY	414	/* Copy the pm suspend handler to SRAM */
	415	at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn,
	416	&at91_pm_suspend_in_sram, at91_pm_suspend_in_sram_sz);
d2e46790	417	}
d2e46790	418
5737b73e AB	419	static const struct of_device_id atmel_pmc_ids[] __initconst = {
	420	{ .compatible = "atmel,at91rm9200-pmc" },
	421	{ .compatible = "atmel,at91sam9260-pmc" },
	422	{ .compatible = "atmel,at91sam9g45-pmc" },
	423	{ .compatible = "atmel,at91sam9n12-pmc" },
	424	{ .compatible = "atmel,at91sam9x5-pmc" },
	425	{ .compatible = "atmel,sama5d3-pmc" },
	426	{ .compatible = "atmel,sama5d2-pmc" },
	427	{ /* sentinel */ },
	428	};
	429
fbc7edca	430	static void __init at91_pm_init(void (*pm_idle)(void))
907d6deb	431	{
5737b73e	432	struct device_node *pmc_np;
f5d0f457	433
5ad945ea DL	434	if (at91_cpuidle_device.dev.platform_data)
5ad945ea DL	435	platform_device_register(&at91_cpuidle_device);
907d6deb	436
5737b73e AB	437	pmc_np = of_find_matching_node(NULL, atmel_pmc_ids);
	438	pmc = of_iomap(pmc_np, 0);
	439	if (!pmc) {
	440	pr_err("AT91: PM not supported, PMC not found\n");
	441	return;
	442	}
	443
fbc7edca AB	444	if (pm_idle)
	445	arm_pm_idle = pm_idle;
	446
5737b73e AB	447	at91_pm_sram_init();
5737b73e AB	448
5726a8b9	449	if (at91_suspend_sram_fn)
d94e688c WY	450	suspend_set_ops(&at91_pm_ops);
	451	else
	452	pr_info("AT91: PM not supported, due to no SRAM allocated\n");
4db0ba22	453	}
907d6deb	454
ad3fc3e3	455	void __init at91rm9200_pm_init(void)
4db0ba22	456	{
827de1f1 AB	457	at91_dt_ramc();
827de1f1 AB	458
4db0ba22 AB	459	/*
	460	* AT91RM9200 SDRAM low-power mode cannot be used with self-refresh.
	461	*/
d7d45f25	462	at91_ramc_write(0, AT91_MC_SDRAMC_LPR, 0);
4db0ba22 AB	463
	464	at91_pm_data.uhp_udp_mask = AT91RM9200_PMC_UHP \| AT91RM9200_PMC_UDP;
	465	at91_pm_data.memctrl = AT91_MEMCTRL_MC;
	466
fbc7edca	467	at91_pm_init(at91rm9200_idle);
4db0ba22 AB	468	}
4db0ba22 AB	469
ad3fc3e3	470	void __init at91sam9260_pm_init(void)
4db0ba22	471	{
827de1f1	472	at91_dt_ramc();
4db0ba22 AB	473	at91_pm_data.memctrl = AT91_MEMCTRL_SDRAMC;
4db0ba22 AB	474	at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP \| AT91SAM926x_PMC_UDP;
fbc7edca	475	at91_pm_init(at91sam9_idle);
4db0ba22 AB	476	}
4db0ba22 AB	477
ad3fc3e3	478	void __init at91sam9g45_pm_init(void)
4db0ba22	479	{
827de1f1	480	at91_dt_ramc();
4db0ba22 AB	481	at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP;
4db0ba22 AB	482	at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
fbc7edca	483	at91_pm_init(at91sam9_idle);
907d6deb	484	}
bf02280e	485
ad3fc3e3	486	void __init at91sam9x5_pm_init(void)
bf02280e	487	{
827de1f1	488	at91_dt_ramc();
bf02280e NF	489	at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP \| AT91SAM926x_PMC_UDP;
bf02280e NF	490	at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
fbc7edca AB	491	at91_pm_init(at91sam9_idle);
	492	}
	493
	494	void __init sama5_pm_init(void)
	495	{
	496	at91_dt_ramc();
	497	at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP \| AT91SAM926x_PMC_UDP;
	498	at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
	499	at91_pm_init(NULL);
bf02280e	500	}