Commit | Line | Data |
---|---|---|
907d6deb | 1 | /* |
9d041268 | 2 | * arch/arm/mach-at91/pm.c |
907d6deb AV |
3 | * AT91 Power Management |
4 | * | |
5 | * Copyright (C) 2005 David Brownell | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | */ | |
12 | ||
2f8163ba | 13 | #include <linux/gpio.h> |
95d9ffbe | 14 | #include <linux/suspend.h> |
907d6deb AV |
15 | #include <linux/sched.h> |
16 | #include <linux/proc_fs.h> | |
907d6deb AV |
17 | #include <linux/interrupt.h> |
18 | #include <linux/sysfs.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/platform_device.h> | |
fced80c7 | 21 | #include <linux/io.h> |
907d6deb | 22 | |
907d6deb | 23 | #include <asm/irq.h> |
60063497 | 24 | #include <linux/atomic.h> |
907d6deb AV |
25 | #include <asm/mach/time.h> |
26 | #include <asm/mach/irq.h> | |
907d6deb | 27 | |
a09e64fb | 28 | #include <mach/at91_pmc.h> |
a09e64fb | 29 | #include <mach/cpu.h> |
907d6deb AV |
30 | |
31 | #include "generic.h" | |
1ea60cf7 | 32 | #include "pm.h" |
907d6deb | 33 | |
565ac445 AV |
34 | /* |
35 | * Show the reason for the previous system reset. | |
36 | */ | |
565ac445 | 37 | |
a09e64fb RK |
38 | #include <mach/at91_rstc.h> |
39 | #include <mach/at91_shdwc.h> | |
565ac445 AV |
40 | |
41 | static void __init show_reset_status(void) | |
42 | { | |
43 | static char reset[] __initdata = "reset"; | |
44 | ||
45 | static char general[] __initdata = "general"; | |
46 | static char wakeup[] __initdata = "wakeup"; | |
47 | static char watchdog[] __initdata = "watchdog"; | |
48 | static char software[] __initdata = "software"; | |
49 | static char user[] __initdata = "user"; | |
50 | static char unknown[] __initdata = "unknown"; | |
51 | ||
52 | static char signal[] __initdata = "signal"; | |
53 | static char rtc[] __initdata = "rtc"; | |
54 | static char rtt[] __initdata = "rtt"; | |
55 | static char restore[] __initdata = "power-restored"; | |
56 | ||
57 | char *reason, *r2 = reset; | |
58 | u32 reset_type, wake_type; | |
59 | ||
e9f68b5c | 60 | if (!at91_shdwc_base || !at91_rstc_base) |
f22deee5 JCPV |
61 | return; |
62 | ||
e9f68b5c | 63 | reset_type = at91_rstc_read(AT91_RSTC_SR) & AT91_RSTC_RSTTYP; |
f22deee5 | 64 | wake_type = at91_shdwc_read(AT91_SHDW_SR); |
565ac445 AV |
65 | |
66 | switch (reset_type) { | |
67 | case AT91_RSTC_RSTTYP_GENERAL: | |
68 | reason = general; | |
69 | break; | |
70 | case AT91_RSTC_RSTTYP_WAKEUP: | |
71 | /* board-specific code enabled the wakeup sources */ | |
72 | reason = wakeup; | |
73 | ||
74 | /* "wakeup signal" */ | |
75 | if (wake_type & AT91_SHDW_WAKEUP0) | |
76 | r2 = signal; | |
77 | else { | |
78 | r2 = reason; | |
79 | if (wake_type & AT91_SHDW_RTTWK) /* rtt wakeup */ | |
80 | reason = rtt; | |
81 | else if (wake_type & AT91_SHDW_RTCWK) /* rtc wakeup */ | |
82 | reason = rtc; | |
83 | else if (wake_type == 0) /* power-restored wakeup */ | |
84 | reason = restore; | |
85 | else /* unknown wakeup */ | |
86 | reason = unknown; | |
87 | } | |
88 | break; | |
89 | case AT91_RSTC_RSTTYP_WATCHDOG: | |
90 | reason = watchdog; | |
91 | break; | |
92 | case AT91_RSTC_RSTTYP_SOFTWARE: | |
93 | reason = software; | |
94 | break; | |
95 | case AT91_RSTC_RSTTYP_USER: | |
96 | reason = user; | |
97 | break; | |
98 | default: | |
99 | reason = unknown; | |
100 | break; | |
101 | } | |
102 | pr_info("AT91: Starting after %s %s\n", reason, r2); | |
103 | } | |
565ac445 | 104 | |
907d6deb AV |
105 | static int at91_pm_valid_state(suspend_state_t state) |
106 | { | |
107 | switch (state) { | |
108 | case PM_SUSPEND_ON: | |
109 | case PM_SUSPEND_STANDBY: | |
110 | case PM_SUSPEND_MEM: | |
111 | return 1; | |
112 | ||
113 | default: | |
114 | return 0; | |
115 | } | |
116 | } | |
117 | ||
118 | ||
119 | static suspend_state_t target_state; | |
120 | ||
121 | /* | |
122 | * Called after processes are frozen, but before we shutdown devices. | |
123 | */ | |
c697eece | 124 | static int at91_pm_begin(suspend_state_t state) |
907d6deb AV |
125 | { |
126 | target_state = state; | |
127 | return 0; | |
128 | } | |
129 | ||
130 | /* | |
131 | * Verify that all the clocks are correct before entering | |
132 | * slow-clock mode. | |
133 | */ | |
134 | static int at91_pm_verify_clocks(void) | |
135 | { | |
136 | unsigned long scsr; | |
137 | int i; | |
138 | ||
139 | scsr = at91_sys_read(AT91_PMC_SCSR); | |
140 | ||
141 | /* USB must not be using PLLB */ | |
d481f864 AV |
142 | if (cpu_is_at91rm9200()) { |
143 | if ((scsr & (AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP)) != 0) { | |
7f96b1ca | 144 | pr_err("AT91: PM - Suspend-to-RAM with USB still active\n"); |
d481f864 AV |
145 | return 0; |
146 | } | |
b319ff80 NF |
147 | } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || cpu_is_at91sam9263() |
148 | || cpu_is_at91sam9g20() || cpu_is_at91sam9g10()) { | |
b6b27ae5 | 149 | if ((scsr & (AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP)) != 0) { |
7f96b1ca | 150 | pr_err("AT91: PM - Suspend-to-RAM with USB still active\n"); |
b6b27ae5 AV |
151 | return 0; |
152 | } | |
907d6deb AV |
153 | } |
154 | ||
155 | #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS | |
156 | /* PCK0..PCK3 must be disabled, or configured to use clk32k */ | |
157 | for (i = 0; i < 4; i++) { | |
158 | u32 css; | |
159 | ||
160 | if ((scsr & (AT91_PMC_PCK0 << i)) == 0) | |
161 | continue; | |
162 | ||
163 | css = at91_sys_read(AT91_PMC_PCKR(i)) & AT91_PMC_CSS; | |
164 | if (css != AT91_PMC_CSS_SLOW) { | |
7f96b1ca | 165 | pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css); |
907d6deb AV |
166 | return 0; |
167 | } | |
168 | } | |
169 | #endif | |
170 | ||
171 | return 1; | |
172 | } | |
173 | ||
174 | /* | |
175 | * Call this from platform driver suspend() to see how deeply to suspend. | |
176 | * For example, some controllers (like OHCI) need one of the PLL clocks | |
177 | * in order to act as a wakeup source, and those are not available when | |
178 | * going into slow clock mode. | |
179 | * | |
180 | * REVISIT: generalize as clk_will_be_available(clk)? Other platforms have | |
181 | * the very same problem (but not using at91 main_clk), and it'd be better | |
182 | * to add one generic API rather than lots of platform-specific ones. | |
183 | */ | |
184 | int at91_suspend_entering_slow_clock(void) | |
185 | { | |
186 | return (target_state == PM_SUSPEND_MEM); | |
187 | } | |
188 | EXPORT_SYMBOL(at91_suspend_entering_slow_clock); | |
189 | ||
190 | ||
191 | static void (*slow_clock)(void); | |
192 | ||
f5d0f457 AV |
193 | #ifdef CONFIG_AT91_SLOW_CLOCK |
194 | extern void at91_slow_clock(void); | |
195 | extern u32 at91_slow_clock_sz; | |
196 | #endif | |
197 | ||
907d6deb | 198 | |
907d6deb AV |
199 | static int at91_pm_enter(suspend_state_t state) |
200 | { | |
201 | at91_gpio_suspend(); | |
202 | at91_irq_suspend(); | |
203 | ||
204 | pr_debug("AT91: PM - wake mask %08x, pm state %d\n", | |
205 | /* remember all the always-wake irqs */ | |
206 | (at91_sys_read(AT91_PMC_PCSR) | |
207 | | (1 << AT91_ID_FIQ) | |
208 | | (1 << AT91_ID_SYS) | |
1f4fd0a0 | 209 | | (at91_extern_irq)) |
be6d4321 | 210 | & at91_aic_read(AT91_AIC_IMR), |
907d6deb AV |
211 | state); |
212 | ||
213 | switch (state) { | |
214 | /* | |
215 | * Suspend-to-RAM is like STANDBY plus slow clock mode, so | |
216 | * drivers must suspend more deeply: only the master clock | |
217 | * controller may be using the main oscillator. | |
218 | */ | |
219 | case PM_SUSPEND_MEM: | |
220 | /* | |
221 | * Ensure that clocks are in a valid state. | |
222 | */ | |
223 | if (!at91_pm_verify_clocks()) | |
224 | goto error; | |
225 | ||
226 | /* | |
227 | * Enter slow clock mode by switching over to clk32k and | |
228 | * turning off the main oscillator; reverse on wakeup. | |
229 | */ | |
230 | if (slow_clock) { | |
f5d0f457 AV |
231 | #ifdef CONFIG_AT91_SLOW_CLOCK |
232 | /* copy slow_clock handler to SRAM, and call it */ | |
233 | memcpy(slow_clock, at91_slow_clock, at91_slow_clock_sz); | |
234 | #endif | |
907d6deb AV |
235 | slow_clock(); |
236 | break; | |
237 | } else { | |
f5d0f457 | 238 | pr_info("AT91: PM - no slow clock mode enabled ...\n"); |
907d6deb AV |
239 | /* FALLTHROUGH leaving master clock alone */ |
240 | } | |
241 | ||
242 | /* | |
243 | * STANDBY mode has *all* drivers suspended; ignores irqs not | |
244 | * marked as 'wakeup' event sources; and reduces DRAM power. | |
245 | * But otherwise it's identical to PM_SUSPEND_ON: cpu idle, and | |
246 | * nothing fancy done with main or cpu clocks. | |
247 | */ | |
248 | case PM_SUSPEND_STANDBY: | |
249 | /* | |
250 | * NOTE: the Wait-for-Interrupt instruction needs to be | |
f5d0f457 AV |
251 | * in icache so no SDRAM accesses are needed until the |
252 | * wakeup IRQ occurs and self-refresh is terminated. | |
8aeeda82 NF |
253 | * For ARM 926 based chips, this requirement is weaker |
254 | * as at91sam9 can access a RAM in self-refresh mode. | |
907d6deb | 255 | */ |
00482a40 | 256 | at91_standby(); |
f5d0f457 | 257 | break; |
907d6deb AV |
258 | |
259 | case PM_SUSPEND_ON: | |
8aeeda82 | 260 | cpu_do_idle(); |
907d6deb AV |
261 | break; |
262 | ||
263 | default: | |
264 | pr_debug("AT91: PM - bogus suspend state %d\n", state); | |
265 | goto error; | |
266 | } | |
267 | ||
268 | pr_debug("AT91: PM - wakeup %08x\n", | |
be6d4321 | 269 | at91_aic_read(AT91_AIC_IPR) & at91_aic_read(AT91_AIC_IMR)); |
907d6deb AV |
270 | |
271 | error: | |
272 | target_state = PM_SUSPEND_ON; | |
273 | at91_irq_resume(); | |
274 | at91_gpio_resume(); | |
275 | return 0; | |
276 | } | |
277 | ||
c697eece RW |
278 | /* |
279 | * Called right prior to thawing processes. | |
280 | */ | |
281 | static void at91_pm_end(void) | |
282 | { | |
283 | target_state = PM_SUSPEND_ON; | |
284 | } | |
285 | ||
907d6deb | 286 | |
2f55ac07 | 287 | static const struct platform_suspend_ops at91_pm_ops = { |
c697eece RW |
288 | .valid = at91_pm_valid_state, |
289 | .begin = at91_pm_begin, | |
290 | .enter = at91_pm_enter, | |
291 | .end = at91_pm_end, | |
907d6deb AV |
292 | }; |
293 | ||
294 | static int __init at91_pm_init(void) | |
295 | { | |
f5d0f457 AV |
296 | #ifdef CONFIG_AT91_SLOW_CLOCK |
297 | slow_clock = (void *) (AT91_IO_VIRT_BASE - at91_slow_clock_sz); | |
907d6deb AV |
298 | #endif |
299 | ||
f5d0f457 AV |
300 | pr_info("AT91: Power Management%s\n", (slow_clock ? " (with slow clock mode)" : "")); |
301 | ||
302 | #ifdef CONFIG_ARCH_AT91RM9200 | |
303 | /* AT91RM9200 SDRAM low-power mode cannot be used with self-refresh. */ | |
907d6deb | 304 | at91_sys_write(AT91_SDRAMC_LPR, 0); |
f5d0f457 | 305 | #endif |
907d6deb | 306 | |
26398a70 | 307 | suspend_set_ops(&at91_pm_ops); |
907d6deb | 308 | |
565ac445 | 309 | show_reset_status(); |
907d6deb AV |
310 | return 0; |
311 | } | |
312 | arch_initcall(at91_pm_init); |