ARM: at91: remove SoC headers
[deliverable/linux.git] / arch / arm / mach-at91 / pm.c
CommitLineData
907d6deb 1/*
9d041268 2 * arch/arm/mach-at91/pm.c
907d6deb
AV
3 * AT91 Power Management
4 *
5 * Copyright (C) 2005 David Brownell
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
2f8163ba 13#include <linux/gpio.h>
95d9ffbe 14#include <linux/suspend.h>
907d6deb
AV
15#include <linux/sched.h>
16#include <linux/proc_fs.h>
d2e46790 17#include <linux/genalloc.h>
907d6deb
AV
18#include <linux/interrupt.h>
19#include <linux/sysfs.h>
20#include <linux/module.h>
f5598d34 21#include <linux/of.h>
d2e46790 22#include <linux/of_platform.h>
827de1f1 23#include <linux/of_address.h>
907d6deb 24#include <linux/platform_device.h>
fced80c7 25#include <linux/io.h>
2edb90ae 26#include <linux/clk/at91_pmc.h>
907d6deb 27
907d6deb 28#include <asm/irq.h>
60063497 29#include <linux/atomic.h>
907d6deb
AV
30#include <asm/mach/time.h>
31#include <asm/mach/irq.h>
d94e688c 32#include <asm/fncpy.h>
385acc0d 33#include <asm/cacheflush.h>
907d6deb 34
ac11a1d4 35#include <mach/hardware.h>
907d6deb
AV
36
37#include "generic.h"
1ea60cf7 38#include "pm.h"
907d6deb 39
f5598d34
AB
40static struct {
41 unsigned long uhp_udp_mask;
42 int memctrl;
43} at91_pm_data;
44
827de1f1 45void __iomem *at91_ramc_base[2];
5ad945ea 46
907d6deb
AV
47static int at91_pm_valid_state(suspend_state_t state)
48{
49 switch (state) {
50 case PM_SUSPEND_ON:
51 case PM_SUSPEND_STANDBY:
52 case PM_SUSPEND_MEM:
53 return 1;
54
55 default:
56 return 0;
57 }
58}
59
60
61static suspend_state_t target_state;
62
63/*
64 * Called after processes are frozen, but before we shutdown devices.
65 */
c697eece 66static int at91_pm_begin(suspend_state_t state)
907d6deb
AV
67{
68 target_state = state;
69 return 0;
70}
71
72/*
73 * Verify that all the clocks are correct before entering
74 * slow-clock mode.
75 */
76static int at91_pm_verify_clocks(void)
77{
78 unsigned long scsr;
79 int i;
80
b5514952 81 scsr = at91_pmc_read(AT91_PMC_SCSR);
907d6deb
AV
82
83 /* USB must not be using PLLB */
f5598d34
AB
84 if ((scsr & at91_pm_data.uhp_udp_mask) != 0) {
85 pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
86 return 0;
907d6deb
AV
87 }
88
907d6deb
AV
89 /* PCK0..PCK3 must be disabled, or configured to use clk32k */
90 for (i = 0; i < 4; i++) {
91 u32 css;
92
93 if ((scsr & (AT91_PMC_PCK0 << i)) == 0)
94 continue;
95
b5514952 96 css = at91_pmc_read(AT91_PMC_PCKR(i)) & AT91_PMC_CSS;
907d6deb 97 if (css != AT91_PMC_CSS_SLOW) {
7f96b1ca 98 pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css);
907d6deb
AV
99 return 0;
100 }
101 }
907d6deb
AV
102
103 return 1;
104}
105
106/*
107 * Call this from platform driver suspend() to see how deeply to suspend.
108 * For example, some controllers (like OHCI) need one of the PLL clocks
109 * in order to act as a wakeup source, and those are not available when
110 * going into slow clock mode.
111 *
112 * REVISIT: generalize as clk_will_be_available(clk)? Other platforms have
113 * the very same problem (but not using at91 main_clk), and it'd be better
114 * to add one generic API rather than lots of platform-specific ones.
115 */
116int at91_suspend_entering_slow_clock(void)
117{
118 return (target_state == PM_SUSPEND_MEM);
119}
120EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
121
5726a8b9 122static void (*at91_suspend_sram_fn)(void __iomem *pmc, void __iomem *ramc0,
fb7e197b 123 void __iomem *ramc1, int memctrl);
907d6deb 124
5726a8b9 125extern void at91_pm_suspend_in_sram(void __iomem *pmc, void __iomem *ramc0,
fb7e197b 126 void __iomem *ramc1, int memctrl);
5726a8b9 127extern u32 at91_pm_suspend_in_sram_sz;
f5d0f457 128
23be4be5
WY
129static void at91_pm_suspend(suspend_state_t state)
130{
131 unsigned int pm_data = at91_pm_data.memctrl;
132
133 pm_data |= (state == PM_SUSPEND_MEM) ?
134 AT91_PM_MODE(AT91_PM_SLOW_CLOCK) : 0;
135
385acc0d
WY
136 flush_cache_all();
137 outer_disable();
138
5726a8b9
WY
139 at91_suspend_sram_fn(at91_pmc_base, at91_ramc_base[0],
140 at91_ramc_base[1], pm_data);
385acc0d
WY
141
142 outer_resume();
23be4be5
WY
143}
144
907d6deb
AV
145static int at91_pm_enter(suspend_state_t state)
146{
85c4b31e 147 at91_pinctrl_gpio_suspend();
907d6deb 148
907d6deb 149 switch (state) {
23be4be5
WY
150 /*
151 * Suspend-to-RAM is like STANDBY plus slow clock mode, so
152 * drivers must suspend more deeply, the master clock switches
153 * to the clk32k and turns off the main oscillator
154 */
155 case PM_SUSPEND_MEM:
907d6deb 156 /*
23be4be5 157 * Ensure that clocks are in a valid state.
907d6deb 158 */
23be4be5
WY
159 if (!at91_pm_verify_clocks())
160 goto error;
907d6deb 161
23be4be5 162 at91_pm_suspend(state);
907d6deb 163
23be4be5 164 break;
907d6deb 165
23be4be5
WY
166 /*
167 * STANDBY mode has *all* drivers suspended; ignores irqs not
168 * marked as 'wakeup' event sources; and reduces DRAM power.
169 * But otherwise it's identical to PM_SUSPEND_ON: cpu idle, and
170 * nothing fancy done with main or cpu clocks.
171 */
172 case PM_SUSPEND_STANDBY:
173 at91_pm_suspend(state);
174 break;
175
176 case PM_SUSPEND_ON:
177 cpu_do_idle();
178 break;
179
180 default:
181 pr_debug("AT91: PM - bogus suspend state %d\n", state);
182 goto error;
907d6deb
AV
183 }
184
907d6deb
AV
185error:
186 target_state = PM_SUSPEND_ON;
07192604 187
85c4b31e 188 at91_pinctrl_gpio_resume();
907d6deb
AV
189 return 0;
190}
191
c697eece
RW
192/*
193 * Called right prior to thawing processes.
194 */
195static void at91_pm_end(void)
196{
197 target_state = PM_SUSPEND_ON;
198}
199
907d6deb 200
2f55ac07 201static const struct platform_suspend_ops at91_pm_ops = {
c697eece
RW
202 .valid = at91_pm_valid_state,
203 .begin = at91_pm_begin,
204 .enter = at91_pm_enter,
205 .end = at91_pm_end,
907d6deb
AV
206};
207
5ad945ea
DL
208static struct platform_device at91_cpuidle_device = {
209 .name = "cpuidle-at91",
210};
211
047794e1 212static void at91_pm_set_standby(void (*at91_standby)(void))
5ad945ea 213{
e32d995c 214 if (at91_standby)
5ad945ea 215 at91_cpuidle_device.dev.platform_data = at91_standby;
5ad945ea
DL
216}
217
444d2d33 218static const struct of_device_id ramc_ids[] __initconst = {
827de1f1
AB
219 { .compatible = "atmel,at91rm9200-sdramc", .data = at91rm9200_standby },
220 { .compatible = "atmel,at91sam9260-sdramc", .data = at91sam9_sdram_standby },
221 { .compatible = "atmel,at91sam9g45-ddramc", .data = at91_ddr_standby },
222 { .compatible = "atmel,sama5d3-ddramc", .data = at91_ddr_standby },
223 { /*sentinel*/ }
224};
225
444d2d33 226static __init void at91_dt_ramc(void)
827de1f1
AB
227{
228 struct device_node *np;
229 const struct of_device_id *of_id;
230 int idx = 0;
231 const void *standby = NULL;
232
233 for_each_matching_node_and_match(np, ramc_ids, &of_id) {
234 at91_ramc_base[idx] = of_iomap(np, 0);
235 if (!at91_ramc_base[idx])
236 panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx);
237
238 if (!standby)
239 standby = of_id->data;
240
241 idx++;
242 }
243
244 if (!idx)
245 panic(pr_fmt("unable to find compatible ram controller node in dtb\n"));
246
247 if (!standby) {
248 pr_warn("ramc no standby function available\n");
249 return;
250 }
251
252 at91_pm_set_standby(standby);
253}
254
d2e46790
AB
255static void __init at91_pm_sram_init(void)
256{
257 struct gen_pool *sram_pool;
258 phys_addr_t sram_pbase;
259 unsigned long sram_base;
260 struct device_node *node;
4a031f7d 261 struct platform_device *pdev = NULL;
d2e46790 262
4a031f7d
AB
263 for_each_compatible_node(node, NULL, "mmio-sram") {
264 pdev = of_find_device_by_node(node);
265 if (pdev) {
266 of_node_put(node);
267 break;
268 }
d2e46790
AB
269 }
270
d2e46790
AB
271 if (!pdev) {
272 pr_warn("%s: failed to find sram device!\n", __func__);
4a031f7d 273 return;
d2e46790
AB
274 }
275
276 sram_pool = dev_get_gen_pool(&pdev->dev);
277 if (!sram_pool) {
278 pr_warn("%s: sram pool unavailable!\n", __func__);
4a031f7d 279 return;
d2e46790
AB
280 }
281
5726a8b9 282 sram_base = gen_pool_alloc(sram_pool, at91_pm_suspend_in_sram_sz);
d2e46790 283 if (!sram_base) {
5726a8b9 284 pr_warn("%s: unable to alloc sram!\n", __func__);
4a031f7d 285 return;
d2e46790
AB
286 }
287
288 sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base);
5726a8b9
WY
289 at91_suspend_sram_fn = __arm_ioremap_exec(sram_pbase,
290 at91_pm_suspend_in_sram_sz, false);
291 if (!at91_suspend_sram_fn) {
d94e688c
WY
292 pr_warn("SRAM: Could not map\n");
293 return;
294 }
295
5726a8b9
WY
296 /* Copy the pm suspend handler to SRAM */
297 at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn,
298 &at91_pm_suspend_in_sram, at91_pm_suspend_in_sram_sz);
d2e46790 299}
d2e46790 300
4db0ba22 301static void __init at91_pm_init(void)
907d6deb 302{
d2e46790 303 at91_pm_sram_init();
f5d0f457 304
5ad945ea
DL
305 if (at91_cpuidle_device.dev.platform_data)
306 platform_device_register(&at91_cpuidle_device);
907d6deb 307
5726a8b9 308 if (at91_suspend_sram_fn)
d94e688c
WY
309 suspend_set_ops(&at91_pm_ops);
310 else
311 pr_info("AT91: PM not supported, due to no SRAM allocated\n");
4db0ba22 312}
907d6deb 313
ad3fc3e3 314void __init at91rm9200_pm_init(void)
4db0ba22 315{
827de1f1
AB
316 at91_dt_ramc();
317
4db0ba22
AB
318 /*
319 * AT91RM9200 SDRAM low-power mode cannot be used with self-refresh.
320 */
321 at91_ramc_write(0, AT91RM9200_SDRAMC_LPR, 0);
322
323 at91_pm_data.uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP;
324 at91_pm_data.memctrl = AT91_MEMCTRL_MC;
325
326 at91_pm_init();
327}
328
ad3fc3e3 329void __init at91sam9260_pm_init(void)
4db0ba22 330{
827de1f1 331 at91_dt_ramc();
4db0ba22
AB
332 at91_pm_data.memctrl = AT91_MEMCTRL_SDRAMC;
333 at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP;
334 return at91_pm_init();
335}
336
ad3fc3e3 337void __init at91sam9g45_pm_init(void)
4db0ba22 338{
827de1f1 339 at91_dt_ramc();
4db0ba22
AB
340 at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP;
341 at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
342 return at91_pm_init();
907d6deb 343}
bf02280e 344
ad3fc3e3 345void __init at91sam9x5_pm_init(void)
bf02280e 346{
827de1f1 347 at91_dt_ramc();
bf02280e
NF
348 at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP;
349 at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
350 return at91_pm_init();
351}
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