[deliverable/linux.git] / arch / arm / mach-at91 / pm.c

/*
 * arch/arm/mach-at91/pm.c
 * AT91 Power Management
 *
 * Copyright (C) 2005 David Brownell
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/gpio.h>
#include <linux/suspend.h>
#include <linux/sched.h>
#include <linux/proc_fs.h>
#include <linux/genalloc.h>
#include <linux/interrupt.h>
#include <linux/sysfs.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/clk/at91_pmc.h>

#include <asm/irq.h>
#include <linux/atomic.h>
#include <asm/mach/time.h>
#include <asm/mach/irq.h>

#include <mach/cpu.h>
#include <mach/hardware.h>

#include "generic.h"
#include "pm.h"

static struct {
	unsigned long uhp_udp_mask;
	int memctrl;
} at91_pm_data;

static void (*at91_pm_standby)(void);
void __iomem *at91_ramc_base[2];

static int at91_pm_valid_state(suspend_state_t state)
{
	switch (state) {
		case PM_SUSPEND_ON:
		case PM_SUSPEND_STANDBY:
		case PM_SUSPEND_MEM:
			return 1;

		default:
			return 0;
	}
}


static suspend_state_t target_state;

/*
 * Called after processes are frozen, but before we shutdown devices.
 */
static int at91_pm_begin(suspend_state_t state)
{
	target_state = state;
	return 0;
}

/*
 * Verify that all the clocks are correct before entering
 * slow-clock mode.
 */
static int at91_pm_verify_clocks(void)
{
	unsigned long scsr;
	int i;

	scsr = at91_pmc_read(AT91_PMC_SCSR);

	/* USB must not be using PLLB */
	if ((scsr & at91_pm_data.uhp_udp_mask) != 0) {
		pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
		return 0;
	}

	/* PCK0..PCK3 must be disabled, or configured to use clk32k */
	for (i = 0; i < 4; i++) {
		u32 css;

		if ((scsr & (AT91_PMC_PCK0 << i)) == 0)
			continue;

		css = at91_pmc_read(AT91_PMC_PCKR(i)) & AT91_PMC_CSS;
		if (css != AT91_PMC_CSS_SLOW) {
			pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css);
			return 0;
		}
	}

	return 1;
}

/*
 * Call this from platform driver suspend() to see how deeply to suspend.
 * For example, some controllers (like OHCI) need one of the PLL clocks
 * in order to act as a wakeup source, and those are not available when
 * going into slow clock mode.
 *
 * REVISIT: generalize as clk_will_be_available(clk)?  Other platforms have
 * the very same problem (but not using at91 main_clk), and it'd be better
 * to add one generic API rather than lots of platform-specific ones.
 */
int at91_suspend_entering_slow_clock(void)
{
	return (target_state == PM_SUSPEND_MEM);
}
EXPORT_SYMBOL(at91_suspend_entering_slow_clock);


static void (*slow_clock)(void __iomem *pmc, void __iomem *ramc0,
			  void __iomem *ramc1, int memctrl);

#ifdef CONFIG_AT91_SLOW_CLOCK
extern void at91_slow_clock(void __iomem *pmc, void __iomem *ramc0,
			    void __iomem *ramc1, int memctrl);
extern u32 at91_slow_clock_sz;
#endif

static int at91_pm_enter(suspend_state_t state)
{
	at91_pinctrl_gpio_suspend();

	switch (state) {
		/*
		 * Suspend-to-RAM is like STANDBY plus slow clock mode, so
		 * drivers must suspend more deeply:  only the master clock
		 * controller may be using the main oscillator.
		 */
		case PM_SUSPEND_MEM:
			/*
			 * Ensure that clocks are in a valid state.
			 */
			if (!at91_pm_verify_clocks())
				goto error;

			/*
			 * Enter slow clock mode by switching over to clk32k and
			 * turning off the main oscillator; reverse on wakeup.
			 */
			if (slow_clock) {
#ifdef CONFIG_AT91_SLOW_CLOCK
				/* copy slow_clock handler to SRAM, and call it */
				memcpy(slow_clock, at91_slow_clock, at91_slow_clock_sz);
#endif
				slow_clock(at91_pmc_base, at91_ramc_base[0],
					   at91_ramc_base[1],
					   at91_pm_data.memctrl);
				break;
			} else {
				pr_info("AT91: PM - no slow clock mode enabled ...\n");
				/* FALLTHROUGH leaving master clock alone */
			}

		/*
		 * STANDBY mode has *all* drivers suspended; ignores irqs not
		 * marked as 'wakeup' event sources; and reduces DRAM power.
		 * But otherwise it's identical to PM_SUSPEND_ON:  cpu idle, and
		 * nothing fancy done with main or cpu clocks.
		 */
		case PM_SUSPEND_STANDBY:
			/*
			 * NOTE: the Wait-for-Interrupt instruction needs to be
			 * in icache so no SDRAM accesses are needed until the
			 * wakeup IRQ occurs and self-refresh is terminated.
			 * For ARM 926 based chips, this requirement is weaker
			 * as at91sam9 can access a RAM in self-refresh mode.
			 */
			if (at91_pm_standby)
				at91_pm_standby();
			break;

		case PM_SUSPEND_ON:
			cpu_do_idle();
			break;

		default:
			pr_debug("AT91: PM - bogus suspend state %d\n", state);
			goto error;
	}

error:
	target_state = PM_SUSPEND_ON;

	at91_pinctrl_gpio_resume();
	return 0;
}

/*
 * Called right prior to thawing processes.
 */
static void at91_pm_end(void)
{
	target_state = PM_SUSPEND_ON;
}


static const struct platform_suspend_ops at91_pm_ops = {
	.valid	= at91_pm_valid_state,
	.begin	= at91_pm_begin,
	.enter	= at91_pm_enter,
	.end	= at91_pm_end,
};

static struct platform_device at91_cpuidle_device = {
	.name = "cpuidle-at91",
};

void at91_pm_set_standby(void (*at91_standby)(void))
{
	if (at91_standby) {
		at91_cpuidle_device.dev.platform_data = at91_standby;
		at91_pm_standby = at91_standby;
	}
}

static const struct of_device_id ramc_ids[] __initconst = {
	{ .compatible = "atmel,at91rm9200-sdramc", .data = at91rm9200_standby },
	{ .compatible = "atmel,at91sam9260-sdramc", .data = at91sam9_sdram_standby },
	{ .compatible = "atmel,at91sam9g45-ddramc", .data = at91_ddr_standby },
	{ .compatible = "atmel,sama5d3-ddramc", .data = at91_ddr_standby },
	{ /*sentinel*/ }
};

static __init void at91_dt_ramc(void)
{
	struct device_node *np;
	const struct of_device_id *of_id;
	int idx = 0;
	const void *standby = NULL;

	for_each_matching_node_and_match(np, ramc_ids, &of_id) {
		at91_ramc_base[idx] = of_iomap(np, 0);
		if (!at91_ramc_base[idx])
			panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx);

		if (!standby)
			standby = of_id->data;

		idx++;
	}

	if (!idx)
		panic(pr_fmt("unable to find compatible ram controller node in dtb\n"));

	if (!standby) {
		pr_warn("ramc no standby function available\n");
		return;
	}

	at91_pm_set_standby(standby);
}

#ifdef CONFIG_AT91_SLOW_CLOCK
static void __init at91_pm_sram_init(void)
{
	struct gen_pool *sram_pool;
	phys_addr_t sram_pbase;
	unsigned long sram_base;
	struct device_node *node;
	struct platform_device *pdev = NULL;

	for_each_compatible_node(node, NULL, "mmio-sram") {
		pdev = of_find_device_by_node(node);
		if (pdev) {
			of_node_put(node);
			break;
		}
	}

	if (!pdev) {
		pr_warn("%s: failed to find sram device!\n", __func__);
		return;
	}

	sram_pool = dev_get_gen_pool(&pdev->dev);
	if (!sram_pool) {
		pr_warn("%s: sram pool unavailable!\n", __func__);
		return;
	}

	sram_base = gen_pool_alloc(sram_pool, at91_slow_clock_sz);
	if (!sram_base) {
		pr_warn("%s: unable to alloc ocram!\n", __func__);
		return;
	}

	sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base);
	slow_clock = __arm_ioremap_exec(sram_pbase, at91_slow_clock_sz, false);
}
#endif


static void __init at91_pm_init(void)
{
#ifdef CONFIG_AT91_SLOW_CLOCK
	at91_pm_sram_init();
#endif

	pr_info("AT91: Power Management%s\n", (slow_clock ? " (with slow clock mode)" : ""));

	if (at91_cpuidle_device.dev.platform_data)
		platform_device_register(&at91_cpuidle_device);

	suspend_set_ops(&at91_pm_ops);
}

void __init at91rm9200_pm_init(void)
{
	at91_dt_ramc();

	/*
	 * AT91RM9200 SDRAM low-power mode cannot be used with self-refresh.
	 */
	at91_ramc_write(0, AT91RM9200_SDRAMC_LPR, 0);

	at91_pm_data.uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP;
	at91_pm_data.memctrl = AT91_MEMCTRL_MC;

	at91_pm_init();
}

void __init at91sam9260_pm_init(void)
{
	at91_dt_ramc();
	at91_pm_data.memctrl = AT91_MEMCTRL_SDRAMC;
	at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP;
	return at91_pm_init();
}

void __init at91sam9g45_pm_init(void)
{
	at91_dt_ramc();
	at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP;
	at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
	return at91_pm_init();
}

void __init at91sam9x5_pm_init(void)
{
	at91_dt_ramc();
	at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP;
	at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
	return at91_pm_init();
}
Commit	Line	Data
907d6deb	1	/*
9d041268	2	* arch/arm/mach-at91/pm.c
907d6deb AV	3	* AT91 Power Management
	4	*
	5	* Copyright (C) 2005 David Brownell
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*/
	12
2f8163ba	13	#include <linux/gpio.h>
95d9ffbe	14	#include <linux/suspend.h>
907d6deb AV	15	#include <linux/sched.h>
907d6deb AV	16	#include <linux/proc_fs.h>
d2e46790	17	#include <linux/genalloc.h>
907d6deb AV	18	#include <linux/interrupt.h>
	19	#include <linux/sysfs.h>
	20	#include <linux/module.h>
f5598d34	21	#include <linux/of.h>
d2e46790	22	#include <linux/of_platform.h>
827de1f1	23	#include <linux/of_address.h>
907d6deb	24	#include <linux/platform_device.h>
fced80c7	25	#include <linux/io.h>
2edb90ae	26	#include <linux/clk/at91_pmc.h>
907d6deb	27
907d6deb	28	#include <asm/irq.h>
60063497	29	#include <linux/atomic.h>
907d6deb AV	30	#include <asm/mach/time.h>
907d6deb AV	31	#include <asm/mach/irq.h>
907d6deb	32
a09e64fb	33	#include <mach/cpu.h>
ac11a1d4	34	#include <mach/hardware.h>
907d6deb AV	35
907d6deb AV	36	#include "generic.h"
1ea60cf7	37	#include "pm.h"
907d6deb	38
f5598d34 AB	39	static struct {
	40	unsigned long uhp_udp_mask;
	41	int memctrl;
	42	} at91_pm_data;
	43
5ad945ea	44	static void (*at91_pm_standby)(void);
827de1f1	45	void __iomem *at91_ramc_base[2];
5ad945ea	46
907d6deb AV	47	static int at91_pm_valid_state(suspend_state_t state)
	48	{
	49	switch (state) {
	50	case PM_SUSPEND_ON:
	51	case PM_SUSPEND_STANDBY:
	52	case PM_SUSPEND_MEM:
	53	return 1;
	54
	55	default:
	56	return 0;
	57	}
	58	}
	59
	60
	61	static suspend_state_t target_state;
	62
	63	/*
	64	* Called after processes are frozen, but before we shutdown devices.
	65	*/
c697eece	66	static int at91_pm_begin(suspend_state_t state)
907d6deb AV	67	{
	68	target_state = state;
	69	return 0;
	70	}
	71
	72	/*
	73	* Verify that all the clocks are correct before entering
	74	* slow-clock mode.
	75	*/
	76	static int at91_pm_verify_clocks(void)
	77	{
	78	unsigned long scsr;
	79	int i;
	80
b5514952	81	scsr = at91_pmc_read(AT91_PMC_SCSR);
907d6deb AV	82
907d6deb AV	83	/* USB must not be using PLLB */
f5598d34 AB	84	if ((scsr & at91_pm_data.uhp_udp_mask) != 0) {
	85	pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
	86	return 0;
907d6deb AV	87	}
907d6deb AV	88
907d6deb AV	89	/* PCK0..PCK3 must be disabled, or configured to use clk32k */
	90	for (i = 0; i < 4; i++) {
	91	u32 css;
	92
	93	if ((scsr & (AT91_PMC_PCK0 << i)) == 0)
	94	continue;
	95
b5514952	96	css = at91_pmc_read(AT91_PMC_PCKR(i)) & AT91_PMC_CSS;
907d6deb	97	if (css != AT91_PMC_CSS_SLOW) {
7f96b1ca	98	pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css);
907d6deb AV	99	return 0;
	100	}
	101	}
907d6deb AV	102
	103	return 1;
	104	}
	105
	106	/*
	107	* Call this from platform driver suspend() to see how deeply to suspend.
	108	* For example, some controllers (like OHCI) need one of the PLL clocks
	109	* in order to act as a wakeup source, and those are not available when
	110	* going into slow clock mode.
	111	*
	112	* REVISIT: generalize as clk_will_be_available(clk)? Other platforms have
	113	* the very same problem (but not using at91 main_clk), and it'd be better
	114	* to add one generic API rather than lots of platform-specific ones.
	115	*/
	116	int at91_suspend_entering_slow_clock(void)
	117	{
	118	return (target_state == PM_SUSPEND_MEM);
	119	}
	120	EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
	121
	122
fb7e197b JCPV	123	static void (slow_clock)(void __iomem pmc, void __iomem *ramc0,
fb7e197b JCPV	124	void __iomem *ramc1, int memctrl);
907d6deb	125
f5d0f457	126	#ifdef CONFIG_AT91_SLOW_CLOCK
fb7e197b JCPV	127	extern void at91_slow_clock(void __iomem pmc, void __iomem ramc0,
fb7e197b JCPV	128	void __iomem *ramc1, int memctrl);
f5d0f457 AV	129	extern u32 at91_slow_clock_sz;
	130	#endif
	131
907d6deb AV	132	static int at91_pm_enter(suspend_state_t state)
907d6deb AV	133	{
85c4b31e	134	at91_pinctrl_gpio_suspend();
907d6deb	135
907d6deb AV	136	switch (state) {
	137	/*
	138	* Suspend-to-RAM is like STANDBY plus slow clock mode, so
	139	* drivers must suspend more deeply: only the master clock
	140	* controller may be using the main oscillator.
	141	*/
	142	case PM_SUSPEND_MEM:
	143	/*
	144	* Ensure that clocks are in a valid state.
	145	*/
	146	if (!at91_pm_verify_clocks())
	147	goto error;
	148
	149	/*
	150	* Enter slow clock mode by switching over to clk32k and
	151	* turning off the main oscillator; reverse on wakeup.
	152	*/
	153	if (slow_clock) {
f5d0f457 AV	154	#ifdef CONFIG_AT91_SLOW_CLOCK
	155	/* copy slow_clock handler to SRAM, and call it */
	156	memcpy(slow_clock, at91_slow_clock, at91_slow_clock_sz);
	157	#endif
fb7e197b	158	slow_clock(at91_pmc_base, at91_ramc_base[0],
f5598d34 AB	159	at91_ramc_base[1],
f5598d34 AB	160	at91_pm_data.memctrl);
907d6deb AV	161	break;
907d6deb AV	162	} else {
f5d0f457	163	pr_info("AT91: PM - no slow clock mode enabled ...\n");
907d6deb AV	164	/* FALLTHROUGH leaving master clock alone */
	165	}
	166
	167	/*
	168	* STANDBY mode has all drivers suspended; ignores irqs not
	169	* marked as 'wakeup' event sources; and reduces DRAM power.
	170	* But otherwise it's identical to PM_SUSPEND_ON: cpu idle, and
	171	* nothing fancy done with main or cpu clocks.
	172	*/
	173	case PM_SUSPEND_STANDBY:
	174	/*
	175	* NOTE: the Wait-for-Interrupt instruction needs to be
f5d0f457 AV	176	* in icache so no SDRAM accesses are needed until the
f5d0f457 AV	177	* wakeup IRQ occurs and self-refresh is terminated.
8aeeda82 NF	178	* For ARM 926 based chips, this requirement is weaker
8aeeda82 NF	179	* as at91sam9 can access a RAM in self-refresh mode.
907d6deb	180	*/
5ad945ea DL	181	if (at91_pm_standby)
5ad945ea DL	182	at91_pm_standby();
f5d0f457	183	break;
907d6deb AV	184
907d6deb AV	185	case PM_SUSPEND_ON:
8aeeda82	186	cpu_do_idle();
907d6deb AV	187	break;
	188
	189	default:
	190	pr_debug("AT91: PM - bogus suspend state %d\n", state);
	191	goto error;
	192	}
	193
907d6deb AV	194	error:
907d6deb AV	195	target_state = PM_SUSPEND_ON;
07192604	196
85c4b31e	197	at91_pinctrl_gpio_resume();
907d6deb AV	198	return 0;
	199	}
	200
c697eece RW	201	/*
	202	* Called right prior to thawing processes.
	203	*/
	204	static void at91_pm_end(void)
	205	{
	206	target_state = PM_SUSPEND_ON;
	207	}
	208
907d6deb	209
2f55ac07	210	static const struct platform_suspend_ops at91_pm_ops = {
c697eece RW	211	.valid = at91_pm_valid_state,
	212	.begin = at91_pm_begin,
	213	.enter = at91_pm_enter,
	214	.end = at91_pm_end,
907d6deb AV	215	};
907d6deb AV	216
5ad945ea DL	217	static struct platform_device at91_cpuidle_device = {
	218	.name = "cpuidle-at91",
	219	};
	220
	221	void at91_pm_set_standby(void (*at91_standby)(void))
	222	{
	223	if (at91_standby) {
	224	at91_cpuidle_device.dev.platform_data = at91_standby;
	225	at91_pm_standby = at91_standby;
	226	}
	227	}
	228
444d2d33	229	static const struct of_device_id ramc_ids[] __initconst = {
827de1f1 AB	230	{ .compatible = "atmel,at91rm9200-sdramc", .data = at91rm9200_standby },
	231	{ .compatible = "atmel,at91sam9260-sdramc", .data = at91sam9_sdram_standby },
	232	{ .compatible = "atmel,at91sam9g45-ddramc", .data = at91_ddr_standby },
	233	{ .compatible = "atmel,sama5d3-ddramc", .data = at91_ddr_standby },
	234	{ /sentinel/ }
	235	};
	236
444d2d33	237	static __init void at91_dt_ramc(void)
827de1f1 AB	238	{
	239	struct device_node *np;
	240	const struct of_device_id *of_id;
	241	int idx = 0;
	242	const void *standby = NULL;
	243
	244	for_each_matching_node_and_match(np, ramc_ids, &of_id) {
	245	at91_ramc_base[idx] = of_iomap(np, 0);
	246	if (!at91_ramc_base[idx])
	247	panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx);
	248
	249	if (!standby)
	250	standby = of_id->data;
	251
	252	idx++;
	253	}
	254
	255	if (!idx)
	256	panic(pr_fmt("unable to find compatible ram controller node in dtb\n"));
	257
	258	if (!standby) {
	259	pr_warn("ramc no standby function available\n");
	260	return;
	261	}
	262
	263	at91_pm_set_standby(standby);
	264	}
	265
d2e46790 AB	266	#ifdef CONFIG_AT91_SLOW_CLOCK
	267	static void __init at91_pm_sram_init(void)
	268	{
	269	struct gen_pool *sram_pool;
	270	phys_addr_t sram_pbase;
	271	unsigned long sram_base;
	272	struct device_node *node;
4a031f7d	273	struct platform_device *pdev = NULL;
d2e46790	274
4a031f7d AB	275	for_each_compatible_node(node, NULL, "mmio-sram") {
	276	pdev = of_find_device_by_node(node);
	277	if (pdev) {
	278	of_node_put(node);
	279	break;
	280	}
d2e46790 AB	281	}
d2e46790 AB	282
d2e46790 AB	283	if (!pdev) {
d2e46790 AB	284	pr_warn("%s: failed to find sram device!\n", __func__);
4a031f7d	285	return;
d2e46790 AB	286	}
	287
	288	sram_pool = dev_get_gen_pool(&pdev->dev);
	289	if (!sram_pool) {
	290	pr_warn("%s: sram pool unavailable!\n", __func__);
4a031f7d	291	return;
d2e46790 AB	292	}
	293
	294	sram_base = gen_pool_alloc(sram_pool, at91_slow_clock_sz);
	295	if (!sram_base) {
	296	pr_warn("%s: unable to alloc ocram!\n", __func__);
4a031f7d	297	return;
d2e46790 AB	298	}
	299
	300	sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base);
	301	slow_clock = __arm_ioremap_exec(sram_pbase, at91_slow_clock_sz, false);
d2e46790 AB	302	}
	303	#endif
	304
	305
4db0ba22	306	static void __init at91_pm_init(void)
907d6deb	307	{
f5d0f457	308	#ifdef CONFIG_AT91_SLOW_CLOCK
d2e46790	309	at91_pm_sram_init();
907d6deb AV	310	#endif
907d6deb AV	311
f5d0f457 AV	312	pr_info("AT91: Power Management%s\n", (slow_clock ? " (with slow clock mode)" : ""));
f5d0f457 AV	313
5ad945ea DL	314	if (at91_cpuidle_device.dev.platform_data)
5ad945ea DL	315	platform_device_register(&at91_cpuidle_device);
907d6deb	316
26398a70	317	suspend_set_ops(&at91_pm_ops);
4db0ba22	318	}
907d6deb	319
ad3fc3e3	320	void __init at91rm9200_pm_init(void)
4db0ba22	321	{
827de1f1 AB	322	at91_dt_ramc();
827de1f1 AB	323
4db0ba22 AB	324	/*
	325	* AT91RM9200 SDRAM low-power mode cannot be used with self-refresh.
	326	*/
	327	at91_ramc_write(0, AT91RM9200_SDRAMC_LPR, 0);
	328
	329	at91_pm_data.uhp_udp_mask = AT91RM9200_PMC_UHP \| AT91RM9200_PMC_UDP;
	330	at91_pm_data.memctrl = AT91_MEMCTRL_MC;
	331
	332	at91_pm_init();
	333	}
	334
ad3fc3e3	335	void __init at91sam9260_pm_init(void)
4db0ba22	336	{
827de1f1	337	at91_dt_ramc();
4db0ba22 AB	338	at91_pm_data.memctrl = AT91_MEMCTRL_SDRAMC;
	339	at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP \| AT91SAM926x_PMC_UDP;
	340	return at91_pm_init();
	341	}
	342
ad3fc3e3	343	void __init at91sam9g45_pm_init(void)
4db0ba22	344	{
827de1f1	345	at91_dt_ramc();
4db0ba22 AB	346	at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP;
	347	at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
	348	return at91_pm_init();
907d6deb	349	}
bf02280e	350
ad3fc3e3	351	void __init at91sam9x5_pm_init(void)
bf02280e	352	{
827de1f1	353	at91_dt_ramc();
bf02280e NF	354	at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP \| AT91SAM926x_PMC_UDP;
	355	at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
	356	return at91_pm_init();
	357	}