[deliverable/linux.git] / arch / arm / mach-at91 / pm.c

/*
 * arch/arm/mach-at91/pm.c
 * AT91 Power Management
 *
 * Copyright (C) 2005 David Brownell
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/suspend.h>
#include <linux/sched.h>
#include <linux/proc_fs.h>
#include <linux/interrupt.h>
#include <linux/sysfs.h>
#include <linux/module.h>
#include <linux/platform_device.h>

#include <asm/io.h>
#include <asm/irq.h>
#include <asm/atomic.h>
#include <asm/mach/time.h>
#include <asm/mach/irq.h>
#include <asm/mach-types.h>

#include <asm/arch/at91_pmc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/cpu.h>

#include "generic.h"

#ifdef CONFIG_ARCH_AT91RM9200
#include <asm/arch/at91rm9200_mc.h>

/*
 * The AT91RM9200 goes into self-refresh mode with this command, and will
 * terminate self-refresh automatically on the next SDRAM access.
 */
#define sdram_selfrefresh_enable()	at91_sys_write(AT91_SDRAMC_SRR, 1)
#define sdram_selfrefresh_disable()	do {} while (0)

#elif defined(CONFIG_ARCH_AT91CAP9)
#include <asm/arch/at91cap9_ddrsdr.h>

static u32 saved_lpr;

static inline void sdram_selfrefresh_enable(void)
{
	u32 lpr;

	saved_lpr = at91_sys_read(AT91_DDRSDRC_LPR);

	lpr = saved_lpr & ~AT91_DDRSDRC_LPCB;
	at91_sys_write(AT91_DDRSDRC_LPR, lpr | AT91_DDRSDRC_LPCB_SELF_REFRESH);
}

#define sdram_selfrefresh_disable()	at91_sys_write(AT91_DDRSDRC_LPR, saved_lpr)

#else
#include <asm/arch/at91sam9_sdramc.h>

static u32 saved_lpr;

static inline void sdram_selfrefresh_enable(void)
{
	u32 lpr;

	saved_lpr = at91_sys_read(AT91_SDRAMC_LPR);

	lpr = saved_lpr & ~AT91_SDRAMC_LPCB;
	at91_sys_write(AT91_SDRAMC_LPR, lpr | AT91_SDRAMC_LPCB_SELF_REFRESH);
}

#define sdram_selfrefresh_disable()	at91_sys_write(AT91_SDRAMC_LPR, saved_lpr)

/*
 * FIXME: The AT91SAM9263 has a second EBI controller which may have
 *        additional SDRAM.  pm_slowclock.S will require a similar fix.
 */

#endif


/*
 * Show the reason for the previous system reset.
 */
#if defined(AT91_SHDWC)

#include <asm/arch/at91_rstc.h>
#include <asm/arch/at91_shdwc.h>

static void __init show_reset_status(void)
{
	static char reset[] __initdata = "reset";

	static char general[] __initdata = "general";
	static char wakeup[] __initdata = "wakeup";
	static char watchdog[] __initdata = "watchdog";
	static char software[] __initdata = "software";
	static char user[] __initdata = "user";
	static char unknown[] __initdata = "unknown";

	static char signal[] __initdata = "signal";
	static char rtc[] __initdata = "rtc";
	static char rtt[] __initdata = "rtt";
	static char restore[] __initdata = "power-restored";

	char *reason, *r2 = reset;
	u32 reset_type, wake_type;

	reset_type = at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_RSTTYP;
	wake_type = at91_sys_read(AT91_SHDW_SR);

	switch (reset_type) {
	case AT91_RSTC_RSTTYP_GENERAL:
		reason = general;
		break;
	case AT91_RSTC_RSTTYP_WAKEUP:
		/* board-specific code enabled the wakeup sources */
		reason = wakeup;

		/* "wakeup signal" */
		if (wake_type & AT91_SHDW_WAKEUP0)
			r2 = signal;
		else {
			r2 = reason;
			if (wake_type & AT91_SHDW_RTTWK)	/* rtt wakeup */
				reason = rtt;
			else if (wake_type & AT91_SHDW_RTCWK)	/* rtc wakeup */
				reason = rtc;
			else if (wake_type == 0)	/* power-restored wakeup */
				reason = restore;
			else				/* unknown wakeup */
				reason = unknown;
		}
		break;
	case AT91_RSTC_RSTTYP_WATCHDOG:
		reason = watchdog;
		break;
	case AT91_RSTC_RSTTYP_SOFTWARE:
		reason = software;
		break;
	case AT91_RSTC_RSTTYP_USER:
		reason = user;
		break;
	default:
		reason = unknown;
		break;
	}
	pr_info("AT91: Starting after %s %s\n", reason, r2);
}
#else
static void __init show_reset_status(void) {}
#endif


static int at91_pm_valid_state(suspend_state_t state)
{
	switch (state) {
		case PM_SUSPEND_ON:
		case PM_SUSPEND_STANDBY:
		case PM_SUSPEND_MEM:
			return 1;

		default:
			return 0;
	}
}


static suspend_state_t target_state;

/*
 * Called after processes are frozen, but before we shutdown devices.
 */
static int at91_pm_begin(suspend_state_t state)
{
	target_state = state;
	return 0;
}

/*
 * Verify that all the clocks are correct before entering
 * slow-clock mode.
 */
static int at91_pm_verify_clocks(void)
{
	unsigned long scsr;
	int i;

	scsr = at91_sys_read(AT91_PMC_SCSR);

	/* USB must not be using PLLB */
	if (cpu_is_at91rm9200()) {
		if ((scsr & (AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP)) != 0) {
			pr_debug("AT91: PM - Suspend-to-RAM with USB still active\n");
			return 0;
		}
	} else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || cpu_is_at91sam9263()) {
		if ((scsr & (AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP)) != 0) {
			pr_debug("AT91: PM - Suspend-to-RAM with USB still active\n");
			return 0;
		}
	} else if (cpu_is_at91cap9()) {
		if ((scsr & AT91CAP9_PMC_UHP) != 0) {
			pr_debug("AT91: PM - Suspend-to-RAM with USB still active\n");
			return 0;
		}
	}

#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
	/* PCK0..PCK3 must be disabled, or configured to use clk32k */
	for (i = 0; i < 4; i++) {
		u32 css;

		if ((scsr & (AT91_PMC_PCK0 << i)) == 0)
			continue;

		css = at91_sys_read(AT91_PMC_PCKR(i)) & AT91_PMC_CSS;
		if (css != AT91_PMC_CSS_SLOW) {
			pr_debug("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css);
			return 0;
		}
	}
#endif

	return 1;
}

/*
 * Call this from platform driver suspend() to see how deeply to suspend.
 * For example, some controllers (like OHCI) need one of the PLL clocks
 * in order to act as a wakeup source, and those are not available when
 * going into slow clock mode.
 *
 * REVISIT: generalize as clk_will_be_available(clk)?  Other platforms have
 * the very same problem (but not using at91 main_clk), and it'd be better
 * to add one generic API rather than lots of platform-specific ones.
 */
int at91_suspend_entering_slow_clock(void)
{
	return (target_state == PM_SUSPEND_MEM);
}
EXPORT_SYMBOL(at91_suspend_entering_slow_clock);


static void (*slow_clock)(void);

#ifdef CONFIG_AT91_SLOW_CLOCK
extern void at91_slow_clock(void);
extern u32 at91_slow_clock_sz;
#endif


static int at91_pm_enter(suspend_state_t state)
{
	at91_gpio_suspend();
	at91_irq_suspend();

	pr_debug("AT91: PM - wake mask %08x, pm state %d\n",
			/* remember all the always-wake irqs */
			(at91_sys_read(AT91_PMC_PCSR)
					| (1 << AT91_ID_FIQ)
					| (1 << AT91_ID_SYS)
					| (at91_extern_irq))
				& at91_sys_read(AT91_AIC_IMR),
			state);

	switch (state) {
		/*
		 * Suspend-to-RAM is like STANDBY plus slow clock mode, so
		 * drivers must suspend more deeply:  only the master clock
		 * controller may be using the main oscillator.
		 */
		case PM_SUSPEND_MEM:
			/*
			 * Ensure that clocks are in a valid state.
			 */
			if (!at91_pm_verify_clocks())
				goto error;

			/*
			 * Enter slow clock mode by switching over to clk32k and
			 * turning off the main oscillator; reverse on wakeup.
			 */
			if (slow_clock) {
#ifdef CONFIG_AT91_SLOW_CLOCK
				/* copy slow_clock handler to SRAM, and call it */
				memcpy(slow_clock, at91_slow_clock, at91_slow_clock_sz);
#endif
				slow_clock();
				break;
			} else {
				pr_info("AT91: PM - no slow clock mode enabled ...\n");
				/* FALLTHROUGH leaving master clock alone */
			}

		/*
		 * STANDBY mode has *all* drivers suspended; ignores irqs not
		 * marked as 'wakeup' event sources; and reduces DRAM power.
		 * But otherwise it's identical to PM_SUSPEND_ON:  cpu idle, and
		 * nothing fancy done with main or cpu clocks.
		 */
		case PM_SUSPEND_STANDBY:
			/*
			 * NOTE: the Wait-for-Interrupt instruction needs to be
			 * in icache so no SDRAM accesses are needed until the
			 * wakeup IRQ occurs and self-refresh is terminated.
			 */
			asm("b 1f; .align 5; 1:");
			asm("mcr p15, 0, r0, c7, c10, 4");	/* drain write buffer */
			sdram_selfrefresh_enable();
			asm("mcr p15, 0, r0, c7, c0, 4");	/* wait for interrupt */
			sdram_selfrefresh_disable();
			break;

		case PM_SUSPEND_ON:
			asm("mcr p15, 0, r0, c7, c0, 4");	/* wait for interrupt */
			break;

		default:
			pr_debug("AT91: PM - bogus suspend state %d\n", state);
			goto error;
	}

	pr_debug("AT91: PM - wakeup %08x\n",
			at91_sys_read(AT91_AIC_IPR) & at91_sys_read(AT91_AIC_IMR));

error:
	sdram_selfrefresh_disable();
	target_state = PM_SUSPEND_ON;
	at91_irq_resume();
	at91_gpio_resume();
	return 0;
}

/*
 * Called right prior to thawing processes.
 */
static void at91_pm_end(void)
{
	target_state = PM_SUSPEND_ON;
}


static struct platform_suspend_ops at91_pm_ops ={
	.valid	= at91_pm_valid_state,
	.begin	= at91_pm_begin,
	.enter	= at91_pm_enter,
	.end	= at91_pm_end,
};

static int __init at91_pm_init(void)
{
#ifdef CONFIG_AT91_SLOW_CLOCK
	slow_clock = (void *) (AT91_IO_VIRT_BASE - at91_slow_clock_sz);
#endif

	pr_info("AT91: Power Management%s\n", (slow_clock ? " (with slow clock mode)" : ""));

#ifdef CONFIG_ARCH_AT91RM9200
	/* AT91RM9200 SDRAM low-power mode cannot be used with self-refresh. */
	at91_sys_write(AT91_SDRAMC_LPR, 0);
#endif

	suspend_set_ops(&at91_pm_ops);

	show_reset_status();
	return 0;
}
arch_initcall(at91_pm_init);
Commit	Line	Data
907d6deb	1	/*
9d041268	2	* arch/arm/mach-at91/pm.c
907d6deb AV	3	* AT91 Power Management
	4	*
	5	* Copyright (C) 2005 David Brownell
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*/
	12
95d9ffbe	13	#include <linux/suspend.h>
907d6deb AV	14	#include <linux/sched.h>
907d6deb AV	15	#include <linux/proc_fs.h>
907d6deb AV	16	#include <linux/interrupt.h>
	17	#include <linux/sysfs.h>
	18	#include <linux/module.h>
	19	#include <linux/platform_device.h>
	20
	21	#include <asm/io.h>
	22	#include <asm/irq.h>
	23	#include <asm/atomic.h>
	24	#include <asm/mach/time.h>
	25	#include <asm/mach/irq.h>
	26	#include <asm/mach-types.h>
	27
55d8baee	28	#include <asm/arch/at91_pmc.h>
907d6deb	29	#include <asm/arch/gpio.h>
d481f864	30	#include <asm/arch/cpu.h>
907d6deb AV	31
	32	#include "generic.h"
	33
f5d0f457 AV	34	#ifdef CONFIG_ARCH_AT91RM9200
	35	#include <asm/arch/at91rm9200_mc.h>
	36
	37	/*
	38	* The AT91RM9200 goes into self-refresh mode with this command, and will
	39	* terminate self-refresh automatically on the next SDRAM access.
	40	*/
	41	#define sdram_selfrefresh_enable() at91_sys_write(AT91_SDRAMC_SRR, 1)
	42	#define sdram_selfrefresh_disable() do {} while (0)
	43
	44	#elif defined(CONFIG_ARCH_AT91CAP9)
	45	#include <asm/arch/at91cap9_ddrsdr.h>
	46
	47	static u32 saved_lpr;
	48
	49	static inline void sdram_selfrefresh_enable(void)
	50	{
	51	u32 lpr;
	52
	53	saved_lpr = at91_sys_read(AT91_DDRSDRC_LPR);
	54
	55	lpr = saved_lpr & ~AT91_DDRSDRC_LPCB;
	56	at91_sys_write(AT91_DDRSDRC_LPR, lpr \| AT91_DDRSDRC_LPCB_SELF_REFRESH);
	57	}
	58
	59	#define sdram_selfrefresh_disable() at91_sys_write(AT91_DDRSDRC_LPR, saved_lpr)
	60
	61	#else
	62	#include <asm/arch/at91sam9_sdramc.h>
	63
	64	static u32 saved_lpr;
	65
	66	static inline void sdram_selfrefresh_enable(void)
	67	{
	68	u32 lpr;
	69
	70	saved_lpr = at91_sys_read(AT91_SDRAMC_LPR);
	71
	72	lpr = saved_lpr & ~AT91_SDRAMC_LPCB;
	73	at91_sys_write(AT91_SDRAMC_LPR, lpr \| AT91_SDRAMC_LPCB_SELF_REFRESH);
	74	}
	75
	76	#define sdram_selfrefresh_disable() at91_sys_write(AT91_SDRAMC_LPR, saved_lpr)
	77
	78	/*
	79	* FIXME: The AT91SAM9263 has a second EBI controller which may have
	80	* additional SDRAM. pm_slowclock.S will require a similar fix.
	81	*/
	82
	83	#endif
	84
907d6deb	85
565ac445 AV	86	/*
	87	* Show the reason for the previous system reset.
	88	*/
	89	#if defined(AT91_SHDWC)
	90
	91	#include <asm/arch/at91_rstc.h>
	92	#include <asm/arch/at91_shdwc.h>
	93
	94	static void __init show_reset_status(void)
	95	{
	96	static char reset[] __initdata = "reset";
	97
	98	static char general[] __initdata = "general";
	99	static char wakeup[] __initdata = "wakeup";
	100	static char watchdog[] __initdata = "watchdog";
	101	static char software[] __initdata = "software";
	102	static char user[] __initdata = "user";
	103	static char unknown[] __initdata = "unknown";
	104
	105	static char signal[] __initdata = "signal";
	106	static char rtc[] __initdata = "rtc";
	107	static char rtt[] __initdata = "rtt";
	108	static char restore[] __initdata = "power-restored";
	109
	110	char reason, r2 = reset;
	111	u32 reset_type, wake_type;
	112
	113	reset_type = at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_RSTTYP;
	114	wake_type = at91_sys_read(AT91_SHDW_SR);
	115
	116	switch (reset_type) {
	117	case AT91_RSTC_RSTTYP_GENERAL:
	118	reason = general;
	119	break;
	120	case AT91_RSTC_RSTTYP_WAKEUP:
	121	/* board-specific code enabled the wakeup sources */
	122	reason = wakeup;
	123
	124	/* "wakeup signal" */
	125	if (wake_type & AT91_SHDW_WAKEUP0)
	126	r2 = signal;
	127	else {
	128	r2 = reason;
	129	if (wake_type & AT91_SHDW_RTTWK) /* rtt wakeup */
	130	reason = rtt;
	131	else if (wake_type & AT91_SHDW_RTCWK) /* rtc wakeup */
	132	reason = rtc;
	133	else if (wake_type == 0) /* power-restored wakeup */
	134	reason = restore;
	135	else /* unknown wakeup */
	136	reason = unknown;
	137	}
	138	break;
	139	case AT91_RSTC_RSTTYP_WATCHDOG:
	140	reason = watchdog;
	141	break;
	142	case AT91_RSTC_RSTTYP_SOFTWARE:
	143	reason = software;
	144	break;
	145	case AT91_RSTC_RSTTYP_USER:
	146	reason = user;
	147	break;
	148	default:
	149	reason = unknown;
150	break;
151	}
152	pr_info("AT91: Starting after %s %s\n", reason, r2);
153	}
154	#else
155	static void __init show_reset_status(void) {}
156	#endif
157
158
907d6deb AV	159	static int at91_pm_valid_state(suspend_state_t state)
	160	{
	161	switch (state) {
	162	case PM_SUSPEND_ON:
	163	case PM_SUSPEND_STANDBY:
	164	case PM_SUSPEND_MEM:
	165	return 1;
	166
	167	default:
	168	return 0;
	169	}
	170	}
	171
	172
	173	static suspend_state_t target_state;
	174
	175	/*
	176	* Called after processes are frozen, but before we shutdown devices.
	177	*/
c697eece	178	static int at91_pm_begin(suspend_state_t state)
907d6deb AV	179	{
	180	target_state = state;
	181	return 0;
	182	}
	183
	184	/*
	185	* Verify that all the clocks are correct before entering
	186	* slow-clock mode.
	187	*/
	188	static int at91_pm_verify_clocks(void)
	189	{
	190	unsigned long scsr;
	191	int i;
	192
	193	scsr = at91_sys_read(AT91_PMC_SCSR);
	194
	195	/* USB must not be using PLLB */
d481f864 AV	196	if (cpu_is_at91rm9200()) {
	197	if ((scsr & (AT91RM9200_PMC_UHP \| AT91RM9200_PMC_UDP)) != 0) {
	198	pr_debug("AT91: PM - Suspend-to-RAM with USB still active\n");
	199	return 0;
	200	}
b6b27ae5 AV	201	} else if (cpu_is_at91sam9260() \|\| cpu_is_at91sam9261() \|\| cpu_is_at91sam9263()) {
	202	if ((scsr & (AT91SAM926x_PMC_UHP \| AT91SAM926x_PMC_UDP)) != 0) {
	203	pr_debug("AT91: PM - Suspend-to-RAM with USB still active\n");
	204	return 0;
	205	}
2b3b3516 AV	206	} else if (cpu_is_at91cap9()) {
	207	if ((scsr & AT91CAP9_PMC_UHP) != 0) {
	208	pr_debug("AT91: PM - Suspend-to-RAM with USB still active\n");
	209	return 0;
	210	}
907d6deb AV	211	}
	212
	213	#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
	214	/* PCK0..PCK3 must be disabled, or configured to use clk32k */
	215	for (i = 0; i < 4; i++) {
	216	u32 css;
	217
	218	if ((scsr & (AT91_PMC_PCK0 << i)) == 0)
	219	continue;
	220
	221	css = at91_sys_read(AT91_PMC_PCKR(i)) & AT91_PMC_CSS;
	222	if (css != AT91_PMC_CSS_SLOW) {
	223	pr_debug("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css);
	224	return 0;
	225	}
	226	}
	227	#endif
	228
	229	return 1;
	230	}
	231
	232	/*
	233	* Call this from platform driver suspend() to see how deeply to suspend.
	234	* For example, some controllers (like OHCI) need one of the PLL clocks
	235	* in order to act as a wakeup source, and those are not available when
	236	* going into slow clock mode.
	237	*
	238	* REVISIT: generalize as clk_will_be_available(clk)? Other platforms have
	239	* the very same problem (but not using at91 main_clk), and it'd be better
	240	* to add one generic API rather than lots of platform-specific ones.
	241	*/
	242	int at91_suspend_entering_slow_clock(void)
	243	{
	244	return (target_state == PM_SUSPEND_MEM);
	245	}
	246	EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
	247
	248
	249	static void (*slow_clock)(void);
	250
f5d0f457 AV	251	#ifdef CONFIG_AT91_SLOW_CLOCK
	252	extern void at91_slow_clock(void);
	253	extern u32 at91_slow_clock_sz;
	254	#endif
	255
907d6deb	256
907d6deb AV	257	static int at91_pm_enter(suspend_state_t state)
	258	{
	259	at91_gpio_suspend();
	260	at91_irq_suspend();
	261
	262	pr_debug("AT91: PM - wake mask %08x, pm state %d\n",
	263	/* remember all the always-wake irqs */
	264	(at91_sys_read(AT91_PMC_PCSR)
	265	\| (1 << AT91_ID_FIQ)
	266	\| (1 << AT91_ID_SYS)
1f4fd0a0	267	\| (at91_extern_irq))
907d6deb AV	268	& at91_sys_read(AT91_AIC_IMR),
	269	state);
	270
	271	switch (state) {
	272	/*
	273	* Suspend-to-RAM is like STANDBY plus slow clock mode, so
	274	* drivers must suspend more deeply: only the master clock
	275	* controller may be using the main oscillator.
	276	*/
	277	case PM_SUSPEND_MEM:
	278	/*
	279	* Ensure that clocks are in a valid state.
	280	*/
	281	if (!at91_pm_verify_clocks())
	282	goto error;
	283
	284	/*
	285	* Enter slow clock mode by switching over to clk32k and
	286	* turning off the main oscillator; reverse on wakeup.
	287	*/
	288	if (slow_clock) {
f5d0f457 AV	289	#ifdef CONFIG_AT91_SLOW_CLOCK
	290	/* copy slow_clock handler to SRAM, and call it */
	291	memcpy(slow_clock, at91_slow_clock, at91_slow_clock_sz);
	292	#endif
907d6deb AV	293	slow_clock();
	294	break;
	295	} else {
f5d0f457	296	pr_info("AT91: PM - no slow clock mode enabled ...\n");
907d6deb AV	297	/* FALLTHROUGH leaving master clock alone */
	298	}
	299
	300	/*
	301	* STANDBY mode has all drivers suspended; ignores irqs not
	302	* marked as 'wakeup' event sources; and reduces DRAM power.
	303	* But otherwise it's identical to PM_SUSPEND_ON: cpu idle, and
	304	* nothing fancy done with main or cpu clocks.
	305	*/
	306	case PM_SUSPEND_STANDBY:
	307	/*
	308	* NOTE: the Wait-for-Interrupt instruction needs to be
f5d0f457 AV	309	* in icache so no SDRAM accesses are needed until the
f5d0f457 AV	310	* wakeup IRQ occurs and self-refresh is terminated.
907d6deb AV	311	*/
	312	asm("b 1f; .align 5; 1:");
	313	asm("mcr p15, 0, r0, c7, c10, 4"); /* drain write buffer */
f5d0f457 AV	314	sdram_selfrefresh_enable();
	315	asm("mcr p15, 0, r0, c7, c0, 4"); /* wait for interrupt */
	316	sdram_selfrefresh_disable();
	317	break;
907d6deb AV	318
	319	case PM_SUSPEND_ON:
	320	asm("mcr p15, 0, r0, c7, c0, 4"); /* wait for interrupt */
	321	break;
	322
	323	default:
	324	pr_debug("AT91: PM - bogus suspend state %d\n", state);
	325	goto error;
	326	}
	327
	328	pr_debug("AT91: PM - wakeup %08x\n",
	329	at91_sys_read(AT91_AIC_IPR) & at91_sys_read(AT91_AIC_IMR));
	330
	331	error:
f5d0f457	332	sdram_selfrefresh_disable();
907d6deb AV	333	target_state = PM_SUSPEND_ON;
	334	at91_irq_resume();
	335	at91_gpio_resume();
	336	return 0;
	337	}
	338
c697eece RW	339	/*
	340	* Called right prior to thawing processes.
	341	*/
	342	static void at91_pm_end(void)
	343	{
	344	target_state = PM_SUSPEND_ON;
	345	}
	346
907d6deb	347
26398a70	348	static struct platform_suspend_ops at91_pm_ops ={
c697eece RW	349	.valid = at91_pm_valid_state,
	350	.begin = at91_pm_begin,
	351	.enter = at91_pm_enter,
	352	.end = at91_pm_end,
907d6deb AV	353	};
	354
	355	static int __init at91_pm_init(void)
	356	{
f5d0f457 AV	357	#ifdef CONFIG_AT91_SLOW_CLOCK
f5d0f457 AV	358	slow_clock = (void *) (AT91_IO_VIRT_BASE - at91_slow_clock_sz);
907d6deb AV	359	#endif
907d6deb AV	360
f5d0f457 AV	361	pr_info("AT91: Power Management%s\n", (slow_clock ? " (with slow clock mode)" : ""));
	362
	363	#ifdef CONFIG_ARCH_AT91RM9200
	364	/* AT91RM9200 SDRAM low-power mode cannot be used with self-refresh. */
907d6deb	365	at91_sys_write(AT91_SDRAMC_LPR, 0);
f5d0f457	366	#endif
907d6deb	367
26398a70	368	suspend_set_ops(&at91_pm_ops);
907d6deb	369
565ac445	370	show_reset_status();
907d6deb AV	371	return 0;
	372	}
	373	arch_initcall(at91_pm_init);