[deliverable/linux.git] / arch / arm / mach-at91 / pm_slowclock.S

/*
 * arch/arm/mach-at91/pm_slow_clock.S
 *
 *  Copyright (C) 2006 Savin Zlobec
 *
 * AT91SAM9 support:
 *  Copyright (C) 2007 Anti Sullin <anti.sullin@artecdesign.ee
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 */

#include <linux/linkage.h>
#include <linux/clk/at91_pmc.h>
#include <mach/hardware.h>
#include <mach/at91_ramc.h>

/*
 * When SLOWDOWN_MASTER_CLOCK is defined we will also slow down the Master
 * clock during suspend by adjusting its prescalar and divisor.
 * NOTE: This hasn't been shown to be stable on SAM9s; and on the RM9200 there
 *       are errata regarding adjusting the prescalar and divisor.
 */
#undef SLOWDOWN_MASTER_CLOCK

pmc	.req	r0
sdramc	.req	r1
ramc1	.req	r2
memctrl	.req	r3
tmp1	.req	r4
tmp2	.req	r5

/*
 * Wait until master clock is ready (after switching master clock source)
 */
	.macro wait_mckrdy
1:	ldr	tmp1, [pmc, #AT91_PMC_SR]
	tst	tmp1, #AT91_PMC_MCKRDY
	beq	1b
	.endm

/*
 * Wait until master oscillator has stabilized.
 */
	.macro wait_moscrdy
1:	ldr	tmp1, [pmc, #AT91_PMC_SR]
	tst	tmp1, #AT91_PMC_MOSCS
	beq	1b
	.endm

/*
 * Wait until PLLA has locked.
 */
	.macro wait_pllalock
1:	ldr	tmp1, [pmc, #AT91_PMC_SR]
	tst	tmp1, #AT91_PMC_LOCKA
	beq	1b
	.endm

/*
 * Wait until PLLB has locked.
 */
	.macro wait_pllblock
1:	ldr	tmp1, [pmc, #AT91_PMC_SR]
	tst	tmp1, #AT91_PMC_LOCKB
	beq	1b
	.endm

	.text

/* void at91_slow_clock(void __iomem *pmc, void __iomem *sdramc,
 *			void __iomem *ramc1, int memctrl)
 */
ENTRY(at91_slow_clock)
	/* Save registers on stack */
	stmfd	sp!, {r4 - r12, lr}

	/*
	 * Register usage:
	 *  R0 = Base address of AT91_PMC
	 *  R1 = Base address of RAM Controller (SDRAM, DDRSDR, or AT91_SYS)
	 *  R2 = Base address of second RAM Controller or 0 if not present
	 *  R3 = Memory controller
	 *  R4 = temporary register
	 *  R5 = temporary register
	 */

	/* Drain write buffer */
	mov	tmp1, #0
	mcr	p15, 0, tmp1, c7, c10, 4

	cmp	memctrl, #AT91_MEMCTRL_MC
	bne	ddr_sr_enable

	/*
	 * at91rm9200 Memory controller
	 */
	/* Put SDRAM in self-refresh mode */
	mov	tmp1, #1
	str	tmp1, [sdramc, #AT91RM9200_SDRAMC_SRR]
	b	sdr_sr_done

	/*
	 * DDRSDR Memory controller
	 */
ddr_sr_enable:
	cmp	memctrl, #AT91_MEMCTRL_DDRSDR
	bne	sdr_sr_enable

	/* LPDDR1 --> force DDR2 mode during self-refresh */
	ldr	tmp1, [sdramc, #AT91_DDRSDRC_MDR]
	str	tmp1, .saved_sam9_mdr
	bic	tmp1, tmp1, #~AT91_DDRSDRC_MD
	cmp	tmp1, #AT91_DDRSDRC_MD_LOW_POWER_DDR
	ldreq	tmp1, [sdramc, #AT91_DDRSDRC_MDR]
	biceq	tmp1, tmp1, #AT91_DDRSDRC_MD
	orreq	tmp1, tmp1, #AT91_DDRSDRC_MD_DDR2
	streq	tmp1, [sdramc, #AT91_DDRSDRC_MDR]

	/* prepare for DDRAM self-refresh mode */
	ldr	tmp1, [sdramc, #AT91_DDRSDRC_LPR]
	str	tmp1, .saved_sam9_lpr
	bic	tmp1, #AT91_DDRSDRC_LPCB
	orr	tmp1, #AT91_DDRSDRC_LPCB_SELF_REFRESH

	/* figure out if we use the second ram controller */
	cmp	ramc1, #0
	beq	ddr_no_2nd_ctrl

	ldr	tmp2, [ramc1, #AT91_DDRSDRC_MDR]
	str	tmp2, .saved_sam9_mdr1
	bic	tmp2, tmp2, #~AT91_DDRSDRC_MD
	cmp	tmp2, #AT91_DDRSDRC_MD_LOW_POWER_DDR
	ldreq	tmp2, [ramc1, #AT91_DDRSDRC_MDR]
	biceq	tmp2, tmp2, #AT91_DDRSDRC_MD
	orreq	tmp2, tmp2, #AT91_DDRSDRC_MD_DDR2
	streq	tmp2, [ramc1, #AT91_DDRSDRC_MDR]

	ldr	tmp2, [ramc1, #AT91_DDRSDRC_LPR]
	str	tmp2, .saved_sam9_lpr1
	bic	tmp2, #AT91_DDRSDRC_LPCB
	orr	tmp2, #AT91_DDRSDRC_LPCB_SELF_REFRESH

	/* Enable DDRAM self-refresh mode */
	str	tmp2, [ramc1, #AT91_DDRSDRC_LPR]
ddr_no_2nd_ctrl:
	str	tmp1, [sdramc, #AT91_DDRSDRC_LPR]

	b	sdr_sr_done

	/*
	 * SDRAMC Memory controller
	 */
sdr_sr_enable:
	/* Enable SDRAM self-refresh mode */
	ldr	tmp1, [sdramc, #AT91_SDRAMC_LPR]
	str	tmp1, .saved_sam9_lpr

	bic	tmp1, #AT91_SDRAMC_LPCB
	orr	tmp1, #AT91_SDRAMC_LPCB_SELF_REFRESH
	str	tmp1, [sdramc, #AT91_SDRAMC_LPR]

sdr_sr_done:
	/* Save Master clock setting */
	ldr	tmp1, [pmc, #AT91_PMC_MCKR]
	str	tmp1, .saved_mckr

	/*
	 * Set the Master clock source to slow clock
	 */
	bic	tmp1, tmp1, #AT91_PMC_CSS
	str	tmp1, [pmc, #AT91_PMC_MCKR]

	wait_mckrdy

#ifdef SLOWDOWN_MASTER_CLOCK
	/*
	 * Set the Master Clock PRES and MDIV fields.
	 *
	 * See AT91RM9200 errata #27 and #28 for details.
	 */
	mov	tmp1, #0
	str	tmp1, [pmc, #AT91_PMC_MCKR]

	wait_mckrdy
#endif

	/* Save PLLA setting and disable it */
	ldr	tmp1, [pmc, #AT91_CKGR_PLLAR]
	str	tmp1, .saved_pllar

	mov	tmp1, #AT91_PMC_PLLCOUNT
	orr	tmp1, tmp1, #(1 << 29)		/* bit 29 always set */
	str	tmp1, [pmc, #AT91_CKGR_PLLAR]

	/* Save PLLB setting and disable it */
	ldr	tmp1, [pmc, #AT91_CKGR_PLLBR]
	str	tmp1, .saved_pllbr

	mov	tmp1, #AT91_PMC_PLLCOUNT
	str	tmp1, [pmc, #AT91_CKGR_PLLBR]

	/* Turn off the main oscillator */
	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
	bic	tmp1, tmp1, #AT91_PMC_MOSCEN
	orr	tmp1, tmp1, #AT91_PMC_KEY
	str	tmp1, [pmc, #AT91_CKGR_MOR]

	/* Wait for interrupt */
	mcr	p15, 0, tmp1, c7, c0, 4

	/* Turn on the main oscillator */
	ldr	tmp1, [pmc, #AT91_CKGR_MOR]
	orr	tmp1, tmp1, #AT91_PMC_MOSCEN
	orr	tmp1, tmp1, #AT91_PMC_KEY
	str	tmp1, [pmc, #AT91_CKGR_MOR]

	wait_moscrdy

	/* Restore PLLB setting */
	ldr	tmp1, .saved_pllbr
	str	tmp1, [pmc, #AT91_CKGR_PLLBR]

	tst	tmp1, #(AT91_PMC_MUL &  0xff0000)
	bne	1f
	tst	tmp1, #(AT91_PMC_MUL & ~0xff0000)
	beq	2f
1:
	wait_pllblock
2:

	/* Restore PLLA setting */
	ldr	tmp1, .saved_pllar
	str	tmp1, [pmc, #AT91_CKGR_PLLAR]

	tst	tmp1, #(AT91_PMC_MUL &  0xff0000)
	bne	3f
	tst	tmp1, #(AT91_PMC_MUL & ~0xff0000)
	beq	4f
3:
	wait_pllalock
4:

#ifdef SLOWDOWN_MASTER_CLOCK
	/*
	 * First set PRES if it was not 0,
	 * than set CSS and MDIV fields.
	 *
	 * See AT91RM9200 errata #27 and #28 for details.
	 */
	ldr	tmp1, .saved_mckr
	tst	tmp1, #AT91_PMC_PRES
	beq	2f
	and	tmp1, tmp1, #AT91_PMC_PRES
	str	tmp1, [pmc, #AT91_PMC_MCKR]

	wait_mckrdy
#endif

	/*
	 * Restore master clock setting
	 */
2:	ldr	tmp1, .saved_mckr
	str	tmp1, [pmc, #AT91_PMC_MCKR]

	wait_mckrdy

	/*
	 * at91rm9200 Memory controller
	 * Do nothing - self-refresh is automatically disabled.
	 */
	cmp	memctrl, #AT91_MEMCTRL_MC
	beq	ram_restored

	/*
	 * DDRSDR Memory controller
	 */
	cmp	memctrl, #AT91_MEMCTRL_DDRSDR
	bne	sdr_en_restore
	/* Restore MDR in case of LPDDR1 */
	ldr	tmp1, .saved_sam9_mdr
	str	tmp1, [sdramc, #AT91_DDRSDRC_MDR]
	/* Restore LPR on AT91 with DDRAM */
	ldr	tmp1, .saved_sam9_lpr
	str	tmp1, [sdramc, #AT91_DDRSDRC_LPR]

	/* if we use the second ram controller */
	cmp	ramc1, #0
	ldrne	tmp2, .saved_sam9_mdr1
	strne	tmp2, [ramc1, #AT91_DDRSDRC_MDR]
	ldrne	tmp2, .saved_sam9_lpr1
	strne	tmp2, [ramc1, #AT91_DDRSDRC_LPR]

	b	ram_restored

	/*
	 * SDRAMC Memory controller
	 */
sdr_en_restore:
	/* Restore LPR on AT91 with SDRAM */
	ldr	tmp1, .saved_sam9_lpr
	str	tmp1, [sdramc, #AT91_SDRAMC_LPR]

ram_restored:
	/* Restore registers, and return */
	ldmfd	sp!, {r4 - r12, pc}


.saved_mckr:
	.word 0

.saved_pllar:
	.word 0

.saved_pllbr:
	.word 0

.saved_sam9_lpr:
	.word 0

.saved_sam9_lpr1:
	.word 0

.saved_sam9_mdr:
	.word 0

.saved_sam9_mdr1:
	.word 0

ENTRY(at91_slow_clock_sz)
	.word .-at91_slow_clock
Commit	Line	Data
eaad2db0 AV	1	/*
	2	* arch/arm/mach-at91/pm_slow_clock.S
	3	*
	4	* Copyright (C) 2006 Savin Zlobec
	5	*
	6	* AT91SAM9 support:
	7	* Copyright (C) 2007 Anti Sullin <anti.sullin@artecdesign.ee
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*
	13	*/
	14
	15	#include <linux/linkage.h>
2edb90ae	16	#include <linux/clk/at91_pmc.h>
eaad2db0	17	#include <mach/hardware.h>
f363c407	18	#include <mach/at91_ramc.h>
eaad2db0	19
eaad2db0 AV	20	/*
	21	* When SLOWDOWN_MASTER_CLOCK is defined we will also slow down the Master
	22	* clock during suspend by adjusting its prescalar and divisor.
	23	* NOTE: This hasn't been shown to be stable on SAM9s; and on the RM9200 there
	24	* are errata regarding adjusting the prescalar and divisor.
	25	*/
	26	#undef SLOWDOWN_MASTER_CLOCK
	27
8ff12ad3 JCPV	28	pmc .req r0
	29	sdramc .req r1
	30	ramc1 .req r2
fb7e197b JCPV	31	memctrl .req r3
	32	tmp1 .req r4
	33	tmp2 .req r5
eaad2db0 AV	34
	35	/*
	36	* Wait until master clock is ready (after switching master clock source)
	37	*/
	38	.macro wait_mckrdy
ad4a38d2	39	1: ldr tmp1, [pmc, #AT91_PMC_SR]
0dcfed14	40	tst tmp1, #AT91_PMC_MCKRDY
eaad2db0	41	beq 1b
eaad2db0 AV	42	.endm
	43
	44	/*
	45	* Wait until master oscillator has stabilized.
	46	*/
	47	.macro wait_moscrdy
ad4a38d2	48	1: ldr tmp1, [pmc, #AT91_PMC_SR]
0dcfed14	49	tst tmp1, #AT91_PMC_MOSCS
eaad2db0	50	beq 1b
eaad2db0 AV	51	.endm
	52
	53	/*
	54	* Wait until PLLA has locked.
	55	*/
	56	.macro wait_pllalock
ad4a38d2	57	1: ldr tmp1, [pmc, #AT91_PMC_SR]
0dcfed14	58	tst tmp1, #AT91_PMC_LOCKA
eaad2db0	59	beq 1b
eaad2db0 AV	60	.endm
	61
	62	/*
	63	* Wait until PLLB has locked.
	64	*/
	65	.macro wait_pllblock
ad4a38d2	66	1: ldr tmp1, [pmc, #AT91_PMC_SR]
0dcfed14	67	tst tmp1, #AT91_PMC_LOCKB
eaad2db0	68	beq 1b
eaad2db0 AV	69	.endm
	70
	71	.text
	72
fb7e197b JCPV	73	/* void at91_slow_clock(void __iomem pmc, void __iomem sdramc,
	74	* void __iomem *ramc1, int memctrl)
	75	*/
eaad2db0 AV	76	ENTRY(at91_slow_clock)
eaad2db0 AV	77	/* Save registers on stack */
fb7e197b	78	stmfd sp!, {r4 - r12, lr}
eaad2db0 AV	79
	80	/*
	81	* Register usage:
8ff12ad3 JCPV	82	* R0 = Base address of AT91_PMC
	83	* R1 = Base address of RAM Controller (SDRAM, DDRSDR, or AT91_SYS)
	84	* R2 = Base address of second RAM Controller or 0 if not present
fb7e197b	85	* R3 = Memory controller
eaad2db0	86	* R4 = temporary register
fb7e197b	87	* R5 = temporary register
eaad2db0	88	*/
eaad2db0 AV	89
eaad2db0 AV	90	/* Drain write buffer */
0dcfed14 JCPV	91	mov tmp1, #0
0dcfed14 JCPV	92	mcr p15, 0, tmp1, c7, c10, 4
eaad2db0	93
fb7e197b JCPV	94	cmp memctrl, #AT91_MEMCTRL_MC
	95	bne ddr_sr_enable
	96
	97	/*
	98	* at91rm9200 Memory controller
	99	*/
eaad2db0	100	/* Put SDRAM in self-refresh mode */
0dcfed14	101	mov tmp1, #1
1a269ade	102	str tmp1, [sdramc, #AT91RM9200_SDRAMC_SRR]
fb7e197b JCPV	103	b sdr_sr_done
	104
	105	/*
	106	* DDRSDR Memory controller
	107	*/
	108	ddr_sr_enable:
	109	cmp memctrl, #AT91_MEMCTRL_DDRSDR
	110	bne sdr_sr_enable
eaad2db0	111
02f513a0 PR	112	/* LPDDR1 --> force DDR2 mode during self-refresh */
	113	ldr tmp1, [sdramc, #AT91_DDRSDRC_MDR]
	114	str tmp1, .saved_sam9_mdr
	115	bic tmp1, tmp1, #~AT91_DDRSDRC_MD
	116	cmp tmp1, #AT91_DDRSDRC_MD_LOW_POWER_DDR
	117	ldreq tmp1, [sdramc, #AT91_DDRSDRC_MDR]
	118	biceq tmp1, tmp1, #AT91_DDRSDRC_MD
	119	orreq tmp1, tmp1, #AT91_DDRSDRC_MD_DDR2
	120	streq tmp1, [sdramc, #AT91_DDRSDRC_MDR]
	121
7dca3343	122	/* prepare for DDRAM self-refresh mode */
0dcfed14 JCPV	123	ldr tmp1, [sdramc, #AT91_DDRSDRC_LPR]
	124	str tmp1, .saved_sam9_lpr
	125	bic tmp1, #AT91_DDRSDRC_LPCB
	126	orr tmp1, #AT91_DDRSDRC_LPCB_SELF_REFRESH
7dca3343 NF	127
7dca3343 NF	128	/* figure out if we use the second ram controller */
0dcfed14	129	cmp ramc1, #0
02f513a0 PR	130	beq ddr_no_2nd_ctrl
	131
	132	ldr tmp2, [ramc1, #AT91_DDRSDRC_MDR]
	133	str tmp2, .saved_sam9_mdr1
	134	bic tmp2, tmp2, #~AT91_DDRSDRC_MD
	135	cmp tmp2, #AT91_DDRSDRC_MD_LOW_POWER_DDR
	136	ldreq tmp2, [ramc1, #AT91_DDRSDRC_MDR]
	137	biceq tmp2, tmp2, #AT91_DDRSDRC_MD
	138	orreq tmp2, tmp2, #AT91_DDRSDRC_MD_DDR2
	139	streq tmp2, [ramc1, #AT91_DDRSDRC_MDR]
	140
	141	ldr tmp2, [ramc1, #AT91_DDRSDRC_LPR]
	142	str tmp2, .saved_sam9_lpr1
	143	bic tmp2, #AT91_DDRSDRC_LPCB
	144	orr tmp2, #AT91_DDRSDRC_LPCB_SELF_REFRESH
7dca3343 NF	145
7dca3343 NF	146	/* Enable DDRAM self-refresh mode */
02f513a0 PR	147	str tmp2, [ramc1, #AT91_DDRSDRC_LPR]
02f513a0 PR	148	ddr_no_2nd_ctrl:
0dcfed14	149	str tmp1, [sdramc, #AT91_DDRSDRC_LPR]
fb7e197b JCPV	150
	151	b sdr_sr_done
	152
	153	/*
	154	* SDRAMC Memory controller
	155	*/
	156	sdr_sr_enable:
eaad2db0	157	/* Enable SDRAM self-refresh mode */
0dcfed14 JCPV	158	ldr tmp1, [sdramc, #AT91_SDRAMC_LPR]
0dcfed14 JCPV	159	str tmp1, .saved_sam9_lpr
eaad2db0	160
0dcfed14 JCPV	161	bic tmp1, #AT91_SDRAMC_LPCB
	162	orr tmp1, #AT91_SDRAMC_LPCB_SELF_REFRESH
	163	str tmp1, [sdramc, #AT91_SDRAMC_LPR]
eaad2db0	164
fb7e197b	165	sdr_sr_done:
eaad2db0	166	/* Save Master clock setting */
b5514952	167	ldr tmp1, [pmc, #AT91_PMC_MCKR]
0dcfed14	168	str tmp1, .saved_mckr
eaad2db0 AV	169
	170	/*
	171	* Set the Master clock source to slow clock
	172	*/
0dcfed14	173	bic tmp1, tmp1, #AT91_PMC_CSS
b5514952	174	str tmp1, [pmc, #AT91_PMC_MCKR]
eaad2db0 AV	175
	176	wait_mckrdy
	177
	178	#ifdef SLOWDOWN_MASTER_CLOCK
	179	/*
	180	* Set the Master Clock PRES and MDIV fields.
	181	*
	182	* See AT91RM9200 errata #27 and #28 for details.
	183	*/
0dcfed14	184	mov tmp1, #0
b5514952	185	str tmp1, [pmc, #AT91_PMC_MCKR]
eaad2db0 AV	186
	187	wait_mckrdy
	188	#endif
	189
	190	/* Save PLLA setting and disable it */
b5514952	191	ldr tmp1, [pmc, #AT91_CKGR_PLLAR]
0dcfed14	192	str tmp1, .saved_pllar
eaad2db0	193
0dcfed14 JCPV	194	mov tmp1, #AT91_PMC_PLLCOUNT
0dcfed14 JCPV	195	orr tmp1, tmp1, #(1 << 29) /* bit 29 always set */
b5514952	196	str tmp1, [pmc, #AT91_CKGR_PLLAR]
eaad2db0	197
eaad2db0	198	/* Save PLLB setting and disable it */
b5514952	199	ldr tmp1, [pmc, #AT91_CKGR_PLLBR]
0dcfed14	200	str tmp1, .saved_pllbr
eaad2db0	201
0dcfed14	202	mov tmp1, #AT91_PMC_PLLCOUNT
b5514952	203	str tmp1, [pmc, #AT91_CKGR_PLLBR]
eaad2db0	204
eaad2db0	205	/* Turn off the main oscillator */
b5514952	206	ldr tmp1, [pmc, #AT91_CKGR_MOR]
0dcfed14	207	bic tmp1, tmp1, #AT91_PMC_MOSCEN
5957457a	208	orr tmp1, tmp1, #AT91_PMC_KEY
b5514952	209	str tmp1, [pmc, #AT91_CKGR_MOR]
eaad2db0 AV	210
eaad2db0 AV	211	/* Wait for interrupt */
0dcfed14	212	mcr p15, 0, tmp1, c7, c0, 4
eaad2db0 AV	213
eaad2db0 AV	214	/* Turn on the main oscillator */
b5514952	215	ldr tmp1, [pmc, #AT91_CKGR_MOR]
0dcfed14	216	orr tmp1, tmp1, #AT91_PMC_MOSCEN
5957457a	217	orr tmp1, tmp1, #AT91_PMC_KEY
b5514952	218	str tmp1, [pmc, #AT91_CKGR_MOR]
eaad2db0 AV	219
	220	wait_moscrdy
	221
	222	/* Restore PLLB setting */
0dcfed14	223	ldr tmp1, .saved_pllbr
b5514952	224	str tmp1, [pmc, #AT91_CKGR_PLLBR]
eaad2db0	225
0dcfed14	226	tst tmp1, #(AT91_PMC_MUL & 0xff0000)
9823f1a8	227	bne 1f
0dcfed14	228	tst tmp1, #(AT91_PMC_MUL & ~0xff0000)
9823f1a8 AL	229	beq 2f
9823f1a8 AL	230	1:
eaad2db0	231	wait_pllblock
9823f1a8	232	2:
eaad2db0 AV	233
eaad2db0 AV	234	/* Restore PLLA setting */
0dcfed14	235	ldr tmp1, .saved_pllar
b5514952	236	str tmp1, [pmc, #AT91_CKGR_PLLAR]
eaad2db0	237
0dcfed14	238	tst tmp1, #(AT91_PMC_MUL & 0xff0000)
9823f1a8	239	bne 3f
0dcfed14	240	tst tmp1, #(AT91_PMC_MUL & ~0xff0000)
9823f1a8 AL	241	beq 4f
9823f1a8 AL	242	3:
eaad2db0	243	wait_pllalock
9823f1a8	244	4:
eaad2db0 AV	245
	246	#ifdef SLOWDOWN_MASTER_CLOCK
	247	/*
	248	* First set PRES if it was not 0,
	249	* than set CSS and MDIV fields.
	250	*
	251	* See AT91RM9200 errata #27 and #28 for details.
	252	*/
0dcfed14 JCPV	253	ldr tmp1, .saved_mckr
0dcfed14 JCPV	254	tst tmp1, #AT91_PMC_PRES
eaad2db0	255	beq 2f
0dcfed14	256	and tmp1, tmp1, #AT91_PMC_PRES
b5514952	257	str tmp1, [pmc, #AT91_PMC_MCKR]
eaad2db0 AV	258
	259	wait_mckrdy
	260	#endif
	261
	262	/*
	263	* Restore master clock setting
	264	*/
0dcfed14	265	2: ldr tmp1, .saved_mckr
b5514952	266	str tmp1, [pmc, #AT91_PMC_MCKR]
eaad2db0 AV	267
	268	wait_mckrdy
	269
fb7e197b JCPV	270	/*
	271	* at91rm9200 Memory controller
	272	* Do nothing - self-refresh is automatically disabled.
	273	*/
	274	cmp memctrl, #AT91_MEMCTRL_MC
	275	beq ram_restored
	276
	277	/*
	278	* DDRSDR Memory controller
	279	*/
	280	cmp memctrl, #AT91_MEMCTRL_DDRSDR
	281	bne sdr_en_restore
02f513a0 PR	282	/* Restore MDR in case of LPDDR1 */
	283	ldr tmp1, .saved_sam9_mdr
	284	str tmp1, [sdramc, #AT91_DDRSDRC_MDR]
7dca3343	285	/* Restore LPR on AT91 with DDRAM */
0dcfed14 JCPV	286	ldr tmp1, .saved_sam9_lpr
0dcfed14 JCPV	287	str tmp1, [sdramc, #AT91_DDRSDRC_LPR]
7dca3343 NF	288
7dca3343 NF	289	/* if we use the second ram controller */
0dcfed14	290	cmp ramc1, #0
02f513a0 PR	291	ldrne tmp2, .saved_sam9_mdr1
02f513a0 PR	292	strne tmp2, [ramc1, #AT91_DDRSDRC_MDR]
0dcfed14 JCPV	293	ldrne tmp2, .saved_sam9_lpr1
0dcfed14 JCPV	294	strne tmp2, [ramc1, #AT91_DDRSDRC_LPR]
7dca3343	295
fb7e197b JCPV	296	b ram_restored
	297
	298	/*
	299	* SDRAMC Memory controller
	300	*/
	301	sdr_en_restore:
7dca3343	302	/* Restore LPR on AT91 with SDRAM */
0dcfed14 JCPV	303	ldr tmp1, .saved_sam9_lpr
0dcfed14 JCPV	304	str tmp1, [sdramc, #AT91_SDRAMC_LPR]
eaad2db0	305
fb7e197b	306	ram_restored:
eaad2db0	307	/* Restore registers, and return */
fb7e197b	308	ldmfd sp!, {r4 - r12, pc}
eaad2db0 AV	309
	310
	311	.saved_mckr:
	312	.word 0
	313
	314	.saved_pllar:
	315	.word 0
	316
	317	.saved_pllbr:
	318	.word 0
	319
	320	.saved_sam9_lpr:
	321	.word 0
	322
7dca3343 NF	323	.saved_sam9_lpr1:
	324	.word 0
	325
02f513a0 PR	326	.saved_sam9_mdr:
	327	.word 0
	328
	329	.saved_sam9_mdr1:
	330	.word 0
	331
eaad2db0 AV	332	ENTRY(at91_slow_clock_sz)
eaad2db0 AV	333	.word .-at91_slow_clock