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21d08b9d JCPV |
1 | /* |
2 | * Copyright (C) 2007 Atmel Corporation. | |
3 | * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | |
4 | * | |
5 | * Under GPLv2 | |
6 | */ | |
7 | ||
8 | #include <linux/module.h> | |
9 | #include <linux/io.h> | |
fb149f9e | 10 | #include <linux/mm.h> |
f22deee5 | 11 | #include <linux/pm.h> |
2b11ea5b | 12 | #include <linux/of_address.h> |
97e5e625 | 13 | #include <linux/pinctrl/machine.h> |
21d08b9d | 14 | |
86dfe446 | 15 | #include <asm/system_misc.h> |
21d08b9d JCPV |
16 | #include <asm/mach/map.h> |
17 | ||
18 | #include <mach/hardware.h> | |
19 | #include <mach/cpu.h> | |
8c3583b6 JCPV |
20 | #include <mach/at91_dbgu.h> |
21 | #include <mach/at91_pmc.h> | |
21d08b9d | 22 | |
176bdd2c | 23 | #include "at91_shdwc.h" |
21d08b9d JCPV |
24 | #include "soc.h" |
25 | #include "generic.h" | |
26 | ||
8c3583b6 JCPV |
27 | struct at91_init_soc __initdata at91_boot_soc; |
28 | ||
29 | struct at91_socinfo at91_soc_initdata; | |
30 | EXPORT_SYMBOL(at91_soc_initdata); | |
31 | ||
32 | void __init at91rm9200_set_type(int type) | |
33 | { | |
34 | if (type == ARCH_REVISON_9200_PQFP) | |
8c3583b6 | 35 | at91_soc_initdata.subtype = AT91_SOC_RM9200_PQFP; |
3e90772f NF |
36 | else |
37 | at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA; | |
38 | ||
39 | pr_info("AT91: filled in soc subtype: %s\n", | |
40 | at91_get_soc_subtype(&at91_soc_initdata)); | |
8c3583b6 | 41 | } |
21d08b9d | 42 | |
92100c12 JCPV |
43 | void __init at91_init_irq_default(void) |
44 | { | |
45 | at91_init_interrupts(at91_boot_soc.default_irq_priority); | |
46 | } | |
47 | ||
48 | void __init at91_init_interrupts(unsigned int *priority) | |
49 | { | |
50 | /* Initialize the AIC interrupt controller */ | |
738a0fd7 | 51 | at91_aic_init(priority, at91_extern_irq); |
92100c12 JCPV |
52 | |
53 | /* Enable GPIO interrupts */ | |
54 | at91_gpio_irq_setup(); | |
55 | } | |
56 | ||
a7776ec6 | 57 | void __iomem *at91_ramc_base[2]; |
9268c6c6 | 58 | EXPORT_SYMBOL_GPL(at91_ramc_base); |
a7776ec6 JCPV |
59 | |
60 | void __init at91_ioremap_ramc(int id, u32 addr, u32 size) | |
61 | { | |
62 | if (id < 0 || id > 1) { | |
63 | pr_emerg("Wrong RAM controller id (%d), cannot continue\n", id); | |
64 | BUG(); | |
65 | } | |
66 | at91_ramc_base[id] = ioremap(addr, size); | |
67 | if (!at91_ramc_base[id]) | |
68 | panic("Impossible to ioremap ramc.%d 0x%x\n", id, addr); | |
69 | } | |
70 | ||
f0051d82 JCPV |
71 | static struct map_desc sram_desc[2] __initdata; |
72 | ||
73 | void __init at91_init_sram(int bank, unsigned long base, unsigned int length) | |
74 | { | |
75 | struct map_desc *desc = &sram_desc[bank]; | |
76 | ||
dca4ba41 | 77 | desc->virtual = (unsigned long)AT91_IO_VIRT_BASE - length; |
f0051d82 JCPV |
78 | if (bank > 0) |
79 | desc->virtual -= sram_desc[bank - 1].length; | |
80 | ||
81 | desc->pfn = __phys_to_pfn(base); | |
82 | desc->length = length; | |
83 | desc->type = MT_DEVICE; | |
84 | ||
85 | pr_info("AT91: sram at 0x%lx of 0x%x mapped at 0x%lx\n", | |
86 | base, length, desc->virtual); | |
87 | ||
88 | iotable_init(desc, 1); | |
89 | } | |
90 | ||
ac09281a | 91 | static struct map_desc at91_io_desc __initdata __maybe_unused = { |
dca4ba41 | 92 | .virtual = (unsigned long)AT91_VA_BASE_SYS, |
21d08b9d JCPV |
93 | .pfn = __phys_to_pfn(AT91_BASE_SYS), |
94 | .length = SZ_16K, | |
95 | .type = MT_DEVICE, | |
96 | }; | |
97 | ||
8c3583b6 | 98 | static void __init soc_detect(u32 dbgu_base) |
21d08b9d | 99 | { |
8c3583b6 JCPV |
100 | u32 cidr, socid; |
101 | ||
102 | cidr = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_CIDR); | |
103 | socid = cidr & ~AT91_CIDR_VERSION; | |
21d08b9d | 104 | |
8c3583b6 | 105 | switch (socid) { |
8c3583b6 JCPV |
106 | case ARCH_ID_AT91RM9200: |
107 | at91_soc_initdata.type = AT91_SOC_RM9200; | |
36224d0f JCPV |
108 | if (at91_soc_initdata.subtype == AT91_SOC_SUBTYPE_NONE) |
109 | at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA; | |
21d08b9d | 110 | at91_boot_soc = at91rm9200_soc; |
8c3583b6 JCPV |
111 | break; |
112 | ||
113 | case ARCH_ID_AT91SAM9260: | |
114 | at91_soc_initdata.type = AT91_SOC_SAM9260; | |
21d08b9d | 115 | at91_boot_soc = at91sam9260_soc; |
8c3583b6 JCPV |
116 | break; |
117 | ||
118 | case ARCH_ID_AT91SAM9261: | |
119 | at91_soc_initdata.type = AT91_SOC_SAM9261; | |
21d08b9d | 120 | at91_boot_soc = at91sam9261_soc; |
8c3583b6 JCPV |
121 | break; |
122 | ||
123 | case ARCH_ID_AT91SAM9263: | |
124 | at91_soc_initdata.type = AT91_SOC_SAM9263; | |
21d08b9d | 125 | at91_boot_soc = at91sam9263_soc; |
8c3583b6 JCPV |
126 | break; |
127 | ||
128 | case ARCH_ID_AT91SAM9G20: | |
129 | at91_soc_initdata.type = AT91_SOC_SAM9G20; | |
21d08b9d | 130 | at91_boot_soc = at91sam9260_soc; |
8c3583b6 JCPV |
131 | break; |
132 | ||
133 | case ARCH_ID_AT91SAM9G45: | |
134 | at91_soc_initdata.type = AT91_SOC_SAM9G45; | |
135 | if (cidr == ARCH_ID_AT91SAM9G45ES) | |
136 | at91_soc_initdata.subtype = AT91_SOC_SAM9G45ES; | |
21d08b9d | 137 | at91_boot_soc = at91sam9g45_soc; |
8c3583b6 JCPV |
138 | break; |
139 | ||
140 | case ARCH_ID_AT91SAM9RL64: | |
141 | at91_soc_initdata.type = AT91_SOC_SAM9RL; | |
21d08b9d | 142 | at91_boot_soc = at91sam9rl_soc; |
8c3583b6 JCPV |
143 | break; |
144 | ||
145 | case ARCH_ID_AT91SAM9X5: | |
146 | at91_soc_initdata.type = AT91_SOC_SAM9X5; | |
21d08b9d | 147 | at91_boot_soc = at91sam9x5_soc; |
8c3583b6 | 148 | break; |
74db4fb9 HX |
149 | |
150 | case ARCH_ID_AT91SAM9N12: | |
151 | at91_soc_initdata.type = AT91_SOC_SAM9N12; | |
152 | at91_boot_soc = at91sam9n12_soc; | |
153 | break; | |
8f4b4794 LD |
154 | |
155 | case ARCH_ID_SAMA5D3: | |
156 | at91_soc_initdata.type = AT91_SOC_SAMA5D3; | |
157 | at91_boot_soc = sama5d3_soc; | |
158 | break; | |
8c3583b6 JCPV |
159 | } |
160 | ||
161 | /* at91sam9g10 */ | |
3d9a0183 | 162 | if ((socid & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10) { |
8c3583b6 JCPV |
163 | at91_soc_initdata.type = AT91_SOC_SAM9G10; |
164 | at91_boot_soc = at91sam9261_soc; | |
165 | } | |
166 | /* at91sam9xe */ | |
167 | else if ((cidr & AT91_CIDR_ARCH) == ARCH_FAMILY_AT91SAM9XE) { | |
168 | at91_soc_initdata.type = AT91_SOC_SAM9260; | |
169 | at91_soc_initdata.subtype = AT91_SOC_SAM9XE; | |
170 | at91_boot_soc = at91sam9260_soc; | |
171 | } | |
172 | ||
173 | if (!at91_soc_is_detected()) | |
174 | return; | |
175 | ||
176 | at91_soc_initdata.cidr = cidr; | |
177 | ||
178 | /* sub version of soc */ | |
179 | at91_soc_initdata.exid = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_EXID); | |
180 | ||
181 | if (at91_soc_initdata.type == AT91_SOC_SAM9G45) { | |
182 | switch (at91_soc_initdata.exid) { | |
183 | case ARCH_EXID_AT91SAM9M10: | |
184 | at91_soc_initdata.subtype = AT91_SOC_SAM9M10; | |
185 | break; | |
186 | case ARCH_EXID_AT91SAM9G46: | |
187 | at91_soc_initdata.subtype = AT91_SOC_SAM9G46; | |
188 | break; | |
189 | case ARCH_EXID_AT91SAM9M11: | |
190 | at91_soc_initdata.subtype = AT91_SOC_SAM9M11; | |
191 | break; | |
192 | } | |
193 | } | |
194 | ||
195 | if (at91_soc_initdata.type == AT91_SOC_SAM9X5) { | |
196 | switch (at91_soc_initdata.exid) { | |
197 | case ARCH_EXID_AT91SAM9G15: | |
198 | at91_soc_initdata.subtype = AT91_SOC_SAM9G15; | |
199 | break; | |
200 | case ARCH_EXID_AT91SAM9G35: | |
201 | at91_soc_initdata.subtype = AT91_SOC_SAM9G35; | |
202 | break; | |
203 | case ARCH_EXID_AT91SAM9X35: | |
204 | at91_soc_initdata.subtype = AT91_SOC_SAM9X35; | |
205 | break; | |
206 | case ARCH_EXID_AT91SAM9G25: | |
207 | at91_soc_initdata.subtype = AT91_SOC_SAM9G25; | |
208 | break; | |
209 | case ARCH_EXID_AT91SAM9X25: | |
210 | at91_soc_initdata.subtype = AT91_SOC_SAM9X25; | |
211 | break; | |
212 | } | |
213 | } | |
8f4b4794 LD |
214 | |
215 | if (at91_soc_initdata.type == AT91_SOC_SAMA5D3) { | |
216 | switch (at91_soc_initdata.exid) { | |
217 | case ARCH_EXID_SAMA5D31: | |
218 | at91_soc_initdata.subtype = AT91_SOC_SAMA5D31; | |
219 | break; | |
220 | case ARCH_EXID_SAMA5D33: | |
221 | at91_soc_initdata.subtype = AT91_SOC_SAMA5D33; | |
222 | break; | |
223 | case ARCH_EXID_SAMA5D34: | |
224 | at91_soc_initdata.subtype = AT91_SOC_SAMA5D34; | |
225 | break; | |
226 | case ARCH_EXID_SAMA5D35: | |
227 | at91_soc_initdata.subtype = AT91_SOC_SAMA5D35; | |
228 | break; | |
229 | } | |
230 | } | |
8c3583b6 JCPV |
231 | } |
232 | ||
233 | static const char *soc_name[] = { | |
234 | [AT91_SOC_RM9200] = "at91rm9200", | |
8c3583b6 JCPV |
235 | [AT91_SOC_SAM9260] = "at91sam9260", |
236 | [AT91_SOC_SAM9261] = "at91sam9261", | |
237 | [AT91_SOC_SAM9263] = "at91sam9263", | |
238 | [AT91_SOC_SAM9G10] = "at91sam9g10", | |
239 | [AT91_SOC_SAM9G20] = "at91sam9g20", | |
240 | [AT91_SOC_SAM9G45] = "at91sam9g45", | |
241 | [AT91_SOC_SAM9RL] = "at91sam9rl", | |
242 | [AT91_SOC_SAM9X5] = "at91sam9x5", | |
74db4fb9 | 243 | [AT91_SOC_SAM9N12] = "at91sam9n12", |
8f4b4794 | 244 | [AT91_SOC_SAMA5D3] = "sama5d3", |
8c3583b6 JCPV |
245 | [AT91_SOC_NONE] = "Unknown" |
246 | }; | |
247 | ||
248 | const char *at91_get_soc_type(struct at91_socinfo *c) | |
249 | { | |
250 | return soc_name[c->type]; | |
251 | } | |
252 | EXPORT_SYMBOL(at91_get_soc_type); | |
253 | ||
254 | static const char *soc_subtype_name[] = { | |
255 | [AT91_SOC_RM9200_BGA] = "at91rm9200 BGA", | |
256 | [AT91_SOC_RM9200_PQFP] = "at91rm9200 PQFP", | |
8c3583b6 JCPV |
257 | [AT91_SOC_SAM9XE] = "at91sam9xe", |
258 | [AT91_SOC_SAM9G45ES] = "at91sam9g45es", | |
259 | [AT91_SOC_SAM9M10] = "at91sam9m10", | |
260 | [AT91_SOC_SAM9G46] = "at91sam9g46", | |
261 | [AT91_SOC_SAM9M11] = "at91sam9m11", | |
262 | [AT91_SOC_SAM9G15] = "at91sam9g15", | |
263 | [AT91_SOC_SAM9G35] = "at91sam9g35", | |
264 | [AT91_SOC_SAM9X35] = "at91sam9x35", | |
265 | [AT91_SOC_SAM9G25] = "at91sam9g25", | |
266 | [AT91_SOC_SAM9X25] = "at91sam9x25", | |
8f4b4794 LD |
267 | [AT91_SOC_SAMA5D31] = "sama5d31", |
268 | [AT91_SOC_SAMA5D33] = "sama5d33", | |
269 | [AT91_SOC_SAMA5D34] = "sama5d34", | |
270 | [AT91_SOC_SAMA5D35] = "sama5d35", | |
8c3583b6 JCPV |
271 | [AT91_SOC_SUBTYPE_NONE] = "Unknown" |
272 | }; | |
273 | ||
274 | const char *at91_get_soc_subtype(struct at91_socinfo *c) | |
275 | { | |
276 | return soc_subtype_name[c->subtype]; | |
277 | } | |
278 | EXPORT_SYMBOL(at91_get_soc_subtype); | |
279 | ||
280 | void __init at91_map_io(void) | |
281 | { | |
282 | /* Map peripherals */ | |
283 | iotable_init(&at91_io_desc, 1); | |
284 | ||
285 | at91_soc_initdata.type = AT91_SOC_NONE; | |
286 | at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE; | |
287 | ||
13079a73 | 288 | soc_detect(AT91_BASE_DBGU0); |
8c3583b6 | 289 | if (!at91_soc_is_detected()) |
13079a73 | 290 | soc_detect(AT91_BASE_DBGU1); |
8c3583b6 JCPV |
291 | |
292 | if (!at91_soc_is_detected()) | |
293 | panic("AT91: Impossible to detect the SOC type"); | |
294 | ||
295 | pr_info("AT91: Detected soc type: %s\n", | |
296 | at91_get_soc_type(&at91_soc_initdata)); | |
297 | pr_info("AT91: Detected soc subtype: %s\n", | |
298 | at91_get_soc_subtype(&at91_soc_initdata)); | |
299 | ||
300 | if (!at91_soc_is_enabled()) | |
301 | panic("AT91: Soc not enabled"); | |
21d08b9d JCPV |
302 | |
303 | if (at91_boot_soc.map_io) | |
304 | at91_boot_soc.map_io(); | |
305 | } | |
306 | ||
f22deee5 JCPV |
307 | void __iomem *at91_shdwc_base = NULL; |
308 | ||
309 | static void at91sam9_poweroff(void) | |
310 | { | |
311 | at91_shdwc_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW); | |
312 | } | |
313 | ||
314 | void __init at91_ioremap_shdwc(u32 base_addr) | |
315 | { | |
316 | at91_shdwc_base = ioremap(base_addr, 16); | |
317 | if (!at91_shdwc_base) | |
318 | panic("Impossible to ioremap at91_shdwc_base\n"); | |
319 | pm_power_off = at91sam9_poweroff; | |
320 | } | |
321 | ||
e9f68b5c JCPV |
322 | void __iomem *at91_rstc_base; |
323 | ||
324 | void __init at91_ioremap_rstc(u32 base_addr) | |
325 | { | |
326 | at91_rstc_base = ioremap(base_addr, 16); | |
327 | if (!at91_rstc_base) | |
328 | panic("Impossible to ioremap at91_rstc_base\n"); | |
329 | } | |
330 | ||
4342d647 | 331 | void __iomem *at91_matrix_base; |
ac8c411c | 332 | EXPORT_SYMBOL_GPL(at91_matrix_base); |
4342d647 JCPV |
333 | |
334 | void __init at91_ioremap_matrix(u32 base_addr) | |
335 | { | |
336 | at91_matrix_base = ioremap(base_addr, 512); | |
337 | if (!at91_matrix_base) | |
338 | panic("Impossible to ioremap at91_matrix_base\n"); | |
339 | } | |
340 | ||
2b11ea5b | 341 | #if defined(CONFIG_OF) |
c8082d34 JCPV |
342 | static struct of_device_id rstc_ids[] = { |
343 | { .compatible = "atmel,at91sam9260-rstc", .data = at91sam9_alt_restart }, | |
344 | { .compatible = "atmel,at91sam9g45-rstc", .data = at91sam9g45_restart }, | |
345 | { /*sentinel*/ } | |
346 | }; | |
347 | ||
348 | static void at91_dt_rstc(void) | |
349 | { | |
350 | struct device_node *np; | |
351 | const struct of_device_id *of_id; | |
352 | ||
353 | np = of_find_matching_node(NULL, rstc_ids); | |
354 | if (!np) | |
355 | panic("unable to find compatible rstc node in dtb\n"); | |
356 | ||
357 | at91_rstc_base = of_iomap(np, 0); | |
358 | if (!at91_rstc_base) | |
359 | panic("unable to map rstc cpu registers\n"); | |
360 | ||
361 | of_id = of_match_node(rstc_ids, np); | |
362 | if (!of_id) | |
e7619459 | 363 | panic("AT91: rtsc no restart function available\n"); |
c8082d34 JCPV |
364 | |
365 | arm_pm_restart = of_id->data; | |
366 | ||
367 | of_node_put(np); | |
368 | } | |
369 | ||
a7776ec6 | 370 | static struct of_device_id ramc_ids[] = { |
397f8c3c | 371 | { .compatible = "atmel,at91rm9200-sdramc" }, |
a7776ec6 JCPV |
372 | { .compatible = "atmel,at91sam9260-sdramc" }, |
373 | { .compatible = "atmel,at91sam9g45-ddramc" }, | |
374 | { /*sentinel*/ } | |
375 | }; | |
376 | ||
377 | static void at91_dt_ramc(void) | |
378 | { | |
379 | struct device_node *np; | |
380 | ||
381 | np = of_find_matching_node(NULL, ramc_ids); | |
382 | if (!np) | |
95f287e5 | 383 | panic("unable to find compatible ram controller node in dtb\n"); |
a7776ec6 JCPV |
384 | |
385 | at91_ramc_base[0] = of_iomap(np, 0); | |
386 | if (!at91_ramc_base[0]) | |
387 | panic("unable to map ramc[0] cpu registers\n"); | |
388 | /* the controller may have 2 banks */ | |
389 | at91_ramc_base[1] = of_iomap(np, 1); | |
390 | ||
391 | of_node_put(np); | |
392 | } | |
393 | ||
82015c4e JCPV |
394 | static struct of_device_id shdwc_ids[] = { |
395 | { .compatible = "atmel,at91sam9260-shdwc", }, | |
396 | { .compatible = "atmel,at91sam9rl-shdwc", }, | |
397 | { .compatible = "atmel,at91sam9x5-shdwc", }, | |
398 | { /*sentinel*/ } | |
399 | }; | |
400 | ||
401 | static const char *shdwc_wakeup_modes[] = { | |
402 | [AT91_SHDW_WKMODE0_NONE] = "none", | |
403 | [AT91_SHDW_WKMODE0_HIGH] = "high", | |
404 | [AT91_SHDW_WKMODE0_LOW] = "low", | |
405 | [AT91_SHDW_WKMODE0_ANYLEVEL] = "any", | |
406 | }; | |
407 | ||
408 | const int at91_dtget_shdwc_wakeup_mode(struct device_node *np) | |
409 | { | |
410 | const char *pm; | |
411 | int err, i; | |
412 | ||
413 | err = of_property_read_string(np, "atmel,wakeup-mode", &pm); | |
414 | if (err < 0) | |
415 | return AT91_SHDW_WKMODE0_ANYLEVEL; | |
416 | ||
417 | for (i = 0; i < ARRAY_SIZE(shdwc_wakeup_modes); i++) | |
418 | if (!strcasecmp(pm, shdwc_wakeup_modes[i])) | |
419 | return i; | |
420 | ||
421 | return -ENODEV; | |
422 | } | |
423 | ||
424 | static void at91_dt_shdwc(void) | |
425 | { | |
426 | struct device_node *np; | |
427 | int wakeup_mode; | |
428 | u32 reg; | |
429 | u32 mode = 0; | |
430 | ||
431 | np = of_find_matching_node(NULL, shdwc_ids); | |
432 | if (!np) { | |
95f287e5 | 433 | pr_debug("AT91: unable to find compatible shutdown (shdwc) controller node in dtb\n"); |
82015c4e JCPV |
434 | return; |
435 | } | |
436 | ||
437 | at91_shdwc_base = of_iomap(np, 0); | |
438 | if (!at91_shdwc_base) | |
439 | panic("AT91: unable to map shdwc cpu registers\n"); | |
440 | ||
441 | wakeup_mode = at91_dtget_shdwc_wakeup_mode(np); | |
442 | if (wakeup_mode < 0) { | |
443 | pr_warn("AT91: shdwc unknown wakeup mode\n"); | |
444 | goto end; | |
445 | } | |
446 | ||
447 | if (!of_property_read_u32(np, "atmel,wakeup-counter", ®)) { | |
448 | if (reg > AT91_SHDW_CPTWK0_MAX) { | |
95f287e5 | 449 | pr_warn("AT91: shdwc wakeup counter 0x%x > 0x%x reduce it to 0x%x\n", |
82015c4e JCPV |
450 | reg, AT91_SHDW_CPTWK0_MAX, AT91_SHDW_CPTWK0_MAX); |
451 | reg = AT91_SHDW_CPTWK0_MAX; | |
452 | } | |
453 | mode |= AT91_SHDW_CPTWK0_(reg); | |
454 | } | |
455 | ||
456 | if (of_property_read_bool(np, "atmel,wakeup-rtc-timer")) | |
457 | mode |= AT91_SHDW_RTCWKEN; | |
458 | ||
459 | if (of_property_read_bool(np, "atmel,wakeup-rtt-timer")) | |
460 | mode |= AT91_SHDW_RTTWKEN; | |
461 | ||
462 | at91_shdwc_write(AT91_SHDW_MR, wakeup_mode | mode); | |
463 | ||
464 | end: | |
465 | pm_power_off = at91sam9_poweroff; | |
466 | ||
467 | of_node_put(np); | |
468 | } | |
469 | ||
397f8c3c JE |
470 | void __init at91rm9200_dt_initialize(void) |
471 | { | |
472 | at91_dt_ramc(); | |
473 | ||
474 | /* Init clock subsystem */ | |
475 | at91_dt_clock_init(); | |
476 | ||
477 | /* Register the processor-specific clocks */ | |
478 | at91_boot_soc.register_clocks(); | |
479 | ||
480 | at91_boot_soc.init(); | |
481 | } | |
482 | ||
2b11ea5b JCPV |
483 | void __init at91_dt_initialize(void) |
484 | { | |
c8082d34 | 485 | at91_dt_rstc(); |
a7776ec6 | 486 | at91_dt_ramc(); |
82015c4e | 487 | at91_dt_shdwc(); |
2b11ea5b | 488 | |
2b11ea5b | 489 | /* Init clock subsystem */ |
eb5e76ff | 490 | at91_dt_clock_init(); |
2b11ea5b JCPV |
491 | |
492 | /* Register the processor-specific clocks */ | |
493 | at91_boot_soc.register_clocks(); | |
494 | ||
5314ec8e JCPV |
495 | if (at91_boot_soc.init) |
496 | at91_boot_soc.init(); | |
2b11ea5b JCPV |
497 | } |
498 | #endif | |
499 | ||
21d08b9d JCPV |
500 | void __init at91_initialize(unsigned long main_clock) |
501 | { | |
cfa5a1fe JCPV |
502 | at91_boot_soc.ioremap_registers(); |
503 | ||
46539374 JCPV |
504 | /* Init clock subsystem */ |
505 | at91_clock_init(main_clock); | |
506 | ||
51ddec76 JCPV |
507 | /* Register the processor-specific clocks */ |
508 | at91_boot_soc.register_clocks(); | |
509 | ||
46539374 | 510 | at91_boot_soc.init(); |
97e5e625 JCPV |
511 | |
512 | pinctrl_provide_dummies(); | |
21d08b9d | 513 | } |