[deliverable/linux.git] / arch / arm / mach-at91 / setup.c

/*
 * Copyright (C) 2007 Atmel Corporation.
 * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
 *
 * Under GPLv2
 */

#include <linux/module.h>
#include <linux/io.h>
#include <linux/mm.h>
#include <linux/pm.h>
#include <linux/of_address.h>
#include <linux/pinctrl/machine.h>

#include <asm/system_misc.h>
#include <asm/mach/map.h>

#include <mach/hardware.h>
#include <mach/cpu.h>
#include <mach/at91_dbgu.h>
#include <mach/at91_pmc.h>
#include <mach/at91_shdwc.h>

#include "soc.h"
#include "generic.h"

struct at91_init_soc __initdata at91_boot_soc;

struct at91_socinfo at91_soc_initdata;
EXPORT_SYMBOL(at91_soc_initdata);

void __init at91rm9200_set_type(int type)
{
	if (type == ARCH_REVISON_9200_PQFP)
		at91_soc_initdata.subtype = AT91_SOC_RM9200_PQFP;
	else
		at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA;

	pr_info("AT91: filled in soc subtype: %s\n",
		at91_get_soc_subtype(&at91_soc_initdata));
}

void __init at91_init_irq_default(void)
{
	at91_init_interrupts(at91_boot_soc.default_irq_priority);
}

void __init at91_init_interrupts(unsigned int *priority)
{
	/* Initialize the AIC interrupt controller */
	at91_aic_init(priority);

	/* Enable GPIO interrupts */
	at91_gpio_irq_setup();
}

void __iomem *at91_ramc_base[2];
EXPORT_SYMBOL_GPL(at91_ramc_base);

void __init at91_ioremap_ramc(int id, u32 addr, u32 size)
{
	if (id < 0 || id > 1) {
		pr_emerg("Wrong RAM controller id (%d), cannot continue\n", id);
		BUG();
	}
	at91_ramc_base[id] = ioremap(addr, size);
	if (!at91_ramc_base[id])
		panic("Impossible to ioremap ramc.%d 0x%x\n", id, addr);
}

static struct map_desc sram_desc[2] __initdata;

void __init at91_init_sram(int bank, unsigned long base, unsigned int length)
{
	struct map_desc *desc = &sram_desc[bank];

	desc->virtual = (unsigned long)AT91_IO_VIRT_BASE - length;
	if (bank > 0)
		desc->virtual -= sram_desc[bank - 1].length;

	desc->pfn = __phys_to_pfn(base);
	desc->length = length;
	desc->type = MT_DEVICE;

	pr_info("AT91: sram at 0x%lx of 0x%x mapped at 0x%lx\n",
		base, length, desc->virtual);

	iotable_init(desc, 1);
}

static struct map_desc at91_io_desc __initdata __maybe_unused = {
	.virtual	= (unsigned long)AT91_VA_BASE_SYS,
	.pfn		= __phys_to_pfn(AT91_BASE_SYS),
	.length		= SZ_16K,
	.type		= MT_DEVICE,
};

static void __init soc_detect(u32 dbgu_base)
{
	u32 cidr, socid;

	cidr = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_CIDR);
	socid = cidr & ~AT91_CIDR_VERSION;

	switch (socid) {
	case ARCH_ID_AT91RM9200:
		at91_soc_initdata.type = AT91_SOC_RM9200;
		at91_boot_soc = at91rm9200_soc;
		break;

	case ARCH_ID_AT91SAM9260:
		at91_soc_initdata.type = AT91_SOC_SAM9260;
		at91_boot_soc = at91sam9260_soc;
		break;

	case ARCH_ID_AT91SAM9261:
		at91_soc_initdata.type = AT91_SOC_SAM9261;
		at91_boot_soc = at91sam9261_soc;
		break;

	case ARCH_ID_AT91SAM9263:
		at91_soc_initdata.type = AT91_SOC_SAM9263;
		at91_boot_soc = at91sam9263_soc;
		break;

	case ARCH_ID_AT91SAM9G20:
		at91_soc_initdata.type = AT91_SOC_SAM9G20;
		at91_boot_soc = at91sam9260_soc;
		break;

	case ARCH_ID_AT91SAM9G45:
		at91_soc_initdata.type = AT91_SOC_SAM9G45;
		if (cidr == ARCH_ID_AT91SAM9G45ES)
			at91_soc_initdata.subtype = AT91_SOC_SAM9G45ES;
		at91_boot_soc = at91sam9g45_soc;
		break;

	case ARCH_ID_AT91SAM9RL64:
		at91_soc_initdata.type = AT91_SOC_SAM9RL;
		at91_boot_soc = at91sam9rl_soc;
		break;

	case ARCH_ID_AT91SAM9X5:
		at91_soc_initdata.type = AT91_SOC_SAM9X5;
		at91_boot_soc = at91sam9x5_soc;
		break;

	case ARCH_ID_AT91SAM9N12:
		at91_soc_initdata.type = AT91_SOC_SAM9N12;
		at91_boot_soc = at91sam9n12_soc;
		break;
	}

	/* at91sam9g10 */
	if ((cidr & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10) {
		at91_soc_initdata.type = AT91_SOC_SAM9G10;
		at91_boot_soc = at91sam9261_soc;
	}
	/* at91sam9xe */
	else if ((cidr & AT91_CIDR_ARCH) == ARCH_FAMILY_AT91SAM9XE) {
		at91_soc_initdata.type = AT91_SOC_SAM9260;
		at91_soc_initdata.subtype = AT91_SOC_SAM9XE;
		at91_boot_soc = at91sam9260_soc;
	}

	if (!at91_soc_is_detected())
		return;

	at91_soc_initdata.cidr = cidr;

	/* sub version of soc */
	at91_soc_initdata.exid = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_EXID);

	if (at91_soc_initdata.type == AT91_SOC_SAM9G45) {
		switch (at91_soc_initdata.exid) {
		case ARCH_EXID_AT91SAM9M10:
			at91_soc_initdata.subtype = AT91_SOC_SAM9M10;
			break;
		case ARCH_EXID_AT91SAM9G46:
			at91_soc_initdata.subtype = AT91_SOC_SAM9G46;
			break;
		case ARCH_EXID_AT91SAM9M11:
			at91_soc_initdata.subtype = AT91_SOC_SAM9M11;
			break;
		}
	}

	if (at91_soc_initdata.type == AT91_SOC_SAM9X5) {
		switch (at91_soc_initdata.exid) {
		case ARCH_EXID_AT91SAM9G15:
			at91_soc_initdata.subtype = AT91_SOC_SAM9G15;
			break;
		case ARCH_EXID_AT91SAM9G35:
			at91_soc_initdata.subtype = AT91_SOC_SAM9G35;
			break;
		case ARCH_EXID_AT91SAM9X35:
			at91_soc_initdata.subtype = AT91_SOC_SAM9X35;
			break;
		case ARCH_EXID_AT91SAM9G25:
			at91_soc_initdata.subtype = AT91_SOC_SAM9G25;
			break;
		case ARCH_EXID_AT91SAM9X25:
			at91_soc_initdata.subtype = AT91_SOC_SAM9X25;
			break;
		}
	}
}

static const char *soc_name[] = {
	[AT91_SOC_RM9200]	= "at91rm9200",
	[AT91_SOC_SAM9260]	= "at91sam9260",
	[AT91_SOC_SAM9261]	= "at91sam9261",
	[AT91_SOC_SAM9263]	= "at91sam9263",
	[AT91_SOC_SAM9G10]	= "at91sam9g10",
	[AT91_SOC_SAM9G20]	= "at91sam9g20",
	[AT91_SOC_SAM9G45]	= "at91sam9g45",
	[AT91_SOC_SAM9RL]	= "at91sam9rl",
	[AT91_SOC_SAM9X5]	= "at91sam9x5",
	[AT91_SOC_SAM9N12]	= "at91sam9n12",
	[AT91_SOC_NONE]		= "Unknown"
};

const char *at91_get_soc_type(struct at91_socinfo *c)
{
	return soc_name[c->type];
}
EXPORT_SYMBOL(at91_get_soc_type);

static const char *soc_subtype_name[] = {
	[AT91_SOC_RM9200_BGA]	= "at91rm9200 BGA",
	[AT91_SOC_RM9200_PQFP]	= "at91rm9200 PQFP",
	[AT91_SOC_SAM9XE]	= "at91sam9xe",
	[AT91_SOC_SAM9G45ES]	= "at91sam9g45es",
	[AT91_SOC_SAM9M10]	= "at91sam9m10",
	[AT91_SOC_SAM9G46]	= "at91sam9g46",
	[AT91_SOC_SAM9M11]	= "at91sam9m11",
	[AT91_SOC_SAM9G15]	= "at91sam9g15",
	[AT91_SOC_SAM9G35]	= "at91sam9g35",
	[AT91_SOC_SAM9X35]	= "at91sam9x35",
	[AT91_SOC_SAM9G25]	= "at91sam9g25",
	[AT91_SOC_SAM9X25]	= "at91sam9x25",
	[AT91_SOC_SUBTYPE_NONE]	= "Unknown"
};

const char *at91_get_soc_subtype(struct at91_socinfo *c)
{
	return soc_subtype_name[c->subtype];
}
EXPORT_SYMBOL(at91_get_soc_subtype);

void __init at91_map_io(void)
{
	/* Map peripherals */
	iotable_init(&at91_io_desc, 1);

	at91_soc_initdata.type = AT91_SOC_NONE;
	at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;

	soc_detect(AT91_BASE_DBGU0);
	if (!at91_soc_is_detected())
		soc_detect(AT91_BASE_DBGU1);

	if (!at91_soc_is_detected())
		panic("AT91: Impossible to detect the SOC type");

	pr_info("AT91: Detected soc type: %s\n",
		at91_get_soc_type(&at91_soc_initdata));
	pr_info("AT91: Detected soc subtype: %s\n",
		at91_get_soc_subtype(&at91_soc_initdata));

	if (!at91_soc_is_enabled())
		panic("AT91: Soc not enabled");

	if (at91_boot_soc.map_io)
		at91_boot_soc.map_io();
}

void __iomem *at91_shdwc_base = NULL;

static void at91sam9_poweroff(void)
{
	at91_shdwc_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
}

void __init at91_ioremap_shdwc(u32 base_addr)
{
	at91_shdwc_base = ioremap(base_addr, 16);
	if (!at91_shdwc_base)
		panic("Impossible to ioremap at91_shdwc_base\n");
	pm_power_off = at91sam9_poweroff;
}

void __iomem *at91_rstc_base;

void __init at91_ioremap_rstc(u32 base_addr)
{
	at91_rstc_base = ioremap(base_addr, 16);
	if (!at91_rstc_base)
		panic("Impossible to ioremap at91_rstc_base\n");
}

void __iomem *at91_matrix_base;
EXPORT_SYMBOL_GPL(at91_matrix_base);

void __init at91_ioremap_matrix(u32 base_addr)
{
	at91_matrix_base = ioremap(base_addr, 512);
	if (!at91_matrix_base)
		panic("Impossible to ioremap at91_matrix_base\n");
}

#if defined(CONFIG_OF)
static struct of_device_id rstc_ids[] = {
	{ .compatible = "atmel,at91sam9260-rstc", .data = at91sam9_alt_restart },
	{ .compatible = "atmel,at91sam9g45-rstc", .data = at91sam9g45_restart },
	{ /*sentinel*/ }
};

static void at91_dt_rstc(void)
{
	struct device_node *np;
	const struct of_device_id *of_id;

	np = of_find_matching_node(NULL, rstc_ids);
	if (!np)
		panic("unable to find compatible rstc node in dtb\n");

	at91_rstc_base = of_iomap(np, 0);
	if (!at91_rstc_base)
		panic("unable to map rstc cpu registers\n");

	of_id = of_match_node(rstc_ids, np);
	if (!of_id)
		panic("AT91: rtsc no restart function availlable\n");

	arm_pm_restart = of_id->data;

	of_node_put(np);
}

static struct of_device_id ramc_ids[] = {
	{ .compatible = "atmel,at91sam9260-sdramc" },
	{ .compatible = "atmel,at91sam9g45-ddramc" },
	{ /*sentinel*/ }
};

static void at91_dt_ramc(void)
{
	struct device_node *np;

	np = of_find_matching_node(NULL, ramc_ids);
	if (!np)
		panic("unable to find compatible ram conroller node in dtb\n");

	at91_ramc_base[0] = of_iomap(np, 0);
	if (!at91_ramc_base[0])
		panic("unable to map ramc[0] cpu registers\n");
	/* the controller may have 2 banks */
	at91_ramc_base[1] = of_iomap(np, 1);

	of_node_put(np);
}

static struct of_device_id shdwc_ids[] = {
	{ .compatible = "atmel,at91sam9260-shdwc", },
	{ .compatible = "atmel,at91sam9rl-shdwc", },
	{ .compatible = "atmel,at91sam9x5-shdwc", },
	{ /*sentinel*/ }
};

static const char *shdwc_wakeup_modes[] = {
	[AT91_SHDW_WKMODE0_NONE]	= "none",
	[AT91_SHDW_WKMODE0_HIGH]	= "high",
	[AT91_SHDW_WKMODE0_LOW]		= "low",
	[AT91_SHDW_WKMODE0_ANYLEVEL]	= "any",
};

const int at91_dtget_shdwc_wakeup_mode(struct device_node *np)
{
	const char *pm;
	int err, i;

	err = of_property_read_string(np, "atmel,wakeup-mode", &pm);
	if (err < 0)
		return AT91_SHDW_WKMODE0_ANYLEVEL;

	for (i = 0; i < ARRAY_SIZE(shdwc_wakeup_modes); i++)
		if (!strcasecmp(pm, shdwc_wakeup_modes[i]))
			return i;

	return -ENODEV;
}

static void at91_dt_shdwc(void)
{
	struct device_node *np;
	int wakeup_mode;
	u32 reg;
	u32 mode = 0;

	np = of_find_matching_node(NULL, shdwc_ids);
	if (!np) {
		pr_debug("AT91: unable to find compatible shutdown (shdwc) conroller node in dtb\n");
		return;
	}

	at91_shdwc_base = of_iomap(np, 0);
	if (!at91_shdwc_base)
		panic("AT91: unable to map shdwc cpu registers\n");

	wakeup_mode = at91_dtget_shdwc_wakeup_mode(np);
	if (wakeup_mode < 0) {
		pr_warn("AT91: shdwc unknown wakeup mode\n");
		goto end;
	}

	if (!of_property_read_u32(np, "atmel,wakeup-counter", &reg)) {
		if (reg > AT91_SHDW_CPTWK0_MAX) {
			pr_warn("AT91: shdwc wakeup conter 0x%x > 0x%x reduce it to 0x%x\n",
				reg, AT91_SHDW_CPTWK0_MAX, AT91_SHDW_CPTWK0_MAX);
			reg = AT91_SHDW_CPTWK0_MAX;
		}
		mode |= AT91_SHDW_CPTWK0_(reg);
	}

	if (of_property_read_bool(np, "atmel,wakeup-rtc-timer"))
			mode |= AT91_SHDW_RTCWKEN;

	if (of_property_read_bool(np, "atmel,wakeup-rtt-timer"))
			mode |= AT91_SHDW_RTTWKEN;

	at91_shdwc_write(AT91_SHDW_MR, wakeup_mode | mode);

end:
	pm_power_off = at91sam9_poweroff;

	of_node_put(np);
}

void __init at91_dt_initialize(void)
{
	at91_dt_rstc();
	at91_dt_ramc();
	at91_dt_shdwc();

	/* Init clock subsystem */
	at91_dt_clock_init();

	/* Register the processor-specific clocks */
	at91_boot_soc.register_clocks();

	if (at91_boot_soc.init)
		at91_boot_soc.init();
}
#endif

void __init at91_initialize(unsigned long main_clock)
{
	at91_boot_soc.ioremap_registers();

	/* Init clock subsystem */
	at91_clock_init(main_clock);

	/* Register the processor-specific clocks */
	at91_boot_soc.register_clocks();

	at91_boot_soc.init();

	pinctrl_provide_dummies();
}
Commit	Line	Data
21d08b9d JCPV	1	/*
	2	* Copyright (C) 2007 Atmel Corporation.
	3	* Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
	4	*
	5	* Under GPLv2
	6	*/
	7
	8	#include <linux/module.h>
	9	#include <linux/io.h>
fb149f9e	10	#include <linux/mm.h>
f22deee5	11	#include <linux/pm.h>
2b11ea5b	12	#include <linux/of_address.h>
97e5e625	13	#include <linux/pinctrl/machine.h>
21d08b9d	14
86dfe446	15	#include <asm/system_misc.h>
21d08b9d JCPV	16	#include <asm/mach/map.h>
	17
	18	#include <mach/hardware.h>
	19	#include <mach/cpu.h>
8c3583b6 JCPV	20	#include <mach/at91_dbgu.h>
8c3583b6 JCPV	21	#include <mach/at91_pmc.h>
f22deee5	22	#include <mach/at91_shdwc.h>
21d08b9d JCPV	23
	24	#include "soc.h"
	25	#include "generic.h"
	26
8c3583b6 JCPV	27	struct at91_init_soc __initdata at91_boot_soc;
	28
	29	struct at91_socinfo at91_soc_initdata;
	30	EXPORT_SYMBOL(at91_soc_initdata);
	31
	32	void __init at91rm9200_set_type(int type)
	33	{
	34	if (type == ARCH_REVISON_9200_PQFP)
8c3583b6	35	at91_soc_initdata.subtype = AT91_SOC_RM9200_PQFP;
3e90772f NF	36	else
	37	at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA;
	38
	39	pr_info("AT91: filled in soc subtype: %s\n",
	40	at91_get_soc_subtype(&at91_soc_initdata));
8c3583b6	41	}
21d08b9d	42
92100c12 JCPV	43	void __init at91_init_irq_default(void)
	44	{
	45	at91_init_interrupts(at91_boot_soc.default_irq_priority);
	46	}
	47
	48	void __init at91_init_interrupts(unsigned int *priority)
	49	{
	50	/* Initialize the AIC interrupt controller */
	51	at91_aic_init(priority);
	52
	53	/* Enable GPIO interrupts */
	54	at91_gpio_irq_setup();
	55	}
	56
a7776ec6	57	void __iomem *at91_ramc_base[2];
9268c6c6	58	EXPORT_SYMBOL_GPL(at91_ramc_base);
a7776ec6 JCPV	59
	60	void __init at91_ioremap_ramc(int id, u32 addr, u32 size)
	61	{
	62	if (id < 0 \|\| id > 1) {
	63	pr_emerg("Wrong RAM controller id (%d), cannot continue\n", id);
	64	BUG();
	65	}
	66	at91_ramc_base[id] = ioremap(addr, size);
	67	if (!at91_ramc_base[id])
	68	panic("Impossible to ioremap ramc.%d 0x%x\n", id, addr);
	69	}
	70
f0051d82 JCPV	71	static struct map_desc sram_desc[2] __initdata;
	72
	73	void __init at91_init_sram(int bank, unsigned long base, unsigned int length)
	74	{
	75	struct map_desc *desc = &sram_desc[bank];
	76
dca4ba41	77	desc->virtual = (unsigned long)AT91_IO_VIRT_BASE - length;
f0051d82 JCPV	78	if (bank > 0)
	79	desc->virtual -= sram_desc[bank - 1].length;
	80
	81	desc->pfn = __phys_to_pfn(base);
	82	desc->length = length;
	83	desc->type = MT_DEVICE;
	84
	85	pr_info("AT91: sram at 0x%lx of 0x%x mapped at 0x%lx\n",
	86	base, length, desc->virtual);
	87
	88	iotable_init(desc, 1);
	89	}
	90
ac09281a	91	static struct map_desc at91_io_desc __initdata __maybe_unused = {
dca4ba41	92	.virtual = (unsigned long)AT91_VA_BASE_SYS,
21d08b9d JCPV	93	.pfn = __phys_to_pfn(AT91_BASE_SYS),
	94	.length = SZ_16K,
	95	.type = MT_DEVICE,
	96	};
	97
8c3583b6	98	static void __init soc_detect(u32 dbgu_base)
21d08b9d	99	{
8c3583b6 JCPV	100	u32 cidr, socid;
	101
	102	cidr = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_CIDR);
	103	socid = cidr & ~AT91_CIDR_VERSION;
21d08b9d	104
8c3583b6	105	switch (socid) {
8c3583b6 JCPV	106	case ARCH_ID_AT91RM9200:
8c3583b6 JCPV	107	at91_soc_initdata.type = AT91_SOC_RM9200;
21d08b9d	108	at91_boot_soc = at91rm9200_soc;
8c3583b6 JCPV	109	break;
	110
	111	case ARCH_ID_AT91SAM9260:
	112	at91_soc_initdata.type = AT91_SOC_SAM9260;
21d08b9d	113	at91_boot_soc = at91sam9260_soc;
8c3583b6 JCPV	114	break;
	115
	116	case ARCH_ID_AT91SAM9261:
	117	at91_soc_initdata.type = AT91_SOC_SAM9261;
21d08b9d	118	at91_boot_soc = at91sam9261_soc;
8c3583b6 JCPV	119	break;
	120
	121	case ARCH_ID_AT91SAM9263:
	122	at91_soc_initdata.type = AT91_SOC_SAM9263;
21d08b9d	123	at91_boot_soc = at91sam9263_soc;
8c3583b6 JCPV	124	break;
	125
	126	case ARCH_ID_AT91SAM9G20:
	127	at91_soc_initdata.type = AT91_SOC_SAM9G20;
21d08b9d	128	at91_boot_soc = at91sam9260_soc;
8c3583b6 JCPV	129	break;
	130
	131	case ARCH_ID_AT91SAM9G45:
	132	at91_soc_initdata.type = AT91_SOC_SAM9G45;
	133	if (cidr == ARCH_ID_AT91SAM9G45ES)
	134	at91_soc_initdata.subtype = AT91_SOC_SAM9G45ES;
21d08b9d	135	at91_boot_soc = at91sam9g45_soc;
8c3583b6 JCPV	136	break;
	137
	138	case ARCH_ID_AT91SAM9RL64:
	139	at91_soc_initdata.type = AT91_SOC_SAM9RL;
21d08b9d	140	at91_boot_soc = at91sam9rl_soc;
8c3583b6 JCPV	141	break;
	142
	143	case ARCH_ID_AT91SAM9X5:
	144	at91_soc_initdata.type = AT91_SOC_SAM9X5;
21d08b9d	145	at91_boot_soc = at91sam9x5_soc;
8c3583b6	146	break;
74db4fb9 HX	147
	148	case ARCH_ID_AT91SAM9N12:
	149	at91_soc_initdata.type = AT91_SOC_SAM9N12;
	150	at91_boot_soc = at91sam9n12_soc;
	151	break;
8c3583b6 JCPV	152	}
	153
	154	/* at91sam9g10 */
	155	if ((cidr & ~AT91_CIDR_EXT) == ARCH_ID_AT91SAM9G10) {
	156	at91_soc_initdata.type = AT91_SOC_SAM9G10;
	157	at91_boot_soc = at91sam9261_soc;
	158	}
	159	/* at91sam9xe */
	160	else if ((cidr & AT91_CIDR_ARCH) == ARCH_FAMILY_AT91SAM9XE) {
	161	at91_soc_initdata.type = AT91_SOC_SAM9260;
	162	at91_soc_initdata.subtype = AT91_SOC_SAM9XE;
	163	at91_boot_soc = at91sam9260_soc;
	164	}
	165
	166	if (!at91_soc_is_detected())
	167	return;
	168
	169	at91_soc_initdata.cidr = cidr;
	170
	171	/* sub version of soc */
	172	at91_soc_initdata.exid = __raw_readl(AT91_IO_P2V(dbgu_base) + AT91_DBGU_EXID);
	173
	174	if (at91_soc_initdata.type == AT91_SOC_SAM9G45) {
	175	switch (at91_soc_initdata.exid) {
	176	case ARCH_EXID_AT91SAM9M10:
	177	at91_soc_initdata.subtype = AT91_SOC_SAM9M10;
	178	break;
	179	case ARCH_EXID_AT91SAM9G46:
	180	at91_soc_initdata.subtype = AT91_SOC_SAM9G46;
	181	break;
	182	case ARCH_EXID_AT91SAM9M11:
	183	at91_soc_initdata.subtype = AT91_SOC_SAM9M11;
	184	break;
	185	}
	186	}
	187
	188	if (at91_soc_initdata.type == AT91_SOC_SAM9X5) {
	189	switch (at91_soc_initdata.exid) {
	190	case ARCH_EXID_AT91SAM9G15:
	191	at91_soc_initdata.subtype = AT91_SOC_SAM9G15;
	192	break;
	193	case ARCH_EXID_AT91SAM9G35:
	194	at91_soc_initdata.subtype = AT91_SOC_SAM9G35;
	195	break;
	196	case ARCH_EXID_AT91SAM9X35:
	197	at91_soc_initdata.subtype = AT91_SOC_SAM9X35;
	198	break;
	199	case ARCH_EXID_AT91SAM9G25:
	200	at91_soc_initdata.subtype = AT91_SOC_SAM9G25;
	201	break;
	202	case ARCH_EXID_AT91SAM9X25:
	203	at91_soc_initdata.subtype = AT91_SOC_SAM9X25;
	204	break;
	205	}
	206	}
	207	}
	208
	209	static const char *soc_name[] = {
	210	[AT91_SOC_RM9200] = "at91rm9200",
8c3583b6 JCPV	211	[AT91_SOC_SAM9260] = "at91sam9260",
	212	[AT91_SOC_SAM9261] = "at91sam9261",
	213	[AT91_SOC_SAM9263] = "at91sam9263",
	214	[AT91_SOC_SAM9G10] = "at91sam9g10",
	215	[AT91_SOC_SAM9G20] = "at91sam9g20",
	216	[AT91_SOC_SAM9G45] = "at91sam9g45",
	217	[AT91_SOC_SAM9RL] = "at91sam9rl",
	218	[AT91_SOC_SAM9X5] = "at91sam9x5",
74db4fb9	219	[AT91_SOC_SAM9N12] = "at91sam9n12",
8c3583b6 JCPV	220	[AT91_SOC_NONE] = "Unknown"
	221	};
	222
	223	const char at91_get_soc_type(struct at91_socinfo c)
	224	{
	225	return soc_name[c->type];
	226	}
	227	EXPORT_SYMBOL(at91_get_soc_type);
	228
	229	static const char *soc_subtype_name[] = {
	230	[AT91_SOC_RM9200_BGA] = "at91rm9200 BGA",
	231	[AT91_SOC_RM9200_PQFP] = "at91rm9200 PQFP",
8c3583b6 JCPV	232	[AT91_SOC_SAM9XE] = "at91sam9xe",
	233	[AT91_SOC_SAM9G45ES] = "at91sam9g45es",
	234	[AT91_SOC_SAM9M10] = "at91sam9m10",
	235	[AT91_SOC_SAM9G46] = "at91sam9g46",
	236	[AT91_SOC_SAM9M11] = "at91sam9m11",
	237	[AT91_SOC_SAM9G15] = "at91sam9g15",
	238	[AT91_SOC_SAM9G35] = "at91sam9g35",
	239	[AT91_SOC_SAM9X35] = "at91sam9x35",
	240	[AT91_SOC_SAM9G25] = "at91sam9g25",
	241	[AT91_SOC_SAM9X25] = "at91sam9x25",
	242	[AT91_SOC_SUBTYPE_NONE] = "Unknown"
	243	};
	244
	245	const char at91_get_soc_subtype(struct at91_socinfo c)
	246	{
	247	return soc_subtype_name[c->subtype];
	248	}
	249	EXPORT_SYMBOL(at91_get_soc_subtype);
	250
	251	void __init at91_map_io(void)
	252	{
	253	/* Map peripherals */
	254	iotable_init(&at91_io_desc, 1);
	255
	256	at91_soc_initdata.type = AT91_SOC_NONE;
	257	at91_soc_initdata.subtype = AT91_SOC_SUBTYPE_NONE;
	258
13079a73	259	soc_detect(AT91_BASE_DBGU0);
8c3583b6	260	if (!at91_soc_is_detected())
13079a73	261	soc_detect(AT91_BASE_DBGU1);
8c3583b6 JCPV	262
	263	if (!at91_soc_is_detected())
	264	panic("AT91: Impossible to detect the SOC type");
	265
	266	pr_info("AT91: Detected soc type: %s\n",
	267	at91_get_soc_type(&at91_soc_initdata));
	268	pr_info("AT91: Detected soc subtype: %s\n",
	269	at91_get_soc_subtype(&at91_soc_initdata));
	270
	271	if (!at91_soc_is_enabled())
	272	panic("AT91: Soc not enabled");
21d08b9d JCPV	273
	274	if (at91_boot_soc.map_io)
	275	at91_boot_soc.map_io();
	276	}
	277
f22deee5 JCPV	278	void __iomem *at91_shdwc_base = NULL;
	279
	280	static void at91sam9_poweroff(void)
	281	{
	282	at91_shdwc_write(AT91_SHDW_CR, AT91_SHDW_KEY \| AT91_SHDW_SHDW);
	283	}
	284
	285	void __init at91_ioremap_shdwc(u32 base_addr)
	286	{
	287	at91_shdwc_base = ioremap(base_addr, 16);
	288	if (!at91_shdwc_base)
	289	panic("Impossible to ioremap at91_shdwc_base\n");
	290	pm_power_off = at91sam9_poweroff;
	291	}
	292
e9f68b5c JCPV	293	void __iomem *at91_rstc_base;
	294
	295	void __init at91_ioremap_rstc(u32 base_addr)
	296	{
	297	at91_rstc_base = ioremap(base_addr, 16);
	298	if (!at91_rstc_base)
	299	panic("Impossible to ioremap at91_rstc_base\n");
	300	}
	301
4342d647	302	void __iomem *at91_matrix_base;
ac8c411c	303	EXPORT_SYMBOL_GPL(at91_matrix_base);
4342d647 JCPV	304
	305	void __init at91_ioremap_matrix(u32 base_addr)
	306	{
	307	at91_matrix_base = ioremap(base_addr, 512);
	308	if (!at91_matrix_base)
	309	panic("Impossible to ioremap at91_matrix_base\n");
	310	}
	311
2b11ea5b	312	#if defined(CONFIG_OF)
c8082d34 JCPV	313	static struct of_device_id rstc_ids[] = {
	314	{ .compatible = "atmel,at91sam9260-rstc", .data = at91sam9_alt_restart },
	315	{ .compatible = "atmel,at91sam9g45-rstc", .data = at91sam9g45_restart },
	316	{ /sentinel/ }
	317	};
	318
	319	static void at91_dt_rstc(void)
	320	{
	321	struct device_node *np;
	322	const struct of_device_id *of_id;
	323
	324	np = of_find_matching_node(NULL, rstc_ids);
	325	if (!np)
	326	panic("unable to find compatible rstc node in dtb\n");
	327
	328	at91_rstc_base = of_iomap(np, 0);
	329	if (!at91_rstc_base)
	330	panic("unable to map rstc cpu registers\n");
	331
	332	of_id = of_match_node(rstc_ids, np);
	333	if (!of_id)
	334	panic("AT91: rtsc no restart function availlable\n");
	335
	336	arm_pm_restart = of_id->data;
	337
	338	of_node_put(np);
	339	}
	340
a7776ec6 JCPV	341	static struct of_device_id ramc_ids[] = {
	342	{ .compatible = "atmel,at91sam9260-sdramc" },
	343	{ .compatible = "atmel,at91sam9g45-ddramc" },
	344	{ /sentinel/ }
	345	};
	346
	347	static void at91_dt_ramc(void)
	348	{
	349	struct device_node *np;
	350
	351	np = of_find_matching_node(NULL, ramc_ids);
	352	if (!np)
	353	panic("unable to find compatible ram conroller node in dtb\n");
	354
	355	at91_ramc_base[0] = of_iomap(np, 0);
	356	if (!at91_ramc_base[0])
	357	panic("unable to map ramc[0] cpu registers\n");
	358	/* the controller may have 2 banks */
	359	at91_ramc_base[1] = of_iomap(np, 1);
	360
	361	of_node_put(np);
	362	}
	363
82015c4e JCPV	364	static struct of_device_id shdwc_ids[] = {
	365	{ .compatible = "atmel,at91sam9260-shdwc", },
	366	{ .compatible = "atmel,at91sam9rl-shdwc", },
	367	{ .compatible = "atmel,at91sam9x5-shdwc", },
	368	{ /sentinel/ }
	369	};
	370
	371	static const char *shdwc_wakeup_modes[] = {
	372	[AT91_SHDW_WKMODE0_NONE] = "none",
	373	[AT91_SHDW_WKMODE0_HIGH] = "high",
	374	[AT91_SHDW_WKMODE0_LOW] = "low",
	375	[AT91_SHDW_WKMODE0_ANYLEVEL] = "any",
	376	};
	377
	378	const int at91_dtget_shdwc_wakeup_mode(struct device_node *np)
	379	{
	380	const char *pm;
	381	int err, i;
	382
	383	err = of_property_read_string(np, "atmel,wakeup-mode", &pm);
	384	if (err < 0)
	385	return AT91_SHDW_WKMODE0_ANYLEVEL;
	386
	387	for (i = 0; i < ARRAY_SIZE(shdwc_wakeup_modes); i++)
	388	if (!strcasecmp(pm, shdwc_wakeup_modes[i]))
	389	return i;
	390
	391	return -ENODEV;
	392	}
	393
	394	static void at91_dt_shdwc(void)
	395	{
	396	struct device_node *np;
	397	int wakeup_mode;
	398	u32 reg;
	399	u32 mode = 0;
	400
	401	np = of_find_matching_node(NULL, shdwc_ids);
	402	if (!np) {
	403	pr_debug("AT91: unable to find compatible shutdown (shdwc) conroller node in dtb\n");
	404	return;
	405	}
	406
	407	at91_shdwc_base = of_iomap(np, 0);
	408	if (!at91_shdwc_base)
	409	panic("AT91: unable to map shdwc cpu registers\n");
	410
	411	wakeup_mode = at91_dtget_shdwc_wakeup_mode(np);
	412	if (wakeup_mode < 0) {
	413	pr_warn("AT91: shdwc unknown wakeup mode\n");
	414	goto end;
	415	}
	416
	417	if (!of_property_read_u32(np, "atmel,wakeup-counter", &reg)) {
	418	if (reg > AT91_SHDW_CPTWK0_MAX) {
	419	pr_warn("AT91: shdwc wakeup conter 0x%x > 0x%x reduce it to 0x%x\n",
	420	reg, AT91_SHDW_CPTWK0_MAX, AT91_SHDW_CPTWK0_MAX);
	421	reg = AT91_SHDW_CPTWK0_MAX;
	422	}
	423	mode \|= AT91_SHDW_CPTWK0_(reg);
	424	}
	425
	426	if (of_property_read_bool(np, "atmel,wakeup-rtc-timer"))
	427	mode \|= AT91_SHDW_RTCWKEN;
428
429	if (of_property_read_bool(np, "atmel,wakeup-rtt-timer"))
430	mode \|= AT91_SHDW_RTTWKEN;
431
432	at91_shdwc_write(AT91_SHDW_MR, wakeup_mode \| mode);
433
434	end:
435	pm_power_off = at91sam9_poweroff;
436
437	of_node_put(np);
438	}
439
2b11ea5b JCPV	440	void __init at91_dt_initialize(void)
2b11ea5b JCPV	441	{
c8082d34	442	at91_dt_rstc();
a7776ec6	443	at91_dt_ramc();
82015c4e	444	at91_dt_shdwc();
2b11ea5b	445
2b11ea5b	446	/* Init clock subsystem */
eb5e76ff	447	at91_dt_clock_init();
2b11ea5b JCPV	448
	449	/* Register the processor-specific clocks */
	450	at91_boot_soc.register_clocks();
	451
5314ec8e JCPV	452	if (at91_boot_soc.init)
5314ec8e JCPV	453	at91_boot_soc.init();
2b11ea5b JCPV	454	}
	455	#endif
	456
21d08b9d JCPV	457	void __init at91_initialize(unsigned long main_clock)
21d08b9d JCPV	458	{
cfa5a1fe JCPV	459	at91_boot_soc.ioremap_registers();
cfa5a1fe JCPV	460
46539374 JCPV	461	/* Init clock subsystem */
	462	at91_clock_init(main_clock);
	463
51ddec76 JCPV	464	/* Register the processor-specific clocks */
	465	at91_boot_soc.register_clocks();
	466
46539374	467	at91_boot_soc.init();
97e5e625 JCPV	468
97e5e625 JCPV	469	pinctrl_provide_dummies();
21d08b9d	470	}