[deliverable/linux.git] / arch / arm / mach-at91rm9200 / gpio.c

/*
 * linux/arch/arm/mach-at91rm9200/gpio.c
 *
 * Copyright (C) 2005 HP Labs
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/errno.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/module.h>

#include <asm/io.h>
#include <asm/hardware.h>
#include <asm/arch/gpio.h>

static const u32 pio_controller_offset[4] = {
	AT91_PIOA,
	AT91_PIOB,
	AT91_PIOC,
	AT91_PIOD,
};

static inline void __iomem *pin_to_controller(unsigned pin)
{
	void __iomem *sys_base = (void __iomem *) AT91_VA_BASE_SYS;

	pin -= PIN_BASE;
	pin /= 32;
	if (likely(pin < BGA_GPIO_BANKS))
		return sys_base + pio_controller_offset[pin];

	return NULL;
}

static inline unsigned pin_to_mask(unsigned pin)
{
	pin -= PIN_BASE;
	return 1 << (pin % 32);
}


/*--------------------------------------------------------------------------*/

/* Not all hardware capabilities are exposed through these calls; they
 * only encapsulate the most common features and modes.  (So if you
 * want to change signals in groups, do it directly.)
 *
 * Bootloaders will usually handle some of the pin multiplexing setup.
 * The intent is certainly that by the time Linux is fully booted, all
 * pins should have been fully initialized.  These setup calls should
 * only be used by board setup routines, or possibly in driver probe().
 *
 * For bootloaders doing all that setup, these calls could be inlined
 * as NOPs so Linux won't duplicate any setup code
 */


/*
 * mux the pin to the "A" internal peripheral role.
 */
int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup)
{
	void __iomem	*pio = pin_to_controller(pin);
	unsigned	mask = pin_to_mask(pin);

	if (!pio)
		return -EINVAL;

	__raw_writel(mask, pio + PIO_IDR);
	__raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
	__raw_writel(mask, pio + PIO_ASR);
	__raw_writel(mask, pio + PIO_PDR);
	return 0;
}
EXPORT_SYMBOL(at91_set_A_periph);


/*
 * mux the pin to the "B" internal peripheral role.
 */
int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup)
{
	void __iomem	*pio = pin_to_controller(pin);
	unsigned	mask = pin_to_mask(pin);

	if (!pio)
		return -EINVAL;

	__raw_writel(mask, pio + PIO_IDR);
	__raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
	__raw_writel(mask, pio + PIO_BSR);
	__raw_writel(mask, pio + PIO_PDR);
	return 0;
}
EXPORT_SYMBOL(at91_set_B_periph);


/*
 * mux the pin to the gpio controller (instead of "A" or "B" peripheral), and
 * configure it for an input.
 */
int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup)
{
	void __iomem	*pio = pin_to_controller(pin);
	unsigned	mask = pin_to_mask(pin);

	if (!pio)
		return -EINVAL;

	__raw_writel(mask, pio + PIO_IDR);
	__raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
	__raw_writel(mask, pio + PIO_ODR);
	__raw_writel(mask, pio + PIO_PER);
	return 0;
}
EXPORT_SYMBOL(at91_set_gpio_input);


/*
 * mux the pin to the gpio controller (instead of "A" or "B" peripheral),
 * and configure it for an output.
 */
int __init_or_module at91_set_gpio_output(unsigned pin, int value)
{
	void __iomem	*pio = pin_to_controller(pin);
	unsigned	mask = pin_to_mask(pin);

	if (!pio)
		return -EINVAL;

	__raw_writel(mask, pio + PIO_IDR);
	__raw_writel(mask, pio + PIO_PUDR);
	__raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
	__raw_writel(mask, pio + PIO_OER);
	__raw_writel(mask, pio + PIO_PER);
	return 0;
}
EXPORT_SYMBOL(at91_set_gpio_output);


/*
 * enable/disable the glitch filter; mostly used with IRQ handling.
 */
int __init_or_module at91_set_deglitch(unsigned pin, int is_on)
{
	void __iomem	*pio = pin_to_controller(pin);
	unsigned	mask = pin_to_mask(pin);

	if (!pio)
		return -EINVAL;
	__raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
	return 0;
}
EXPORT_SYMBOL(at91_set_deglitch);

/*
 * enable/disable the multi-driver; This is only valid for output and
 * allows the output pin to run as an open collector output.
 */
int __init_or_module at91_set_multi_drive(unsigned pin, int is_on)
{
	void __iomem	*pio = pin_to_controller(pin);
	unsigned	mask = pin_to_mask(pin);

	if (!pio)
		return -EINVAL;

	__raw_writel(mask, pio + (is_on ? PIO_MDER : PIO_MDDR));
	return 0;
}
EXPORT_SYMBOL(at91_set_multi_drive);

/*--------------------------------------------------------------------------*/


/*
 * assuming the pin is muxed as a gpio output, set its value.
 */
int at91_set_gpio_value(unsigned pin, int value)
{
	void __iomem	*pio = pin_to_controller(pin);
	unsigned	mask = pin_to_mask(pin);

	if (!pio)
		return -EINVAL;
	__raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
	return 0;
}
EXPORT_SYMBOL(at91_set_gpio_value);


/*
 * read the pin's value (works even if it's not muxed as a gpio).
 */
int at91_get_gpio_value(unsigned pin)
{
	void __iomem	*pio = pin_to_controller(pin);
	unsigned	mask = pin_to_mask(pin);
	u32		pdsr;

	if (!pio)
		return -EINVAL;
	pdsr = __raw_readl(pio + PIO_PDSR);
	return (pdsr & mask) != 0;
}
EXPORT_SYMBOL(at91_get_gpio_value);

/*--------------------------------------------------------------------------*/

#ifdef CONFIG_PM

static u32 wakeups[BGA_GPIO_BANKS];
static u32 backups[BGA_GPIO_BANKS];

static int gpio_irq_set_wake(unsigned pin, unsigned state)
{
	unsigned	mask = pin_to_mask(pin);

	pin -= PIN_BASE;
	pin /= 32;

	if (unlikely(pin >= BGA_GPIO_BANKS))
		return -EINVAL;

	if (state)
		wakeups[pin] |= mask;
	else
		wakeups[pin] &= ~mask;

	return 0;
}

void at91_gpio_suspend(void)
{
	int i;

	for (i = 0; i < BGA_GPIO_BANKS; i++) {
		u32 pio = pio_controller_offset[i];

		/*
		 * Note: drivers should have disabled GPIO interrupts that
		 * aren't supposed to be wakeup sources.
		 * But that is not much good on ARM.....  disable_irq() does
		 * not update the hardware immediately, so the hardware mask
		 * (IMR) has the wrong value (not current, too much is
		 * permitted).
		 *
		 * Our workaround is to disable all non-wakeup IRQs ...
		 * which is exactly what correct drivers asked for in the
		 * first place!
		 */
		backups[i] = at91_sys_read(pio + PIO_IMR);
		at91_sys_write(pio_controller_offset[i] + PIO_IDR, backups[i]);
		at91_sys_write(pio_controller_offset[i] + PIO_IER, wakeups[i]);

		if (!wakeups[i]) {
			disable_irq_wake(AT91_ID_PIOA + i);
			at91_sys_write(AT91_PMC_PCDR, 1 << (AT91_ID_PIOA + i));
		} else {
			enable_irq_wake(AT91_ID_PIOA + i);
#ifdef CONFIG_PM_DEBUG
			printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", "ABCD"[i], wakeups[i]);
#endif
		}
	}
}

void at91_gpio_resume(void)
{
	int i;

	for (i = 0; i < BGA_GPIO_BANKS; i++) {
		at91_sys_write(pio_controller_offset[i] + PIO_IDR, wakeups[i]);
		at91_sys_write(pio_controller_offset[i] + PIO_IER, backups[i]);
	}

	at91_sys_write(AT91_PMC_PCER,
			  (1 << AT91_ID_PIOA)
			| (1 << AT91_ID_PIOB)
			| (1 << AT91_ID_PIOC)
			| (1 << AT91_ID_PIOD));
}

#else
#define gpio_irq_set_wake	NULL
#endif


/* Several AIC controller irqs are dispatched through this GPIO handler.
 * To use any AT91_PIN_* as an externally triggered IRQ, first call
 * at91_set_gpio_input() then maybe enable its glitch filter.
 * Then just request_irq() with the pin ID; it works like any ARM IRQ
 * handler, though it always triggers on rising and falling edges.
 *
 * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
 * configuring them with at91_set_a_periph() or at91_set_b_periph().
 * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering.
 */

static void gpio_irq_mask(unsigned pin)
{
	void __iomem	*pio = pin_to_controller(pin);
	unsigned	mask = pin_to_mask(pin);

	if (pio)
		__raw_writel(mask, pio + PIO_IDR);
}

static void gpio_irq_unmask(unsigned pin)
{
	void __iomem	*pio = pin_to_controller(pin);
	unsigned	mask = pin_to_mask(pin);

	if (pio)
		__raw_writel(mask, pio + PIO_IER);
}

static int gpio_irq_type(unsigned pin, unsigned type)
{
	return (type == IRQT_BOTHEDGE) ? 0 : -EINVAL;
}

static struct irq_chip gpio_irqchip = {
	.name		= "GPIO",
	.mask		= gpio_irq_mask,
	.unmask		= gpio_irq_unmask,
	.set_type	= gpio_irq_type,
	.set_wake	= gpio_irq_set_wake,
};

static void gpio_irq_handler(unsigned irq, struct irqdesc *desc, struct pt_regs *regs)
{
	unsigned	pin;
	struct irqdesc	*gpio;
	void __iomem	*pio;
	u32		isr;

	pio = get_irq_chip_data(irq);

	/* temporarily mask (level sensitive) parent IRQ */
	desc->chip->ack(irq);
	for (;;) {
		/* reading ISR acks the pending (edge triggered) GPIO interrupt */
		isr = __raw_readl(pio + PIO_ISR) & __raw_readl(pio + PIO_IMR);
		if (!isr)
			break;

		pin = (unsigned) get_irq_data(irq);
		gpio = &irq_desc[pin];

		while (isr) {
			if (isr & 1) {
				if (unlikely(gpio->depth)) {
					/*
					 * The core ARM interrupt handler lazily disables IRQs so
					 * another IRQ must be generated before it actually gets
					 * here to be disabled on the GPIO controller.
					 */
					gpio_irq_mask(pin);
				}
				else
					desc_handle_irq(pin, gpio, regs);
			}
			pin++;
			gpio++;
			isr >>= 1;
		}
	}
	desc->chip->unmask(irq);
	/* now it may re-trigger */
}

/* call this from board-specific init_irq */
void __init at91_gpio_irq_setup(unsigned banks)
{
	unsigned	pioc, pin, id;

	if (banks > 4)
		banks = 4;
	for (pioc = 0, pin = PIN_BASE, id = AT91_ID_PIOA;
			pioc < banks;
			pioc++, id++) {
		void __iomem	*controller;
		unsigned	i;

		controller = (void __iomem *) AT91_VA_BASE_SYS + pio_controller_offset[pioc];
		__raw_writel(~0, controller + PIO_IDR);

		set_irq_data(id, (void *) pin);
		set_irq_chipdata(id, controller);

		for (i = 0; i < 32; i++, pin++) {
			/*
			 * Can use the "simple" and not "edge" handler since it's
			 * shorter, and the AIC handles interupts sanely.
			 */
			set_irq_chip(pin, &gpio_irqchip);
			set_irq_handler(pin, do_simple_IRQ);
			set_irq_flags(pin, IRQF_VALID);
		}

		set_irq_chained_handler(id, gpio_irq_handler);
	}
	pr_info("AT91: %d gpio irqs in %d banks\n", pin - PIN_BASE, banks);
}
Commit	Line	Data
73a59c1c SP	1	/*
	2	* linux/arch/arm/mach-at91rm9200/gpio.c
	3	*
	4	* Copyright (C) 2005 HP Labs
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*/
	11
	12	#include <linux/errno.h>
07d265dd TG	13	#include <linux/interrupt.h>
07d265dd TG	14	#include <linux/irq.h>
73a59c1c SP	15	#include <linux/kernel.h>
	16	#include <linux/list.h>
	17	#include <linux/module.h>
	18
	19	#include <asm/io.h>
ea75ee9a	20	#include <asm/hardware.h>
73a59c1c SP	21	#include <asm/arch/gpio.h>
	22
	23	static const u32 pio_controller_offset[4] = {
	24	AT91_PIOA,
	25	AT91_PIOB,
	26	AT91_PIOC,
	27	AT91_PIOD,
	28	};
	29
	30	static inline void __iomem *pin_to_controller(unsigned pin)
	31	{
	32	void __iomem sys_base = (void __iomem ) AT91_VA_BASE_SYS;
	33
	34	pin -= PIN_BASE;
	35	pin /= 32;
	36	if (likely(pin < BGA_GPIO_BANKS))
	37	return sys_base + pio_controller_offset[pin];
	38
	39	return NULL;
	40	}
	41
	42	static inline unsigned pin_to_mask(unsigned pin)
	43	{
	44	pin -= PIN_BASE;
	45	return 1 << (pin % 32);
	46	}
	47
	48
	49	/--------------------------------------------------------------------------/
	50
	51	/* Not all hardware capabilities are exposed through these calls; they
	52	* only encapsulate the most common features and modes. (So if you
	53	* want to change signals in groups, do it directly.)
	54	*
	55	* Bootloaders will usually handle some of the pin multiplexing setup.
	56	* The intent is certainly that by the time Linux is fully booted, all
	57	* pins should have been fully initialized. These setup calls should
	58	* only be used by board setup routines, or possibly in driver probe().
	59	*
	60	* For bootloaders doing all that setup, these calls could be inlined
	61	* as NOPs so Linux won't duplicate any setup code
	62	*/
	63
	64
	65	/*
	66	* mux the pin to the "A" internal peripheral role.
	67	*/
	68	int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup)
	69	{
	70	void __iomem *pio = pin_to_controller(pin);
	71	unsigned mask = pin_to_mask(pin);
	72
	73	if (!pio)
	74	return -EINVAL;
	75
	76	__raw_writel(mask, pio + PIO_IDR);
	77	__raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
	78	__raw_writel(mask, pio + PIO_ASR);
	79	__raw_writel(mask, pio + PIO_PDR);
	80	return 0;
	81	}
	82	EXPORT_SYMBOL(at91_set_A_periph);
	83
	84
85	/*
86	* mux the pin to the "B" internal peripheral role.
87	*/
88	int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup)
89	{
90	void __iomem *pio = pin_to_controller(pin);
91	unsigned mask = pin_to_mask(pin);
92
93	if (!pio)
94	return -EINVAL;
95
96	__raw_writel(mask, pio + PIO_IDR);
97	__raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
98	__raw_writel(mask, pio + PIO_BSR);
99	__raw_writel(mask, pio + PIO_PDR);
100	return 0;
101	}
102	EXPORT_SYMBOL(at91_set_B_periph);
103
104
105	/*
106	* mux the pin to the gpio controller (instead of "A" or "B" peripheral), and
107	* configure it for an input.
108	*/
109	int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup)
110	{
111	void __iomem *pio = pin_to_controller(pin);
112	unsigned mask = pin_to_mask(pin);
113
114	if (!pio)
115	return -EINVAL;
116
117	__raw_writel(mask, pio + PIO_IDR);
118	__raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
119	__raw_writel(mask, pio + PIO_ODR);
120	__raw_writel(mask, pio + PIO_PER);
121	return 0;
122	}
123	EXPORT_SYMBOL(at91_set_gpio_input);
124
125
126	/*
127	* mux the pin to the gpio controller (instead of "A" or "B" peripheral),
128	* and configure it for an output.
129	*/
130	int __init_or_module at91_set_gpio_output(unsigned pin, int value)
131	{
132	void __iomem *pio = pin_to_controller(pin);
133	unsigned mask = pin_to_mask(pin);
134
135	if (!pio)
136	return -EINVAL;
137
138	__raw_writel(mask, pio + PIO_IDR);
139	__raw_writel(mask, pio + PIO_PUDR);
140	__raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
141	__raw_writel(mask, pio + PIO_OER);
142	__raw_writel(mask, pio + PIO_PER);
143	return 0;
144	}
145	EXPORT_SYMBOL(at91_set_gpio_output);
146
147
148	/*
149	* enable/disable the glitch filter; mostly used with IRQ handling.
150	*/
151	int __init_or_module at91_set_deglitch(unsigned pin, int is_on)
152	{
153	void __iomem *pio = pin_to_controller(pin);
154	unsigned mask = pin_to_mask(pin);
155
156	if (!pio)
157	return -EINVAL;
158	__raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
159	return 0;
160	}
161	EXPORT_SYMBOL(at91_set_deglitch);
162
df666b9c AV	163	/*
	164	* enable/disable the multi-driver; This is only valid for output and
	165	* allows the output pin to run as an open collector output.
	166	*/
	167	int __init_or_module at91_set_multi_drive(unsigned pin, int is_on)
	168	{
	169	void __iomem *pio = pin_to_controller(pin);
	170	unsigned mask = pin_to_mask(pin);
	171
	172	if (!pio)
	173	return -EINVAL;
	174
	175	__raw_writel(mask, pio + (is_on ? PIO_MDER : PIO_MDDR));
	176	return 0;
	177	}
	178	EXPORT_SYMBOL(at91_set_multi_drive);
	179
73a59c1c SP	180	/--------------------------------------------------------------------------/
	181
	182
	183	/*
	184	* assuming the pin is muxed as a gpio output, set its value.
	185	*/
	186	int at91_set_gpio_value(unsigned pin, int value)
	187	{
	188	void __iomem *pio = pin_to_controller(pin);
	189	unsigned mask = pin_to_mask(pin);
	190
	191	if (!pio)
	192	return -EINVAL;
	193	__raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
	194	return 0;
	195	}
	196	EXPORT_SYMBOL(at91_set_gpio_value);
	197
	198
	199	/*
	200	* read the pin's value (works even if it's not muxed as a gpio).
	201	*/
	202	int at91_get_gpio_value(unsigned pin)
	203	{
	204	void __iomem *pio = pin_to_controller(pin);
	205	unsigned mask = pin_to_mask(pin);
	206	u32 pdsr;
	207
	208	if (!pio)
	209	return -EINVAL;
	210	pdsr = __raw_readl(pio + PIO_PDSR);
	211	return (pdsr & mask) != 0;
	212	}
	213	EXPORT_SYMBOL(at91_get_gpio_value);
	214
	215	/--------------------------------------------------------------------------/
	216
814138ff AV	217	#ifdef CONFIG_PM
	218
	219	static u32 wakeups[BGA_GPIO_BANKS];
	220	static u32 backups[BGA_GPIO_BANKS];
	221
	222	static int gpio_irq_set_wake(unsigned pin, unsigned state)
	223	{
	224	unsigned mask = pin_to_mask(pin);
	225
	226	pin -= PIN_BASE;
	227	pin /= 32;
	228
	229	if (unlikely(pin >= BGA_GPIO_BANKS))
	230	return -EINVAL;
	231
	232	if (state)
	233	wakeups[pin] \|= mask;
	234	else
	235	wakeups[pin] &= ~mask;
	236
	237	return 0;
	238	}
	239
	240	void at91_gpio_suspend(void)
	241	{
	242	int i;
	243
	244	for (i = 0; i < BGA_GPIO_BANKS; i++) {
	245	u32 pio = pio_controller_offset[i];
	246
	247	/*
	248	* Note: drivers should have disabled GPIO interrupts that
	249	* aren't supposed to be wakeup sources.
	250	* But that is not much good on ARM..... disable_irq() does
	251	* not update the hardware immediately, so the hardware mask
	252	* (IMR) has the wrong value (not current, too much is
	253	* permitted).
	254	*
	255	* Our workaround is to disable all non-wakeup IRQs ...
	256	* which is exactly what correct drivers asked for in the
	257	* first place!
	258	*/
	259	backups[i] = at91_sys_read(pio + PIO_IMR);
	260	at91_sys_write(pio_controller_offset[i] + PIO_IDR, backups[i]);
	261	at91_sys_write(pio_controller_offset[i] + PIO_IER, wakeups[i]);
	262
	263	if (!wakeups[i]) {
	264	disable_irq_wake(AT91_ID_PIOA + i);
	265	at91_sys_write(AT91_PMC_PCDR, 1 << (AT91_ID_PIOA + i));
	266	} else {
	267	enable_irq_wake(AT91_ID_PIOA + i);
	268	#ifdef CONFIG_PM_DEBUG
	269	printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", "ABCD"[i], wakeups[i]);
	270	#endif
	271	}
	272	}
	273	}
	274
	275	void at91_gpio_resume(void)
	276	{
	277	int i;
	278
	279	for (i = 0; i < BGA_GPIO_BANKS; i++) {
	280	at91_sys_write(pio_controller_offset[i] + PIO_IDR, wakeups[i]);
281	at91_sys_write(pio_controller_offset[i] + PIO_IER, backups[i]);
282	}
283
284	at91_sys_write(AT91_PMC_PCER,
285	(1 << AT91_ID_PIOA)
286	\| (1 << AT91_ID_PIOB)
287	\| (1 << AT91_ID_PIOC)
288	\| (1 << AT91_ID_PIOD));
289	}
290
291	#else
292	#define gpio_irq_set_wake NULL
293	#endif
294
73a59c1c SP	295
	296	/* Several AIC controller irqs are dispatched through this GPIO handler.
	297	* To use any AT91_PIN_* as an externally triggered IRQ, first call
	298	* at91_set_gpio_input() then maybe enable its glitch filter.
	299	* Then just request_irq() with the pin ID; it works like any ARM IRQ
	300	* handler, though it always triggers on rising and falling edges.
	301	*
	302	* Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
	303	* configuring them with at91_set_a_periph() or at91_set_b_periph().
	304	* IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering.
	305	*/
	306
	307	static void gpio_irq_mask(unsigned pin)
	308	{
	309	void __iomem *pio = pin_to_controller(pin);
	310	unsigned mask = pin_to_mask(pin);
	311
	312	if (pio)
	313	__raw_writel(mask, pio + PIO_IDR);
	314	}
	315
	316	static void gpio_irq_unmask(unsigned pin)
	317	{
	318	void __iomem *pio = pin_to_controller(pin);
	319	unsigned mask = pin_to_mask(pin);
	320
	321	if (pio)
	322	__raw_writel(mask, pio + PIO_IER);
	323	}
	324
	325	static int gpio_irq_type(unsigned pin, unsigned type)
	326	{
	327	return (type == IRQT_BOTHEDGE) ? 0 : -EINVAL;
	328	}
	329
38c677cb DB	330	static struct irq_chip gpio_irqchip = {
38c677cb DB	331	.name = "GPIO",
73a59c1c SP	332	.mask = gpio_irq_mask,
	333	.unmask = gpio_irq_unmask,
	334	.set_type = gpio_irq_type,
814138ff	335	.set_wake = gpio_irq_set_wake,
73a59c1c SP	336	};
	337
	338	static void gpio_irq_handler(unsigned irq, struct irqdesc desc, struct pt_regs regs)
	339	{
	340	unsigned pin;
	341	struct irqdesc *gpio;
	342	void __iomem *pio;
	343	u32 isr;
	344
07d265dd	345	pio = get_irq_chip_data(irq);
73a59c1c SP	346
	347	/* temporarily mask (level sensitive) parent IRQ */
	348	desc->chip->ack(irq);
	349	for (;;) {
814138ff	350	/* reading ISR acks the pending (edge triggered) GPIO interrupt */
73a59c1c SP	351	isr = __raw_readl(pio + PIO_ISR) & __raw_readl(pio + PIO_IMR);
	352	if (!isr)
	353	break;
	354
07d265dd	355	pin = (unsigned) get_irq_data(irq);
73a59c1c SP	356	gpio = &irq_desc[pin];
	357
	358	while (isr) {
abbea718	359	if (isr & 1) {
07d265dd	360	if (unlikely(gpio->depth)) {
abbea718 AV	361	/*
	362	* The core ARM interrupt handler lazily disables IRQs so
	363	* another IRQ must be generated before it actually gets
	364	* here to be disabled on the GPIO controller.
	365	*/
	366	gpio_irq_mask(pin);
	367	}
	368	else
07d265dd	369	desc_handle_irq(pin, gpio, regs);
abbea718	370	}
73a59c1c SP	371	pin++;
	372	gpio++;
	373	isr >>= 1;
	374	}
	375	}
	376	desc->chip->unmask(irq);
	377	/* now it may re-trigger */
	378	}
	379
	380	/* call this from board-specific init_irq */
	381	void __init at91_gpio_irq_setup(unsigned banks)
	382	{
	383	unsigned pioc, pin, id;
	384
	385	if (banks > 4)
	386	banks = 4;
	387	for (pioc = 0, pin = PIN_BASE, id = AT91_ID_PIOA;
	388	pioc < banks;
	389	pioc++, id++) {
	390	void __iomem *controller;
	391	unsigned i;
	392
	393	controller = (void __iomem *) AT91_VA_BASE_SYS + pio_controller_offset[pioc];
	394	__raw_writel(~0, controller + PIO_IDR);
	395
	396	set_irq_data(id, (void *) pin);
54815366	397	set_irq_chipdata(id, controller);
73a59c1c SP	398
73a59c1c SP	399	for (i = 0; i < 32; i++, pin++) {
814138ff AV	400	/*
	401	* Can use the "simple" and not "edge" handler since it's
	402	* shorter, and the AIC handles interupts sanely.
	403	*/
73a59c1c SP	404	set_irq_chip(pin, &gpio_irqchip);
	405	set_irq_handler(pin, do_simple_IRQ);
	406	set_irq_flags(pin, IRQF_VALID);
	407	}
	408
	409	set_irq_chained_handler(id, gpio_irq_handler);
73a59c1c SP	410	}
	411	pr_info("AT91: %d gpio irqs in %d banks\n", pin - PIN_BASE, banks);
	412	}