[deliverable/linux.git] / arch / arm / mach-bcm / platsmp.c

/*
 * Copyright (C) 2014-2015 Broadcom Corporation
 * Copyright 2014 Linaro Limited
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation version 2.
 *
 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 * kind, whether express or implied; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/cpumask.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/jiffies.h>
#include <linux/of.h>
#include <linux/sched.h>
#include <linux/smp.h>

#include <asm/cacheflush.h>
#include <asm/smp.h>
#include <asm/smp_plat.h>
#include <asm/smp_scu.h>

/* Size of mapped Cortex A9 SCU address space */
#define CORTEX_A9_SCU_SIZE	0x58

#define SECONDARY_TIMEOUT_NS	NSEC_PER_MSEC	/* 1 msec (in nanoseconds) */
#define BOOT_ADDR_CPUID_MASK	0x3

/* Name of device node property defining secondary boot register location */
#define OF_SECONDARY_BOOT	"secondary-boot-reg"
#define MPIDR_CPUID_BITMASK	0x3

/*
 * Enable the Cortex A9 Snoop Control Unit
 *
 * By the time this is called we already know there are multiple
 * cores present.  We assume we're running on a Cortex A9 processor,
 * so any trouble getting the base address register or getting the
 * SCU base is a problem.
 *
 * Return 0 if successful or an error code otherwise.
 */
static int __init scu_a9_enable(void)
{
	unsigned long config_base;
	void __iomem *scu_base;

	if (!scu_a9_has_base()) {
		pr_err("no configuration base address register!\n");
		return -ENXIO;
	}

	/* Config base address register value is zero for uniprocessor */
	config_base = scu_a9_get_base();
	if (!config_base) {
		pr_err("hardware reports only one core\n");
		return -ENOENT;
	}

	scu_base = ioremap((phys_addr_t)config_base, CORTEX_A9_SCU_SIZE);
	if (!scu_base) {
		pr_err("failed to remap config base (%lu/%u) for SCU\n",
			config_base, CORTEX_A9_SCU_SIZE);
		return -ENOMEM;
	}

	scu_enable(scu_base);

	iounmap(scu_base);	/* That's the last we'll need of this */

	return 0;
}

static u32 secondary_boot_addr_for(unsigned int cpu)
{
	u32 secondary_boot_addr = 0;
	struct device_node *cpu_node = of_get_cpu_node(cpu, NULL);

        if (!cpu_node) {
		pr_err("Failed to find device tree node for CPU%u\n", cpu);
		return 0;
	}

	if (of_property_read_u32(cpu_node,
				 OF_SECONDARY_BOOT,
				 &secondary_boot_addr))
		pr_err("required secondary boot register not specified for CPU%u\n",
			cpu);

	of_node_put(cpu_node);

	return secondary_boot_addr;
}

static int nsp_write_lut(unsigned int cpu)
{
	void __iomem *sku_rom_lut;
	phys_addr_t secondary_startup_phy;
	const u32 secondary_boot_addr = secondary_boot_addr_for(cpu);

	if (!secondary_boot_addr)
		return -EINVAL;

	sku_rom_lut = ioremap_nocache((phys_addr_t)secondary_boot_addr,
				      sizeof(phys_addr_t));
	if (!sku_rom_lut) {
		pr_warn("unable to ioremap SKU-ROM LUT register for cpu %u\n", cpu);
		return -ENOMEM;
	}

	secondary_startup_phy = virt_to_phys(secondary_startup);
	BUG_ON(secondary_startup_phy > (phys_addr_t)U32_MAX);

	writel_relaxed(secondary_startup_phy, sku_rom_lut);

	/* Ensure the write is visible to the secondary core */
	smp_wmb();

	iounmap(sku_rom_lut);

	return 0;
}

static void __init bcm_smp_prepare_cpus(unsigned int max_cpus)
{
	const cpumask_t only_cpu_0 = { CPU_BITS_CPU0 };

	/* Enable the SCU on Cortex A9 based SoCs */
	if (scu_a9_enable()) {
		/* Update the CPU present map to reflect uniprocessor mode */
		pr_warn("failed to enable A9 SCU - disabling SMP\n");
		init_cpu_present(&only_cpu_0);
	}
}

/*
 * The ROM code has the secondary cores looping, waiting for an event.
 * When an event occurs each core examines the bottom two bits of the
 * secondary boot register.  When a core finds those bits contain its
 * own core id, it performs initialization, including computing its boot
 * address by clearing the boot register value's bottom two bits.  The
 * core signals that it is beginning its execution by writing its boot
 * address back to the secondary boot register, and finally jumps to
 * that address.
 *
 * So to start a core executing we need to:
 * - Encode the (hardware) CPU id with the bottom bits of the secondary
 *   start address.
 * - Write that value into the secondary boot register.
 * - Generate an event to wake up the secondary CPU(s).
 * - Wait for the secondary boot register to be re-written, which
 *   indicates the secondary core has started.
 */
static int kona_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
	void __iomem *boot_reg;
	phys_addr_t boot_func;
	u64 start_clock;
	u32 cpu_id;
	u32 boot_val;
	bool timeout = false;
	const u32 secondary_boot_addr = secondary_boot_addr_for(cpu);

	cpu_id = cpu_logical_map(cpu);
	if (cpu_id & ~BOOT_ADDR_CPUID_MASK) {
		pr_err("bad cpu id (%u > %u)\n", cpu_id, BOOT_ADDR_CPUID_MASK);
		return -EINVAL;
	}

	if (!secondary_boot_addr)
		return -EINVAL;

	boot_reg = ioremap_nocache((phys_addr_t)secondary_boot_addr,
				   sizeof(phys_addr_t));
	if (!boot_reg) {
		pr_err("unable to map boot register for cpu %u\n", cpu_id);
		return -ENOMEM;
	}

	/*
	 * Secondary cores will start in secondary_startup(),
	 * defined in "arch/arm/kernel/head.S"
	 */
	boot_func = virt_to_phys(secondary_startup);
	BUG_ON(boot_func & BOOT_ADDR_CPUID_MASK);
	BUG_ON(boot_func > (phys_addr_t)U32_MAX);

	/* The core to start is encoded in the low bits */
	boot_val = (u32)boot_func | cpu_id;
	writel_relaxed(boot_val, boot_reg);

	sev();

	/* The low bits will be cleared once the core has started */
	start_clock = local_clock();
	while (!timeout && readl_relaxed(boot_reg) == boot_val)
		timeout = local_clock() - start_clock > SECONDARY_TIMEOUT_NS;

	iounmap(boot_reg);

	if (!timeout)
		return 0;

	pr_err("timeout waiting for cpu %u to start\n", cpu_id);

	return -ENXIO;
}

static int nsp_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
	int ret;

	/*
	 * After wake up, secondary core branches to the startup
	 * address programmed at SKU ROM LUT location.
	 */
	ret = nsp_write_lut(cpu);
	if (ret) {
		pr_err("unable to write startup addr to SKU ROM LUT\n");
		goto out;
	}

	/* Send a CPU wakeup interrupt to the secondary core */
	arch_send_wakeup_ipi_mask(cpumask_of(cpu));

out:
	return ret;
}

static const struct smp_operations kona_smp_ops __initconst = {
	.smp_prepare_cpus	= bcm_smp_prepare_cpus,
	.smp_boot_secondary	= kona_boot_secondary,
};
CPU_METHOD_OF_DECLARE(bcm_smp_bcm281xx, "brcm,bcm11351-cpu-method",
			&kona_smp_ops);

static const struct smp_operations nsp_smp_ops __initconst = {
	.smp_prepare_cpus	= bcm_smp_prepare_cpus,
	.smp_boot_secondary	= nsp_boot_secondary,
};
CPU_METHOD_OF_DECLARE(bcm_smp_nsp, "brcm,bcm-nsp-smp", &nsp_smp_ops);
Commit	Line	Data
9a5a110e	1	/*
84320e1a	2	* Copyright (C) 2014-2015 Broadcom Corporation
9a5a110e AE	3	* Copyright 2014 Linaro Limited
	4	*
	5	* This program is free software; you can redistribute it and/or
	6	* modify it under the terms of the GNU General Public License as
	7	* published by the Free Software Foundation version 2.
	8	*
	9	* This program is distributed "as is" WITHOUT ANY WARRANTY of any
	10	* kind, whether express or implied; without even the implied warranty
	11	* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*/
	14
97890821 KH	15	#include <linux/cpumask.h>
97890821 KH	16	#include <linux/delay.h>
9a5a110e	17	#include <linux/errno.h>
97890821	18	#include <linux/init.h>
9a5a110e	19	#include <linux/io.h>
97890821	20	#include <linux/jiffies.h>
9a5a110e AE	21	#include <linux/of.h>
9a5a110e AE	22	#include <linux/sched.h>
97890821	23	#include <linux/smp.h>
9a5a110e	24
97890821	25	#include <asm/cacheflush.h>
9a5a110e AE	26	#include <asm/smp.h>
	27	#include <asm/smp_plat.h>
	28	#include <asm/smp_scu.h>
	29
	30	/* Size of mapped Cortex A9 SCU address space */
	31	#define CORTEX_A9_SCU_SIZE 0x58
	32
	33	#define SECONDARY_TIMEOUT_NS NSEC_PER_MSEC /* 1 msec (in nanoseconds) */
	34	#define BOOT_ADDR_CPUID_MASK 0x3
	35
	36	/* Name of device node property defining secondary boot register location */
	37	#define OF_SECONDARY_BOOT "secondary-boot-reg"
84320e1a	38	#define MPIDR_CPUID_BITMASK 0x3
9a5a110e	39
9a5a110e AE	40	/*
	41	* Enable the Cortex A9 Snoop Control Unit
	42	*
	43	* By the time this is called we already know there are multiple
	44	* cores present. We assume we're running on a Cortex A9 processor,
	45	* so any trouble getting the base address register or getting the
	46	* SCU base is a problem.
	47	*
	48	* Return 0 if successful or an error code otherwise.
	49	*/
	50	static int __init scu_a9_enable(void)
	51	{
	52	unsigned long config_base;
	53	void __iomem *scu_base;
	54
	55	if (!scu_a9_has_base()) {
	56	pr_err("no configuration base address register!\n");
	57	return -ENXIO;
	58	}
	59
	60	/* Config base address register value is zero for uniprocessor */
	61	config_base = scu_a9_get_base();
	62	if (!config_base) {
	63	pr_err("hardware reports only one core\n");
	64	return -ENOENT;
	65	}
	66
	67	scu_base = ioremap((phys_addr_t)config_base, CORTEX_A9_SCU_SIZE);
	68	if (!scu_base) {
	69	pr_err("failed to remap config base (%lu/%u) for SCU\n",
	70	config_base, CORTEX_A9_SCU_SIZE);
	71	return -ENOMEM;
	72	}
	73
	74	scu_enable(scu_base);
	75
	76	iounmap(scu_base); /* That's the last we'll need of this */
	77
	78	return 0;
	79	}
	80
6585cb5a CB	81	static u32 secondary_boot_addr_for(unsigned int cpu)
	82	{
	83	u32 secondary_boot_addr = 0;
	84	struct device_node *cpu_node = of_get_cpu_node(cpu, NULL);
	85
	86	if (!cpu_node) {
	87	pr_err("Failed to find device tree node for CPU%u\n", cpu);
	88	return 0;
	89	}
	90
	91	if (of_property_read_u32(cpu_node,
	92	OF_SECONDARY_BOOT,
	93	&secondary_boot_addr))
	94	pr_err("required secondary boot register not specified for CPU%u\n",
	95	cpu);
	96
	97	of_node_put(cpu_node);
	98
	99	return secondary_boot_addr;
	100	}
	101
	102	static int nsp_write_lut(unsigned int cpu)
97890821 KH	103	{
	104	void __iomem *sku_rom_lut;
	105	phys_addr_t secondary_startup_phy;
6585cb5a	106	const u32 secondary_boot_addr = secondary_boot_addr_for(cpu);
97890821	107
6585cb5a	108	if (!secondary_boot_addr)
97890821	109	return -EINVAL;
97890821 KH	110
97890821 KH	111	sku_rom_lut = ioremap_nocache((phys_addr_t)secondary_boot_addr,
6585cb5a	112	sizeof(phys_addr_t));
97890821	113	if (!sku_rom_lut) {
6585cb5a	114	pr_warn("unable to ioremap SKU-ROM LUT register for cpu %u\n", cpu);
97890821 KH	115	return -ENOMEM;
	116	}
	117
	118	secondary_startup_phy = virt_to_phys(secondary_startup);
	119	BUG_ON(secondary_startup_phy > (phys_addr_t)U32_MAX);
	120
	121	writel_relaxed(secondary_startup_phy, sku_rom_lut);
	122
	123	/* Ensure the write is visible to the secondary core */
	124	smp_wmb();
	125
	126	iounmap(sku_rom_lut);
	127
	128	return 0;
	129	}
	130
9a5a110e AE	131	static void __init bcm_smp_prepare_cpus(unsigned int max_cpus)
9a5a110e AE	132	{
6585cb5a	133	const cpumask_t only_cpu_0 = { CPU_BITS_CPU0 };
84320e1a	134
6585cb5a CB	135	/* Enable the SCU on Cortex A9 based SoCs */
6585cb5a CB	136	if (scu_a9_enable()) {
9a5a110e	137	/* Update the CPU present map to reflect uniprocessor mode */
6585cb5a	138	pr_warn("failed to enable A9 SCU - disabling SMP\n");
9a5a110e AE	139	init_cpu_present(&only_cpu_0);
	140	}
	141	}
	142
	143	/*
	144	* The ROM code has the secondary cores looping, waiting for an event.
	145	* When an event occurs each core examines the bottom two bits of the
	146	* secondary boot register. When a core finds those bits contain its
	147	* own core id, it performs initialization, including computing its boot
	148	* address by clearing the boot register value's bottom two bits. The
	149	* core signals that it is beginning its execution by writing its boot
	150	* address back to the secondary boot register, and finally jumps to
	151	* that address.
	152	*
	153	* So to start a core executing we need to:
	154	* - Encode the (hardware) CPU id with the bottom bits of the secondary
	155	* start address.
	156	* - Write that value into the secondary boot register.
	157	* - Generate an event to wake up the secondary CPU(s).
	158	* - Wait for the secondary boot register to be re-written, which
	159	* indicates the secondary core has started.
	160	*/
84320e1a	161	static int kona_boot_secondary(unsigned int cpu, struct task_struct *idle)
9a5a110e AE	162	{
	163	void __iomem *boot_reg;
	164	phys_addr_t boot_func;
	165	u64 start_clock;
	166	u32 cpu_id;
	167	u32 boot_val;
	168	bool timeout = false;
6585cb5a	169	const u32 secondary_boot_addr = secondary_boot_addr_for(cpu);
9a5a110e AE	170
	171	cpu_id = cpu_logical_map(cpu);
	172	if (cpu_id & ~BOOT_ADDR_CPUID_MASK) {
	173	pr_err("bad cpu id (%u > %u)\n", cpu_id, BOOT_ADDR_CPUID_MASK);
	174	return -EINVAL;
	175	}
	176
6585cb5a	177	if (!secondary_boot_addr)
9a5a110e	178	return -EINVAL;
9a5a110e	179
6585cb5a CB	180	boot_reg = ioremap_nocache((phys_addr_t)secondary_boot_addr,
6585cb5a CB	181	sizeof(phys_addr_t));
9a5a110e AE	182	if (!boot_reg) {
9a5a110e AE	183	pr_err("unable to map boot register for cpu %u\n", cpu_id);
84320e1a	184	return -ENOMEM;
9a5a110e AE	185	}
	186
	187	/*
	188	* Secondary cores will start in secondary_startup(),
	189	* defined in "arch/arm/kernel/head.S"
	190	*/
	191	boot_func = virt_to_phys(secondary_startup);
	192	BUG_ON(boot_func & BOOT_ADDR_CPUID_MASK);
	193	BUG_ON(boot_func > (phys_addr_t)U32_MAX);
	194
	195	/* The core to start is encoded in the low bits */
	196	boot_val = (u32)boot_func \| cpu_id;
	197	writel_relaxed(boot_val, boot_reg);
	198
	199	sev();
	200
	201	/* The low bits will be cleared once the core has started */
	202	start_clock = local_clock();
	203	while (!timeout && readl_relaxed(boot_reg) == boot_val)
	204	timeout = local_clock() - start_clock > SECONDARY_TIMEOUT_NS;
	205
	206	iounmap(boot_reg);
	207
	208	if (!timeout)
	209	return 0;
	210
	211	pr_err("timeout waiting for cpu %u to start\n", cpu_id);
	212
84320e1a	213	return -ENXIO;
9a5a110e AE	214	}
9a5a110e AE	215
97890821 KH	216	static int nsp_boot_secondary(unsigned int cpu, struct task_struct *idle)
	217	{
	218	int ret;
	219
	220	/*
	221	* After wake up, secondary core branches to the startup
	222	* address programmed at SKU ROM LUT location.
	223	*/
6585cb5a	224	ret = nsp_write_lut(cpu);
97890821 KH	225	if (ret) {
	226	pr_err("unable to write startup addr to SKU ROM LUT\n");
	227	goto out;
	228	}
	229
	230	/* Send a CPU wakeup interrupt to the secondary core */
	231	arch_send_wakeup_ipi_mask(cpumask_of(cpu));
	232
	233	out:
	234	return ret;
	235	}
	236
6585cb5a	237	static const struct smp_operations kona_smp_ops __initconst = {
9a5a110e	238	.smp_prepare_cpus = bcm_smp_prepare_cpus,
84320e1a	239	.smp_boot_secondary = kona_boot_secondary,
9a5a110e AE	240	};
9a5a110e AE	241	CPU_METHOD_OF_DECLARE(bcm_smp_bcm281xx, "brcm,bcm11351-cpu-method",
6585cb5a	242	&kona_smp_ops);
97890821	243
9480e085	244	static const struct smp_operations nsp_smp_ops __initconst = {
97890821 KH	245	.smp_prepare_cpus = bcm_smp_prepare_cpus,
	246	.smp_boot_secondary = nsp_boot_secondary,
	247	};
	248	CPU_METHOD_OF_DECLARE(bcm_smp_nsp, "brcm,bcm-nsp-smp", &nsp_smp_ops);