ARM: clps711x: Set PLL clock to zero if we work from 13 mHz source
[deliverable/linux.git] / arch / arm / mach-clps711x / board-autcpu12.c
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1da177e4
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1/*
2 * linux/arch/arm/mach-clps711x/autcpu12.c
3 *
4 * (c) 2001 Thomas Gleixner, autronix automation <gleixner@autronix.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#include <linux/kernel.h>
21#include <linux/init.h>
22#include <linux/types.h>
23#include <linux/string.h>
24#include <linux/mm.h>
fced80c7 25#include <linux/io.h>
90383e0a 26#include <linux/gpio.h>
ce55754c 27#include <linux/ioport.h>
200daa36 28#include <linux/interrupt.h>
90383e0a
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29#include <linux/mtd/partitions.h>
30#include <linux/mtd/nand-gpio.h>
ce55754c 31#include <linux/platform_device.h>
90383e0a 32#include <linux/basic_mmio_gpio.h>
1da177e4 33
a09e64fb 34#include <mach/hardware.h>
1da177e4 35#include <asm/sizes.h>
1da177e4
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36#include <asm/setup.h>
37#include <asm/mach-types.h>
38#include <asm/mach/arch.h>
39#include <asm/pgtable.h>
40#include <asm/page.h>
41
42#include <asm/mach/map.h>
a09e64fb 43#include <mach/autcpu12.h>
1da177e4
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44
45#include "common.h"
e328b880 46#include "devices.h"
1da177e4 47
200daa36
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48#define AUTCPU12_CS8900_BASE (CS2_PHYS_BASE + 0x300)
49#define AUTCPU12_CS8900_IRQ (IRQ_EINT3)
1da177e4 50
90383e0a
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51#define AUTCPU12_SMC_BASE (CS1_PHYS_BASE + 0x06000000)
52#define AUTCPU12_SMC_SEL_BASE (AUTCPU12_SMC_BASE + 0x10)
53
54#define AUTCPU12_MMGPIO_BASE (CLPS711X_NR_GPIO)
55#define AUTCPU12_SMC_NCE (AUTCPU12_MMGPIO_BASE + 0) /* Bit 0 */
56#define AUTCPU12_SMC_RDY CLPS711X_GPIO(1, 2)
57#define AUTCPU12_SMC_ALE CLPS711X_GPIO(1, 3)
58#define AUTCPU12_SMC_CLE CLPS711X_GPIO(1, 3)
59
200daa36
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60static struct resource autcpu12_cs8900_resource[] __initdata = {
61 DEFINE_RES_MEM(AUTCPU12_CS8900_BASE, SZ_1K),
62 DEFINE_RES_IRQ(AUTCPU12_CS8900_IRQ),
63};
1da177e4 64
ce55754c
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65static struct resource autcpu12_nvram_resource[] __initdata = {
66 DEFINE_RES_MEM_NAMED(AUTCPU12_PHYS_NVRAM, SZ_128K, "SRAM"),
67};
68
69static struct platform_device autcpu12_nvram_pdev __initdata = {
70 .name = "autcpu12_nvram",
71 .id = -1,
72 .resource = autcpu12_nvram_resource,
73 .num_resources = ARRAY_SIZE(autcpu12_nvram_resource),
74};
75
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76static struct resource autcpu12_nand_resource[] __initdata = {
77 DEFINE_RES_MEM(AUTCPU12_SMC_BASE, SZ_16),
78};
79
80static struct mtd_partition autcpu12_nand_parts[] __initdata = {
81 {
82 .name = "Flash partition 1",
83 .offset = 0,
84 .size = SZ_8M,
85 },
86 {
87 .name = "Flash partition 2",
88 .offset = MTDPART_OFS_APPEND,
89 .size = MTDPART_SIZ_FULL,
90 },
91};
92
93static void __init autcpu12_adjust_parts(struct gpio_nand_platdata *pdata,
94 size_t sz)
95{
96 switch (sz) {
97 case SZ_16M:
98 case SZ_32M:
99 break;
100 case SZ_64M:
101 case SZ_128M:
102 pdata->parts[0].size = SZ_16M;
103 break;
104 default:
105 pr_warn("Unsupported SmartMedia device size %u\n", sz);
106 break;
107 }
108}
109
110static struct gpio_nand_platdata autcpu12_nand_pdata __initdata = {
111 .gpio_rdy = AUTCPU12_SMC_RDY,
112 .gpio_nce = AUTCPU12_SMC_NCE,
113 .gpio_ale = AUTCPU12_SMC_ALE,
114 .gpio_cle = AUTCPU12_SMC_CLE,
115 .gpio_nwp = -1,
116 .chip_delay = 20,
117 .parts = autcpu12_nand_parts,
118 .num_parts = ARRAY_SIZE(autcpu12_nand_parts),
119 .adjust_parts = autcpu12_adjust_parts,
120};
121
122static struct platform_device autcpu12_nand_pdev __initdata = {
123 .name = "gpio-nand",
124 .id = -1,
125 .resource = autcpu12_nand_resource,
126 .num_resources = ARRAY_SIZE(autcpu12_nand_resource),
127 .dev = {
128 .platform_data = &autcpu12_nand_pdata,
129 },
130};
131
132static struct resource autcpu12_mmgpio_resource[] __initdata = {
133 DEFINE_RES_MEM_NAMED(AUTCPU12_SMC_SEL_BASE, SZ_1, "dat"),
134};
135
136static struct bgpio_pdata autcpu12_mmgpio_pdata __initdata = {
137 .base = AUTCPU12_MMGPIO_BASE,
138 .ngpio = 8,
139};
140
141static struct platform_device autcpu12_mmgpio_pdev __initdata = {
142 .name = "basic-mmio-gpio",
143 .id = -1,
144 .resource = autcpu12_mmgpio_resource,
145 .num_resources = ARRAY_SIZE(autcpu12_mmgpio_resource),
146 .dev = {
147 .platform_data = &autcpu12_mmgpio_pdata,
148 },
149};
150
ce55754c
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151static void __init autcpu12_init(void)
152{
e328b880 153 clps711x_devices_init();
dd850f12 154 platform_device_register_simple("video-clps711x", 0, NULL, 0);
200daa36
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155 platform_device_register_simple("cs89x0", 0, autcpu12_cs8900_resource,
156 ARRAY_SIZE(autcpu12_cs8900_resource));
90383e0a 157 platform_device_register(&autcpu12_mmgpio_pdev);
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158 platform_device_register(&autcpu12_nvram_pdev);
159}
160
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161static void __init autcpu12_init_late(void)
162{
163 if (IS_ENABLED(MTD_NAND_GPIO) && IS_ENABLED(GPIO_GENERIC_PLATFORM)) {
164 /* We are need both drivers to handle NAND */
165 platform_device_register(&autcpu12_nand_pdev);
166 }
167}
168
1da177e4 169MACHINE_START(AUTCPU12, "autronix autcpu12")
e9dea0c6 170 /* Maintainer: Thomas Gleixner */
6244fa9c 171 .atag_offset = 0x20000,
0d8be81c 172 .nr_irqs = CLPS711X_NR_IRQS,
200daa36 173 .map_io = clps711x_map_io,
e9dea0c6 174 .init_irq = clps711x_init_irq,
6bb27d73 175 .init_time = clps711x_timer_init,
200daa36 176 .init_machine = autcpu12_init,
90383e0a 177 .init_late = autcpu12_init_late,
99f04c8f 178 .handle_irq = clps711x_handle_irq,
6c000712 179 .restart = clps711x_restart,
1da177e4
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180MACHINE_END
181
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