Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
3a083227 | 2 | * linux/arch/arm/mach-clps711x/core.c |
1da177e4 | 3 | * |
3a083227 RK |
4 | * Core support for the CLPS711x-based machines. |
5 | * | |
6 | * Copyright (C) 2001,2011 Deep Blue Solutions Ltd | |
1da177e4 LT |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | */ | |
61ae48c3 | 22 | #include <linux/io.h> |
1da177e4 | 23 | #include <linux/init.h> |
4a8355c4 | 24 | #include <linux/sizes.h> |
3a083227 | 25 | #include <linux/interrupt.h> |
3a083227 | 26 | #include <linux/irq.h> |
61ae48c3 AS |
27 | #include <linux/clk.h> |
28 | #include <linux/clkdev.h> | |
4a8355c4 | 29 | #include <linux/clockchips.h> |
c99f72ad | 30 | #include <linux/clocksource.h> |
61ae48c3 | 31 | #include <linux/clk-provider.h> |
5bd8e16d | 32 | #include <linux/sched_clock.h> |
1da177e4 | 33 | |
99f04c8f | 34 | #include <asm/exception.h> |
19792610 | 35 | #include <asm/mach/irq.h> |
3a083227 RK |
36 | #include <asm/mach/map.h> |
37 | #include <asm/mach/time.h> | |
9f97da78 | 38 | #include <asm/system_misc.h> |
1da177e4 | 39 | |
61ae48c3 AS |
40 | #include <mach/hardware.h> |
41 | ||
42 | static struct clk *clk_pll, *clk_bus, *clk_uart, *clk_timerl, *clk_timerh, | |
43 | *clk_tint, *clk_spi; | |
61ae48c3 | 44 | |
3a083227 RK |
45 | /* |
46 | * This maps the generic CLPS711x registers | |
47 | */ | |
48 | static struct map_desc clps711x_io_desc[] __initdata = { | |
49 | { | |
304b2c68 AS |
50 | .virtual = (unsigned long)CLPS711X_VIRT_BASE, |
51 | .pfn = __phys_to_pfn(CLPS711X_PHYS_BASE), | |
6cb1b145 | 52 | .length = SZ_64K, |
3a083227 RK |
53 | .type = MT_DEVICE |
54 | } | |
55 | }; | |
56 | ||
57 | void __init clps711x_map_io(void) | |
58 | { | |
59 | iotable_init(clps711x_io_desc, ARRAY_SIZE(clps711x_io_desc)); | |
60 | } | |
61 | ||
8ad357ca | 62 | static void int1_mask(struct irq_data *d) |
1da177e4 LT |
63 | { |
64 | u32 intmr1; | |
65 | ||
66 | intmr1 = clps_readl(INTMR1); | |
8ad357ca | 67 | intmr1 &= ~(1 << d->irq); |
1da177e4 LT |
68 | clps_writel(intmr1, INTMR1); |
69 | } | |
70 | ||
74fde6de | 71 | static void int1_eoi(struct irq_data *d) |
1da177e4 | 72 | { |
8ad357ca | 73 | switch (d->irq) { |
1da177e4 LT |
74 | case IRQ_CSINT: clps_writel(0, COEOI); break; |
75 | case IRQ_TC1OI: clps_writel(0, TC1EOI); break; | |
76 | case IRQ_TC2OI: clps_writel(0, TC2EOI); break; | |
77 | case IRQ_RTCMI: clps_writel(0, RTCEOI); break; | |
78 | case IRQ_TINT: clps_writel(0, TEOI); break; | |
79 | case IRQ_UMSINT: clps_writel(0, UMSEOI); break; | |
80 | } | |
81 | } | |
82 | ||
8ad357ca | 83 | static void int1_unmask(struct irq_data *d) |
1da177e4 LT |
84 | { |
85 | u32 intmr1; | |
86 | ||
87 | intmr1 = clps_readl(INTMR1); | |
8ad357ca | 88 | intmr1 |= 1 << d->irq; |
1da177e4 LT |
89 | clps_writel(intmr1, INTMR1); |
90 | } | |
91 | ||
10dd5ce2 | 92 | static struct irq_chip int1_chip = { |
19792610 | 93 | .name = "Interrupt Vector 1", |
74fde6de | 94 | .irq_eoi = int1_eoi, |
8ad357ca LB |
95 | .irq_mask = int1_mask, |
96 | .irq_unmask = int1_unmask, | |
1da177e4 LT |
97 | }; |
98 | ||
8ad357ca | 99 | static void int2_mask(struct irq_data *d) |
1da177e4 LT |
100 | { |
101 | u32 intmr2; | |
102 | ||
103 | intmr2 = clps_readl(INTMR2); | |
8ad357ca | 104 | intmr2 &= ~(1 << (d->irq - 16)); |
1da177e4 LT |
105 | clps_writel(intmr2, INTMR2); |
106 | } | |
107 | ||
74fde6de | 108 | static void int2_eoi(struct irq_data *d) |
1da177e4 | 109 | { |
8ad357ca | 110 | switch (d->irq) { |
1da177e4 LT |
111 | case IRQ_KBDINT: clps_writel(0, KBDEOI); break; |
112 | } | |
113 | } | |
114 | ||
8ad357ca | 115 | static void int2_unmask(struct irq_data *d) |
1da177e4 LT |
116 | { |
117 | u32 intmr2; | |
118 | ||
119 | intmr2 = clps_readl(INTMR2); | |
8ad357ca | 120 | intmr2 |= 1 << (d->irq - 16); |
1da177e4 LT |
121 | clps_writel(intmr2, INTMR2); |
122 | } | |
123 | ||
10dd5ce2 | 124 | static struct irq_chip int2_chip = { |
19792610 | 125 | .name = "Interrupt Vector 2", |
74fde6de | 126 | .irq_eoi = int2_eoi, |
8ad357ca LB |
127 | .irq_mask = int2_mask, |
128 | .irq_unmask = int2_unmask, | |
1da177e4 LT |
129 | }; |
130 | ||
19792610 AS |
131 | static void int3_mask(struct irq_data *d) |
132 | { | |
133 | u32 intmr3; | |
134 | ||
135 | intmr3 = clps_readl(INTMR3); | |
136 | intmr3 &= ~(1 << (d->irq - 32)); | |
137 | clps_writel(intmr3, INTMR3); | |
138 | } | |
139 | ||
140 | static void int3_unmask(struct irq_data *d) | |
141 | { | |
142 | u32 intmr3; | |
143 | ||
144 | intmr3 = clps_readl(INTMR3); | |
145 | intmr3 |= 1 << (d->irq - 32); | |
146 | clps_writel(intmr3, INTMR3); | |
147 | } | |
148 | ||
149 | static struct irq_chip int3_chip = { | |
150 | .name = "Interrupt Vector 3", | |
151 | .irq_mask = int3_mask, | |
152 | .irq_unmask = int3_unmask, | |
153 | }; | |
154 | ||
99f04c8f | 155 | static struct { |
74fde6de AS |
156 | int nr; |
157 | struct irq_chip *chip; | |
158 | irq_flow_handler_t handle; | |
99f04c8f | 159 | } clps711x_irqdescs[] __initdata = { |
74fde6de AS |
160 | { IRQ_CSINT, &int1_chip, handle_fasteoi_irq, }, |
161 | { IRQ_EINT1, &int1_chip, handle_level_irq, }, | |
162 | { IRQ_EINT2, &int1_chip, handle_level_irq, }, | |
163 | { IRQ_EINT3, &int1_chip, handle_level_irq, }, | |
164 | { IRQ_TC1OI, &int1_chip, handle_fasteoi_irq, }, | |
165 | { IRQ_TC2OI, &int1_chip, handle_fasteoi_irq, }, | |
166 | { IRQ_RTCMI, &int1_chip, handle_fasteoi_irq, }, | |
167 | { IRQ_TINT, &int1_chip, handle_fasteoi_irq, }, | |
168 | { IRQ_UTXINT1, &int1_chip, handle_level_irq, }, | |
169 | { IRQ_URXINT1, &int1_chip, handle_level_irq, }, | |
170 | { IRQ_UMSINT, &int1_chip, handle_fasteoi_irq, }, | |
171 | { IRQ_SSEOTI, &int1_chip, handle_level_irq, }, | |
172 | { IRQ_KBDINT, &int2_chip, handle_fasteoi_irq, }, | |
173 | { IRQ_SS2RX, &int2_chip, handle_level_irq, }, | |
174 | { IRQ_SS2TX, &int2_chip, handle_level_irq, }, | |
175 | { IRQ_UTXINT2, &int2_chip, handle_level_irq, }, | |
176 | { IRQ_URXINT2, &int2_chip, handle_level_irq, }, | |
177 | }; | |
178 | ||
1da177e4 LT |
179 | void __init clps711x_init_irq(void) |
180 | { | |
181 | unsigned int i; | |
182 | ||
74fde6de | 183 | /* Disable interrupts */ |
1da177e4 LT |
184 | clps_writel(0, INTMR1); |
185 | clps_writel(0, INTMR2); | |
74fde6de | 186 | clps_writel(0, INTMR3); |
1da177e4 | 187 | |
74fde6de AS |
188 | /* Clear down any pending interrupts */ |
189 | clps_writel(0, BLEOI); | |
190 | clps_writel(0, MCEOI); | |
1da177e4 LT |
191 | clps_writel(0, COEOI); |
192 | clps_writel(0, TC1EOI); | |
193 | clps_writel(0, TC2EOI); | |
194 | clps_writel(0, RTCEOI); | |
195 | clps_writel(0, TEOI); | |
196 | clps_writel(0, UMSEOI); | |
1da177e4 | 197 | clps_writel(0, KBDEOI); |
74fde6de AS |
198 | clps_writel(0, SRXEOF); |
199 | clps_writel(0xffffffff, DAISR); | |
200 | ||
201 | for (i = 0; i < ARRAY_SIZE(clps711x_irqdescs); i++) { | |
202 | irq_set_chip_and_handler(clps711x_irqdescs[i].nr, | |
203 | clps711x_irqdescs[i].chip, | |
204 | clps711x_irqdescs[i].handle); | |
205 | set_irq_flags(clps711x_irqdescs[i].nr, | |
206 | IRQF_VALID | IRQF_PROBE); | |
207 | } | |
19792610 AS |
208 | |
209 | if (IS_ENABLED(CONFIG_FIQ)) { | |
210 | init_FIQ(0); | |
211 | irq_set_chip_and_handler(IRQ_DAIINT, &int3_chip, | |
212 | handle_bad_irq); | |
213 | set_irq_flags(IRQ_DAIINT, | |
214 | IRQF_VALID | IRQF_PROBE | IRQF_NOAUTOEN); | |
215 | } | |
1da177e4 | 216 | } |
3a083227 | 217 | |
7dfbf1b6 | 218 | static inline u32 fls16(u32 x) |
99f04c8f AS |
219 | { |
220 | u32 r = 15; | |
221 | ||
222 | if (!(x & 0xff00)) { | |
223 | x <<= 8; | |
224 | r -= 8; | |
225 | } | |
226 | if (!(x & 0xf000)) { | |
227 | x <<= 4; | |
228 | r -= 4; | |
229 | } | |
230 | if (!(x & 0xc000)) { | |
231 | x <<= 2; | |
232 | r -= 2; | |
233 | } | |
234 | if (!(x & 0x8000)) | |
235 | r--; | |
236 | ||
237 | return r; | |
238 | } | |
239 | ||
240 | asmlinkage void __exception_irq_entry clps711x_handle_irq(struct pt_regs *regs) | |
241 | { | |
7dfbf1b6 AS |
242 | do { |
243 | u32 irqstat; | |
244 | void __iomem *base = CLPS711X_VIRT_BASE; | |
245 | ||
246 | irqstat = readw_relaxed(base + INTSR1) & | |
247 | readw_relaxed(base + INTMR1); | |
248 | if (irqstat) | |
249 | handle_IRQ(fls16(irqstat), regs); | |
250 | ||
251 | irqstat = readw_relaxed(base + INTSR2) & | |
252 | readw_relaxed(base + INTMR2); | |
253 | if (irqstat) { | |
254 | handle_IRQ(fls16(irqstat) + 16, regs); | |
255 | continue; | |
256 | } | |
257 | ||
258 | break; | |
259 | } while (1); | |
99f04c8f AS |
260 | } |
261 | ||
161f4089 | 262 | static u64 notrace clps711x_sched_clock_read(void) |
c99f72ad AS |
263 | { |
264 | return ~readw_relaxed(CLPS711X_VIRT_BASE + TC1D); | |
265 | } | |
266 | ||
4a8355c4 AS |
267 | static void clps711x_clockevent_set_mode(enum clock_event_mode mode, |
268 | struct clock_event_device *evt) | |
3a083227 | 269 | { |
c99f72ad AS |
270 | disable_irq(IRQ_TC2OI); |
271 | ||
272 | switch (mode) { | |
273 | case CLOCK_EVT_MODE_PERIODIC: | |
274 | enable_irq(IRQ_TC2OI); | |
275 | break; | |
276 | case CLOCK_EVT_MODE_ONESHOT: | |
277 | /* Not supported */ | |
278 | case CLOCK_EVT_MODE_SHUTDOWN: | |
279 | case CLOCK_EVT_MODE_UNUSED: | |
280 | case CLOCK_EVT_MODE_RESUME: | |
281 | /* Left event sources disabled, no more interrupts appear */ | |
282 | break; | |
283 | } | |
3a083227 RK |
284 | } |
285 | ||
4a8355c4 | 286 | static struct clock_event_device clockevent_clps711x = { |
c99f72ad | 287 | .name = "clps711x-clockevent", |
4a8355c4 AS |
288 | .rating = 300, |
289 | .features = CLOCK_EVT_FEAT_PERIODIC, | |
290 | .set_mode = clps711x_clockevent_set_mode, | |
291 | }; | |
292 | ||
293 | static irqreturn_t clps711x_timer_interrupt(int irq, void *dev_id) | |
3a083227 | 294 | { |
4a8355c4 AS |
295 | clockevent_clps711x.event_handler(&clockevent_clps711x); |
296 | ||
3a083227 RK |
297 | return IRQ_HANDLED; |
298 | } | |
299 | ||
300 | static struct irqaction clps711x_timer_irq = { | |
c99f72ad AS |
301 | .name = "clps711x-timer", |
302 | .flags = IRQF_TIMER | IRQF_IRQPOLL, | |
4a8355c4 | 303 | .handler = clps711x_timer_interrupt, |
3a083227 RK |
304 | }; |
305 | ||
61ae48c3 AS |
306 | static void add_fixed_clk(struct clk *clk, const char *name, int rate) |
307 | { | |
308 | clk = clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate); | |
309 | clk_register_clkdev(clk, name, NULL); | |
310 | } | |
311 | ||
6bb27d73 | 312 | void __init clps711x_timer_init(void) |
3a083227 | 313 | { |
61ae48c3 AS |
314 | int osc, ext, pll, cpu, bus, timl, timh, uart, spi; |
315 | u32 tmp; | |
316 | ||
317 | osc = 3686400; | |
318 | ext = 13000000; | |
319 | ||
320 | tmp = clps_readl(PLLR) >> 24; | |
321 | if (tmp) | |
322 | pll = (osc * tmp) / 2; | |
323 | else | |
324 | pll = 73728000; /* Default value */ | |
325 | ||
326 | tmp = clps_readl(SYSFLG2); | |
327 | if (tmp & SYSFLG2_CKMODE) { | |
328 | cpu = ext; | |
329 | bus = cpu; | |
330 | spi = 135400; | |
2a6f0614 | 331 | pll = 0; |
61ae48c3 AS |
332 | } else { |
333 | cpu = pll; | |
334 | if (cpu >= 36864000) | |
335 | bus = cpu / 2; | |
336 | else | |
337 | bus = 36864000 / 2; | |
338 | spi = cpu / 576; | |
339 | } | |
340 | ||
341 | uart = bus / 10; | |
342 | ||
343 | if (tmp & SYSFLG2_CKMODE) { | |
344 | tmp = clps_readl(SYSCON2); | |
345 | if (tmp & SYSCON2_OSTB) | |
346 | timh = ext / 26; | |
347 | else | |
348 | timh = 541440; | |
349 | } else | |
c99f72ad | 350 | timh = DIV_ROUND_CLOSEST(cpu, 144); |
61ae48c3 | 351 | |
c99f72ad | 352 | timl = DIV_ROUND_CLOSEST(timh, 256); |
61ae48c3 AS |
353 | |
354 | /* All clocks are fixed */ | |
355 | add_fixed_clk(clk_pll, "pll", pll); | |
356 | add_fixed_clk(clk_bus, "bus", bus); | |
357 | add_fixed_clk(clk_uart, "uart", uart); | |
358 | add_fixed_clk(clk_timerl, "timer_lf", timl); | |
359 | add_fixed_clk(clk_timerh, "timer_hf", timh); | |
360 | add_fixed_clk(clk_tint, "tint", 64); | |
361 | add_fixed_clk(clk_spi, "spi", spi); | |
362 | ||
363 | pr_info("CPU frequency set at %i Hz.\n", cpu); | |
364 | ||
c99f72ad AS |
365 | /* Start Timer1 in free running mode (Low frequency) */ |
366 | tmp = clps_readl(SYSCON1) & ~(SYSCON1_TC1S | SYSCON1_TC1M); | |
367 | clps_writel(tmp, SYSCON1); | |
368 | ||
161f4089 | 369 | sched_clock_register(clps711x_sched_clock_read, 16, timl); |
c99f72ad AS |
370 | |
371 | clocksource_mmio_init(CLPS711X_VIRT_BASE + TC1D, | |
372 | "clps711x_clocksource", timl, 300, 16, | |
373 | clocksource_mmio_readw_down); | |
374 | ||
375 | /* Set Timer2 prescaler */ | |
4a8355c4 | 376 | clps_writew(DIV_ROUND_CLOSEST(timh, HZ), TC2D); |
3a083227 | 377 | |
c99f72ad AS |
378 | /* Start Timer2 in prescale mode (High frequency)*/ |
379 | tmp = clps_readl(SYSCON1) | SYSCON1_TC2M | SYSCON1_TC2S; | |
61ae48c3 | 380 | clps_writel(tmp, SYSCON1); |
3a083227 | 381 | |
c99f72ad | 382 | clockevents_config_and_register(&clockevent_clps711x, timh, 0, 0); |
3a083227 RK |
383 | |
384 | setup_irq(IRQ_TC2OI, &clps711x_timer_irq); | |
3a083227 RK |
385 | } |
386 | ||
7b6d864b | 387 | void clps711x_restart(enum reboot_mode mode, const char *cmd) |
6c000712 RK |
388 | { |
389 | soft_restart(0); | |
390 | } | |
71e256c5 NP |
391 | |
392 | static void clps711x_idle(void) | |
393 | { | |
394 | clps_writel(1, HALT); | |
d0ad52a6 AS |
395 | asm("mov r0, r0"); |
396 | asm("mov r0, r0"); | |
71e256c5 NP |
397 | } |
398 | ||
d0ad52a6 | 399 | void __init clps711x_init_early(void) |
71e256c5 NP |
400 | { |
401 | arm_pm_idle = clps711x_idle; | |
71e256c5 | 402 | } |