ARM: cns3xxx: Add support for SDHCI controllers
[deliverable/linux.git] / arch / arm / mach-cns3xxx / cns3420vb.c
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1/*
2 * Cavium Networks CNS3420 Validation Board
3 *
4 * Copyright 2000 Deep Blue Solutions Ltd
5 * Copyright 2008 ARM Limited
6 * Copyright 2008 Cavium Networks
7 * Scott Shu
8 * Copyright 2010 MontaVista Software, LLC.
9 * Anton Vorontsov <avorontsov@mvista.com>
10 *
11 * This file is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License, Version 2, as
13 * published by the Free Software Foundation.
14 */
15
16#include <linux/init.h>
17#include <linux/kernel.h>
18#include <linux/compiler.h>
19#include <linux/io.h>
20#include <linux/serial_core.h>
21#include <linux/serial_8250.h>
22#include <linux/platform_device.h>
23#include <linux/mtd/mtd.h>
24#include <linux/mtd/physmap.h>
25#include <linux/mtd/partitions.h>
26#include <asm/setup.h>
27#include <asm/mach-types.h>
28#include <asm/mach/arch.h>
29#include <asm/mach/map.h>
30#include <asm/mach/time.h>
31#include <mach/hardware.h>
32#include <mach/cns3xxx.h>
33#include <mach/irqs.h>
34#include "core.h"
6279d0ea 35#include "devices.h"
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36
37/*
38 * NOR Flash
39 */
40static struct mtd_partition cns3420_nor_partitions[] = {
41 {
42 .name = "uboot",
43 .size = 0x00040000,
44 .offset = 0,
45 .mask_flags = MTD_WRITEABLE,
46 }, {
47 .name = "kernel",
48 .size = 0x004C0000,
49 .offset = MTDPART_OFS_APPEND,
50 }, {
51 .name = "filesystem",
52 .size = 0x7000000,
53 .offset = MTDPART_OFS_APPEND,
54 }, {
55 .name = "filesystem2",
56 .size = 0x0AE0000,
57 .offset = MTDPART_OFS_APPEND,
58 }, {
59 .name = "ubootenv",
60 .size = MTDPART_SIZ_FULL,
61 .offset = MTDPART_OFS_APPEND,
62 },
63};
64
65static struct physmap_flash_data cns3420_nor_pdata = {
66 .width = 2,
67 .parts = cns3420_nor_partitions,
68 .nr_parts = ARRAY_SIZE(cns3420_nor_partitions),
69};
70
71static struct resource cns3420_nor_res = {
72 .start = CNS3XXX_FLASH_BASE,
73 .end = CNS3XXX_FLASH_BASE + SZ_128M - 1,
74 .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
75};
76
77static struct platform_device cns3420_nor_pdev = {
78 .name = "physmap-flash",
79 .id = 0,
80 .resource = &cns3420_nor_res,
81 .num_resources = 1,
82 .dev = {
83 .platform_data = &cns3420_nor_pdata,
84 },
85};
86
87/*
88 * UART
89 */
90static void __init cns3420_early_serial_setup(void)
91{
92#ifdef CONFIG_SERIAL_8250_CONSOLE
93 static struct uart_port cns3420_serial_port = {
94 .membase = (void __iomem *)CNS3XXX_UART0_BASE_VIRT,
95 .mapbase = CNS3XXX_UART0_BASE,
96 .irq = IRQ_CNS3XXX_UART0,
97 .iotype = UPIO_MEM,
98 .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
99 .regshift = 2,
100 .uartclk = 24000000,
101 .line = 0,
102 .type = PORT_16550A,
103 .fifosize = 16,
104 };
105
106 early_serial_setup(&cns3420_serial_port);
107#endif
108}
109
110/*
111 * Initialization
112 */
113static struct platform_device *cns3420_pdevs[] __initdata = {
114 &cns3420_nor_pdev,
115};
116
117static void __init cns3420_init(void)
118{
119 platform_add_devices(cns3420_pdevs, ARRAY_SIZE(cns3420_pdevs));
120
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121 cns3xxx_sdhci_init();
122
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123 pm_power_off = cns3xxx_power_off;
124}
125
126static struct map_desc cns3420_io_desc[] __initdata = {
127 {
128 .virtual = CNS3XXX_UART0_BASE_VIRT,
129 .pfn = __phys_to_pfn(CNS3XXX_UART0_BASE),
130 .length = SZ_4K,
131 .type = MT_DEVICE,
132 },
133};
134
135static void __init cns3420_map_io(void)
136{
137 cns3xxx_map_io();
138 iotable_init(cns3420_io_desc, ARRAY_SIZE(cns3420_io_desc));
139
140 cns3420_early_serial_setup();
141}
142
143MACHINE_START(CNS3420VB, "Cavium Networks CNS3420 Validation Board")
144 .phys_io = CNS3XXX_UART0_BASE,
145 .io_pg_offst = (CNS3XXX_UART0_BASE_VIRT >> 18) & 0xfffc,
146 .boot_params = 0x00000100,
147 .map_io = cns3420_map_io,
148 .init_irq = cns3xxx_init_irq,
149 .timer = &cns3xxx_timer,
150 .init_machine = cns3420_init,
151MACHINE_END
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