[deliverable/linux.git] / arch / arm / mach-cns3xxx / pm.c

/*
 * Copyright 2008 Cavium Networks
 *
 * This file is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License, Version 2, as
 * published by the Free Software Foundation.
 */

#include <linux/init.h>
#include <linux/module.h>
#include <linux/io.h>
#include <linux/delay.h>
#include <mach/system.h>
#include <mach/cns3xxx.h>
#include <mach/pm.h>

void cns3xxx_pwr_clk_en(unsigned int block)
{
	u32 reg = __raw_readl(PM_CLK_GATE_REG);

	reg |= (block & PM_CLK_GATE_REG_MASK);
	__raw_writel(reg, PM_CLK_GATE_REG);
}
EXPORT_SYMBOL(cns3xxx_pwr_clk_en);

void cns3xxx_pwr_clk_dis(unsigned int block)
{
	u32 reg = __raw_readl(PM_CLK_GATE_REG);

	reg &= ~(block & PM_CLK_GATE_REG_MASK);
	__raw_writel(reg, PM_CLK_GATE_REG);
}
EXPORT_SYMBOL(cns3xxx_pwr_clk_dis);

void cns3xxx_pwr_power_up(unsigned int block)
{
	u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG);

	reg &= ~(block & CNS3XXX_PWR_PLL_ALL);
	__raw_writel(reg, PM_PLL_HM_PD_CTRL_REG);

	/* Wait for 300us for the PLL output clock locked. */
	udelay(300);
};
EXPORT_SYMBOL(cns3xxx_pwr_power_up);

void cns3xxx_pwr_power_down(unsigned int block)
{
	u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG);

	/* write '1' to power down */
	reg |= (block & CNS3XXX_PWR_PLL_ALL);
	__raw_writel(reg, PM_PLL_HM_PD_CTRL_REG);
};
EXPORT_SYMBOL(cns3xxx_pwr_power_down);

static void cns3xxx_pwr_soft_rst_force(unsigned int block)
{
	u32 reg = __raw_readl(PM_SOFT_RST_REG);

	/*
	 * bit 0, 28, 29 => program low to reset,
	 * the other else program low and then high
	 */
	if (block & 0x30000001) {
		reg &= ~(block & PM_SOFT_RST_REG_MASK);
	} else {
		reg &= ~(block & PM_SOFT_RST_REG_MASK);
		__raw_writel(reg, PM_SOFT_RST_REG);
		reg |= (block & PM_SOFT_RST_REG_MASK);
	}

	__raw_writel(reg, PM_SOFT_RST_REG);
}
EXPORT_SYMBOL(cns3xxx_pwr_soft_rst_force);

void cns3xxx_pwr_soft_rst(unsigned int block)
{
	static unsigned int soft_reset;

	if (soft_reset & block) {
		/* SPI/I2C/GPIO use the same block, reset once. */
		return;
	} else {
		soft_reset |= block;
	}
	cns3xxx_pwr_soft_rst_force(block);
}
EXPORT_SYMBOL(cns3xxx_pwr_soft_rst);

void arch_reset(char mode, const char *cmd)
{
	/*
	 * To reset, we hit the on-board reset register
	 * in the system FPGA.
	 */
	cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(GLOBAL));
}

/*
 * cns3xxx_cpu_clock - return CPU/L2 clock
 *  aclk: cpu clock/2
 *  hclk: cpu clock/4
 *  pclk: cpu clock/8
 */
int cns3xxx_cpu_clock(void)
{
	u32 reg = __raw_readl(PM_CLK_CTRL_REG);
	int cpu;
	int cpu_sel;
	int div_sel;

	cpu_sel = (reg >> PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL) & 0xf;
	div_sel = (reg >> PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV) & 0x3;

	cpu = (300 + ((cpu_sel / 3) * 100) + ((cpu_sel % 3) * 33)) >> div_sel;

	return cpu;
}
EXPORT_SYMBOL(cns3xxx_cpu_clock);
Commit	Line	Data
d94f944e AV	1	/*
	2	* Copyright 2008 Cavium Networks
	3	*
	4	* This file is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License, Version 2, as
	6	* published by the Free Software Foundation.
	7	*/
	8
38e64ba0 ML	9	#include <linux/init.h>
38e64ba0 ML	10	#include <linux/module.h>
6eb5d146	11	#include <linux/io.h>
d94f944e AV	12	#include <linux/delay.h>
	13	#include <mach/system.h>
	14	#include <mach/cns3xxx.h>
38e64ba0	15	#include <mach/pm.h>
d94f944e AV	16
	17	void cns3xxx_pwr_clk_en(unsigned int block)
	18	{
6eb5d146 AV	19	u32 reg = __raw_readl(PM_CLK_GATE_REG);
	20
	21	reg \|= (block & PM_CLK_GATE_REG_MASK);
	22	__raw_writel(reg, PM_CLK_GATE_REG);
d94f944e	23	}
38e64ba0 ML	24	EXPORT_SYMBOL(cns3xxx_pwr_clk_en);
	25
	26	void cns3xxx_pwr_clk_dis(unsigned int block)
	27	{
	28	u32 reg = __raw_readl(PM_CLK_GATE_REG);
	29
	30	reg &= ~(block & PM_CLK_GATE_REG_MASK);
	31	__raw_writel(reg, PM_CLK_GATE_REG);
	32	}
	33	EXPORT_SYMBOL(cns3xxx_pwr_clk_dis);
d94f944e AV	34
	35	void cns3xxx_pwr_power_up(unsigned int block)
	36	{
6eb5d146 AV	37	u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG);
	38
	39	reg &= ~(block & CNS3XXX_PWR_PLL_ALL);
	40	__raw_writel(reg, PM_PLL_HM_PD_CTRL_REG);
d94f944e AV	41
	42	/* Wait for 300us for the PLL output clock locked. */
	43	udelay(300);
	44	};
38e64ba0	45	EXPORT_SYMBOL(cns3xxx_pwr_power_up);
d94f944e AV	46
	47	void cns3xxx_pwr_power_down(unsigned int block)
	48	{
6eb5d146 AV	49	u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG);
6eb5d146 AV	50
d94f944e	51	/* write '1' to power down */
6eb5d146 AV	52	reg \|= (block & CNS3XXX_PWR_PLL_ALL);
6eb5d146 AV	53	__raw_writel(reg, PM_PLL_HM_PD_CTRL_REG);
d94f944e	54	};
38e64ba0	55	EXPORT_SYMBOL(cns3xxx_pwr_power_down);
d94f944e AV	56
	57	static void cns3xxx_pwr_soft_rst_force(unsigned int block)
	58	{
6eb5d146 AV	59	u32 reg = __raw_readl(PM_SOFT_RST_REG);
6eb5d146 AV	60
d94f944e AV	61	/*
	62	* bit 0, 28, 29 => program low to reset,
	63	* the other else program low and then high
	64	*/
	65	if (block & 0x30000001) {
6eb5d146	66	reg &= ~(block & PM_SOFT_RST_REG_MASK);
d94f944e	67	} else {
6eb5d146	68	reg &= ~(block & PM_SOFT_RST_REG_MASK);
df8f4d2f	69	__raw_writel(reg, PM_SOFT_RST_REG);
6eb5d146	70	reg \|= (block & PM_SOFT_RST_REG_MASK);
d94f944e	71	}
6eb5d146 AV	72
6eb5d146 AV	73	__raw_writel(reg, PM_SOFT_RST_REG);
d94f944e	74	}
38e64ba0	75	EXPORT_SYMBOL(cns3xxx_pwr_soft_rst_force);
d94f944e AV	76
	77	void cns3xxx_pwr_soft_rst(unsigned int block)
	78	{
	79	static unsigned int soft_reset;
	80
	81	if (soft_reset & block) {
	82	/* SPI/I2C/GPIO use the same block, reset once. */
	83	return;
	84	} else {
	85	soft_reset \|= block;
	86	}
	87	cns3xxx_pwr_soft_rst_force(block);
	88	}
38e64ba0	89	EXPORT_SYMBOL(cns3xxx_pwr_soft_rst);
d94f944e AV	90
	91	void arch_reset(char mode, const char *cmd)
	92	{
	93	/*
	94	* To reset, we hit the on-board reset register
	95	* in the system FPGA.
	96	*/
	97	cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(GLOBAL));
	98	}
	99
	100	/*
	101	* cns3xxx_cpu_clock - return CPU/L2 clock
	102	* aclk: cpu clock/2
	103	* hclk: cpu clock/4
	104	* pclk: cpu clock/8
	105	*/
	106	int cns3xxx_cpu_clock(void)
	107	{
6eb5d146	108	u32 reg = __raw_readl(PM_CLK_CTRL_REG);
d94f944e AV	109	int cpu;
	110	int cpu_sel;
	111	int div_sel;
	112
6eb5d146 AV	113	cpu_sel = (reg >> PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL) & 0xf;
6eb5d146 AV	114	div_sel = (reg >> PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV) & 0x3;
d94f944e AV	115
	116	cpu = (300 + ((cpu_sel / 3) * 100) + ((cpu_sel % 3) * 33)) >> div_sel;
	117
	118	return cpu;
	119	}
38e64ba0	120	EXPORT_SYMBOL(cns3xxx_cpu_clock);